Computer Organisation and Architecture (May 2017)
KTU
B.TECH - FOURTH SEMESTER EXAMINATION, MAY-2017
COMPUTER ORGANISATION AND ARCHITECTURE
Time: 3 Hours
PART-A
Note: Answer all questions. Each carries 3 marks.
Ques 1) Write notes on condition codes. (03)
Ans: Condition Code
The condition code flags are used to store the results of
certain condition when certain operations are performed
during execution of the program. The condition code flags
are stored in the status registers. The status register is also
referred to as flag register.
ALU operations and certain register operations may set or
reset one or more bits in the status register. Status bits lead
to a new set of microprocessor instructions. These
instructions permit the execution of a program to change
flow on the basis of the condition of bits in the status
register. So the condition bits in the status register can be
used to take logical decision within the program. Some of
the common condition code flags are:
1) Carry/Borrow
2) Zero
3) Negative/Sign
4) Auxiliary Carry
5) Overflow flag
6) Parity
Refer Unit-5 Question No.- 5 Page No.-61
Ques 2) Explain indirect addressing with an example.
(03)
Ans: Indirect Addressing
Refer Unit-1 Question No.- 16 Page No.-16
Ques 3) Draw the flow chart for Booths Multiplication
algorithm. (03)
Ans: Flowchart for Booths Multiplication Algorithm
Refer Unit-2 Question No.- 18 Page No.-30
Ques 4) Explain the process of storing a word in
memory using a single bus organisation. Specify which
all control signals will be activated. (03)
Ans: Process of Storing a Word in Memory
Refer Unit-2 Question No.- 5 Page No.-24-25
* *
1
Max. Marks: 100
PART-B
Note: Answer any two question. Each carries 9 marks.
Ques 5 a) Briefly explain the memory access
instruction and addressing modes of ARM processor.
(04)
Ans: Memory Access Instructions of ARM
1) LDR and STR (immediate offset): Load and Store
with immediate offset, pre-indexed immediate offset,
or post-indexed immediate offset.
2) LDR and STR (register offset): Load and Store with
register offset, pre-indexed register offset, or post-
indexed register offset.
3) LDR and STR, unprivileged: Load and Store, with
User mode privilege.
4) LDR (PC-relative) The address is an offset from the
PC.
5) LDR (register-relative): The address is an offset
from a base register.
6) ADR (PC-relative): Load a PC-relative address.
7) ADR (register-relative): Load a register-relative
address.
8) PLD, PLDW, and PLI: Preload an address for the
future.
9) LDM and STM: Load and Store Multiple Registers.
10) PUSH and POP: Push low registers, and optionally
the LR, onto the stack. Pop low registers, and
optionally the PC, off the stack.
11) RFE: Return From Exception.
12) ERET: Exception Return.
13) SRS: Store Return State.
14) LDREX and STREX: Load and Store Register
Exclusive.
15) CLREX: Clear Exclusive.
16) SWP and SWPB: Swap data between registers and
memory.
Addressing Modes of ARM
This section summarizes the modes used for addressing
instruction operands. ARM uses four main modes:
register, immediate, base, and PC-relative addressing.
Most other architectures provide similar addressing
2 Computer Organisation and Architecture (KTU) Solved Paper

modes, so understanding these modes helps you easily memory location, and the processor stack grows toward
learn other assembly languages. Register and base lower addresses, it is possible that too many PUSH or
addressing have several submodes described below. The CALL operations without a sufficient number of
first three modes (register, immediate, and base intervening POP or RET operations result in the overflow
addressing) define modes of reading and writing operands. of stack. For example, assume that read/write memory
The last mode (PC-relative addressing) defines a mode of allocated in the system for stack has address range from
writing the program counter (PC). Table 1 summarizes 2000H to 27FFH. In this case, if stack grows beyond
and gives examples of each addressing mode. 2000H then it is called overflow of stack. Care must be
taken in memory allocation and program design to prevent
Data-processing instructions use register or immediate this.
addressing, in which the first source operand is a register
and the second is a register or immediate, respectively. Stack Frame
ARM allows the second register to be optionally shifted by The stack can be used to pass the parameters. The main
an amount specified in an immediate or a third register. program places the parameters on the stack by using
Memory instructions use base addressing, in which the PUSH instructions. These parameters together with return
base address comes from a register and the offset comes addresses are stored on the stack, which is called stack
from an immediate, a register, or a register shifted by an frame. The stack frame is shown in figure 1.
immediate. Branches use PC-relative addressing in which
the branch target address is computed by adding an offset The subroutine pops the return address from the stack and
to PC + 8. saves it in internal register or reserved memory location.
The subroutine pops the parameters from the stack as
Table 1: ARM operand addressing modes needed. When all the parameters are removed and
Operand Addressing Example Description processed, the subroutine pushes the return address back
Mode onto the stack and executes a return instruction.
Register
Register-only ADD R3, R2, R3 R2 + R1 Main Subroutine
R1 PUSH B POP H
Immediate-shifted SUB R4, R5, R4 R5 (R9 >> PUSH D SHLD Address
register R9, LSR #2 2)
PUSH H :
Register-shifted 0RR R0, R10, R0 R10 | (R2
register R2, ROR R7 R0R R7) CALL Sub :
Immediate SUB R3, R2, R3 R2 25 ADD B LHLD Address
#25 : PUSH H
Base : RET
Immediate offset STR R6, [R11, mem [R11+77]
#77) R6
Register offset LDR R12, [R1, R12 mem[R1
R5] R5]
Immediate-shifted LDR R8, [R9, R8 mem[R9 +
register offset R2, LSL #2) (R2 << 2)]
AddrL
PC-Relative B LABEL1 Branch to
LABEL1 SP 6 AddrH

Ques 5 b) Write notes on multiple bus organisation. SP 6 6

(05) SP 5 5

Ans: Multiple Bus Organisation SP 4 4

SP 3 3
Refer Unit-2 Question No.- 8 Page No.-26
SP 2 2
Ques 6) Explain the terms processor stack, stack frame
SP 1 1
and frame pointer with relation to subroutine
processing. Use a relevant example. (09) SP

Ans: Processor Stack Figure 1: Parameter Passing Using Stack

The stack portion pointed by the stack pointer is also
called processor stack. The level of subroutine nesting Frame Pointer
cannot exceed the level supported by the available Some microprocessor have a dedicated register for
processor stack in the system. Since the stack pointer is managing the stack frame, the register is referred to as the
usually initialised to the highest available read/write frame pointer.
* *
Computer Organisation and Architecture (May 2017) 3

The frame pointer keeps track of the fixed base address of Part-C
the current stack frame; this allows to the stack frame
content using a fixed offset. Note: Answer all questions. Each carries 3 marks.

Ques 7) Draw and explain the flow charts for floating Ques 8) Differentiate between programmed I/O and
point multiplication and division. (09) interrupt driven I/O. (03)

Ans: Floating Point Multiplication Ans: Difference between Programmed I/O and
Interrupt Driven I/O
Multiply
Refer Unit-3 Question No.- 10 Page No.-44
No No Ques 9) Define the terms: (03)
x = 0? x = 0? Add
Exponents i) Latency
Yes Yes
ii) Bandwidth
z0 Subtract Bias iii) Memory cycle time

RETURN Ans: Latency

Exponent Yes Report
overflow?
Refer Unit-4 Question No.- 1 Page No.-49
Overflow

No Bandwidth
Refer Unit-4 Question No.- 1 Page No.-49
Exponent Yes Report
Underflow? Underflow
Memory Cycle Time
No Refer Unit-4 Question No.- 1 Page No.-49
Multiply
Significands Ques 10) Why do dynamic RAMs need constant
refreshing? How is this done? (03)
Normalise
Ans: Need of Refreshing to Dynamic Memory
Refer Unit-4 Question No.- 8 Page No.-52-53
Round RETURN

Ques 11) Explain Direct Memory Access. What is burst

mode DMA? (03)
Floating Point Division
DIVIDE Ans: DMA
Refer Unit-3 Question No.- 11 Page No.-44

x = 0? No No
x = 0? Subtract Burst Mode DMA
Exponents
Yes Yes
Refer Unit-3 Question No.- 11 Page No.-44
z 0 z Add Bias Part-D

RETURN Note: Answer any Two questions. Each carries 9

Exponent Yes Report marks.
overflow? Overflow
Ques 12 a) Distinguish between centralised and
No distributed bus arbitration? (04)

Exponent Yes Report Ans: Difference between Centralised and Distributed

Underflow? Underflow Bus Arbitration
No 1) Centralised Arbitration
i) Single hardware device controlling bus access
Divide
Significands Bus Controller/Arbiter
ii) May be part of CPU or separate
Normalise
2) Distributed Arbitration
i) Each module may claim the bus
Round RETURN ii) Access control logic is on all modules
iii) Modules work together to control bus

* *
4 Computer Organisation and Architecture (KTU) Solved Paper
Ques 12 b) Write notes on set associative cache
mapping. (05)
Ans: Set Associative Cache Mapping
Refer Unit-4 Question No.- 16 Page No.-56-58
Ques 13 a) Distinguish between synchronous and
asynchronous DRAMs. (04)
Ans: Difference between Synchronous and
Asynchronous DRAM
Let us conclude by saying that in terms of the basic
technology and principle of operation of a basic DRAM
memory cell, both types are the same, but the SDRAM
scores higher only because of the way it is used. Since
asynchronous DRAM does not share any sort of common
clock signal with the CPU and chipset, the chipset has to
manipulate the DRAMs control pins based on all sorts of
timing considerations. SDRAM, however, shares the bus
clock with the CPU. Commands can be placed (or certain
predefined combinations of signals) on its control pins on
the rising clock edge.
Ques 13 b) Explain the important Data transfer signals
on the PCI bus. (05)
Ans: Data Transfer Signals on PCI Bus
Table 2: Data transfer signals on the PCI bus
Name Function
CLK A 33-MHz or 66-MHz clock.
FRAME# Sent by the initiator to indicate the duration of a
transaction.
AD 32 address/data lines, which may be optionally
increased to 64.
C/BE# 4 command/byte-enable lines (8 for a 64-bit
bus).
IRDY#, Initiator-ready and Target-ready signals.
TRDY#
DEVSEL# A response from the device indicating that it has
recognised its address and is ready for a data
transfer transaction.
IDSEL# Initialisation Device Select
Ques 14 a) Describe the different type of ROMs.
Ans: Types of ROM
1) PROM: PROM stands for Programmable Read
Only Memory. Even though the users do not have the
authority to manipulate the firmware yet they can
customize the system. For customization, they have to
convert the programs into micro programs and store
them into the ROM with the help of PROM-programs.
Like a ROM, once a PROM is programmed, its
contents cannot be altered.
2) EPROM: EPROM is the abbreviation of Erasable
Programmable Read Only Memory. EPROM has
the facility to erase and re-program the stored
information.
* *
All this can be done by exposing the chip to
ultraviolet light for certain period. It is non-volatile
memory. One cannot modify or re-program it until all
current information has been completely erased.
3) EEPROM: EEPROM stands for Electrically
Erasable Programmable Read-Only Memory. It is
also non-volatile memory developed in mid-1970s.
An electronic circuitry is used in EEPROM for
erasing and reprogramming.
It is like EPROM except that a high voltage electrical
pulse is used in place of ultraviolet light for erasing
EEPROMs content.
4) EAROM: EAROM is an acronym for Electrically
Alterable Read-Only Memory.
It is a type of memory that combines the
characteristics of RAM and read-only memory. It is
non-volatile, like read-only memory, but can be
written into by the processor. It can only be re-
programmed a limited number of times. It is a
specialised read-only memory with a special slow-write
cycle and a much faster read cycle, used with
microprocessors and microcomputers.
Ques 14 b) Explain the procedure and the packets used
for an output transfer in USB interface. (05)
Ans:
All information transferred over th USB in organised in
packets, where a packet consists of one or more bytes of
information. There are many types of packets that perform
a variety of control functions.
The information transferred on the USB can be divided
into two broad categories:
1) Control Packets: It performs such tasks as
addressing a device to initiate data transfer,
acknowledging that data have been received correctly
or indicating in error.
2) Data Packets: It carry information that is delivered to
a device; for example, input and output data are
transferred inside data packets.
(04)
When the software requires data transfer to occur between
itself and the USB, it sends a block of data called an I/O
Request Packet (IRP) to the appropriate pipe, and the
software is later notified when this request is completed
successfully or terminated by error. Other than the
presence of an IRP request, the pipe has no interaction
with the USB. In the event of an error after three retry
attempts, the IRP is cancelled and all further and
outstanding IRPs to that pipe are ignored until the software
responds to the error signal that is generated by sending an
appropriate call to the USB. How exactly this is handled
depends upon the type of device and the software.
As suggested by the name Universal Serial Bus, data
transmission in the bus occurs in a serial form. Bytes of
data are broken up and sent along the bus one bit at a time,
with the least significant bit first.
Computer Organisation and Architecture (May 2017) 5

The actual data is sent across the bus in packets. Each Ques 16) Design a 4bit Arithmetic unit which performs
packet is a bundle of data along with information the following operations on two inputs. A and B,
concerning the source, destination and length of the data, controlled by selection variables s1, and s0, and input
and also error detection information. Since each endpoint carry Cin: (10)
sets, during configuration, a limit to the size of the packet
it can handle, an IRP may require several packets to be S1 S0 Cin = 0 Cin = 1
sent. 0 0 F=A F=A+1
0 1 F=A+B F=A+B+1
Each of these packets should be the maximum possible 1 0 F = A + B F = A + B + 1
size except for the final packet. The USB host has a built 1 1 F=A1 F=A
in mechanism so that the software can tell it when to
expect full sized packets. Ques 17 a) Write notes on status register. (05)

PART-E Ans: Status Register

Note: Answer any Four questions. Each carries 10 Refer Unit-5 Question No.- 3 Page No.-61
marks.
Ques 15) Describe processor organisation with Ques 17 b) Distinguish between horizontal and vertical
diagram using: (10) microinstructions. (05)
i) Scratchpad memory. Ans: Difference between Horizontal and Vertical
ii) Two port memory. Microinstruction

Ans: Processor Organisation Using Scratchpad Refer Unit-6 Question No.- 6 Page No.-88-89
Memory and Two Port Memory Horizontal Vertical
Long formats Short formats
Ability to express a high Limited Ability to express
degree of parallelism parallelism microoperations
A address Scratchpad B address Little encoding of the Considerable encoding of the
memory control information control information
WE ME Memory Useful when higher Slower operating speed
enable operating speed is desired

Ques 18) What is the significance of a micro program

A B
CP
ALU and Shifter
Figure 2: Processor Unit with a 2-Port Memory
The organisation of a processor unit with a 2-port
scratchpad memory is shown in figure 2. The memory has
two sets of addresses, one for port A and the other for port
B. Data from any word in memory are read into the A
register by specifying an A address. Likewise, data from
any word in memory are read into the B register by
specifying a B address. The same address can be applied
to the A address and the B address, in which case the
identical word will appear in both A and B registers. When
enabled by the Memory Enable (ME) input, new data can
be written into the word specified by the B address. Thus
the A and B addresses specify two source registers
simultaneously, and the B address always specifies the
destination register. Figure 2 does not show a path for
external input and output data, but they can be included as
in previous organisations.
sequencer? Explain its working with the help of a
diagram. (10)
Ans: Significance of Micro Program Sequencer
The purpose of a microprogram sequencer is to present an
address to the control memory so that a microinstruction
may be read and executed. The function performed by a
microprogram sequencer is to determine the order in
which the microinstructions are fetched from the control
store. It is desirable to have features such that the total
amount of control storage required is minimized for any
given application consistent with speed and ease of use. A
sequencer is proposed which is believed to satisfy a broad
range of applications.
Working of Micro Program Sequencer
The block diagram of the microprogram sequencer is
shown in figure 3. The control memory is included in the
diagram to show the interaction between the sequencer
and the memory attached to it. There are two multiplexers
in the circuit. The first multiplexer selects an address from
one of four sources and routes it into a control address
register CAR. The second multiplexer tests the value of a
selected status bit and the result of the test is applied to an
input logic circuit. The output from CAR provides the
address for the control memory.

* *
6 Computer Organisation and Architecture (KTU) Solved Paper

The content of CAR is incremented and applied to one of the multiplexer inputs and to the subroutine registers SBR.
The other three inputs to multiplexer number 1 come from the address field of the present microinstruction, from the output
of SBR, and from an external source that maps the instruction. Although the diagram shows a single subroutine register, a
typical sequencer will have a register stack about four to eight levels deep. In this way, a number of subroutines can be
active at the same time. A push and pop operation, in conjunction with a stack pointer, stores and retrieves the return
address during the call and return microinstructions.
The CD (condition) field of the microinstruction selects one of the status bits in the second multiplexer. If the bit selected
is equal to 1, the T(test) variable is equal to 1; otherwise, it is equal to 0. The T value together with the two bits from the
BR (branch) field go to an input logic circuit. The input logic in a particular sequencer will determine the type of
operations that are available in the unit. Typical sequencer operations are: increment, branch or jump, call and return from
subroutine, load an external address, push or pop the stack, and other address sequencing operations. With three inputs, the
sequencer can provide up to eight address sequencing operation. Some commercial sequencers have three or four inputs in
addition to the T input and thus provide a wider range of operations.
The input logic circuit in figure 7-8 has three inputs, I0, I1, and T, and three outputs, S0, S1, and L. Variables S0 and S1
select one of the source addresses for CAR. Variable L enables the load input in SBR. The binary values of the two
selection variables determine the path in the multiplexer. For example, with S1, S0 = 10, multiplexer input number 2 is
selected and establishes a transfer path from SBR to CAR. Note that each of the four inputs as well as the output of MUX 1
contains a 7-bit address.
External
(MAP)

l0Input logic 3 2 1 0
Load
l1 S1 MUX-1 SBR
T S0

1 MUX-2 Test Incrementer

l
S Select
Z
Clock CAR

Control Memory

Microops CD BR AD

Figure 3: Microprogram Sequencer for a Control Memory

The truth table for the input logic circuit is shown in table 3. Inputs I and I0 are identical to the bit values in the BR field.
the bit values for S1 and S0 are determined from the stated function and the path in the multiplexer that establishes the
required transfer. The subroutine register is loaded with the incremented value of CAR during a call microinstruction (BR
= 01) provided that the status bi-condition is satified (T = 1). The truth table can be used to obtain the simplified Boolean
functions for the input logic circuit:
S1 = I1
S0 = I1 I0 + I1 T
L = I1 I 0 T

* *
Computer Organisation and Architecture (May 2017) 7

Table 3: Input Logic Truth Table for Microprogram Sequencer

Input MUX 1 Load SBR
BR Field
I1 I0 T S1 S0 L
0 0 0 0 0 0 0 0
0 0 0 0 1 0 1 0
0 1 0 1 0 0 0 0
0 1 0 1 1 1 1 1
1 0 1 0 1 0 0
1 1 1 1 1 1 0
The circuit can be constructed with three AND gates, an OR gate, and an inverter.
Ques 19) Explain micro programmed CPU organisation with the help of a diagram. (10)
Ans: Micro Programmed CPU Organisation
Refer Unit-6 Question No.- 5 Page No.-87-88
Ques 20) With the help of a block diagram, describe a complete processor unit with all components and appropriate
control variables. Show with an example, how a control word for the processor can be defined. (10)
Ans: Complete Processor Unit
The figure 4 shows the block diagram of processor unit with selection variables. These selection variables control the
micro-operations executed within the processor. As shown in the figure 4, the selection variables control the source for A
bus, the source for B bus, ALU function, shifter operation and destination register. A and B inputs of ALU have eight
possible input sources: seven from R0 to R6 and one external input. Two 8 : 1 multiplexers are used to select the desired
source for ALU. The 3-bit field A and 3-bit field B of control word is used to select a source for A and B inputs of ALU,
respectively. The output of the ALU goes either to output data or to the destination register through the shifter. The D field
selects the destination register. The F field, together with the bit Cin, selects a function for the ALU and the SH field selects
the type of shift operation to be performed by the shifter. Input data

Registers
R0 to R6

0 6 7 0 6 7 0
6 3
Destination 8:1 8:1
D 7 B 4 MUX MUX 1 A
select
8 5 BUS A select BUS B select 2

Status register 9
10 F
V Z S C ALU
11
Cin(12)

13
14 SH
Shifter
15

Output data
(a) Block Diagram of Processor Unit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SH Cin F D B A
(b) Control Word of Processor Unit
*
Figure 4 *
8 Computer Organisation and Architecture (KTU) Solved Paper

The Table lists the functions of all selection variables. The table also gives the 3-bit binary code for each of the five fields
A, B, D, F and SH.

Table 4: Function of control variables for the processor

Binary Function of selection variables
Code A B D F with Cin = 0 F with Cin = 1 SH
000 R0 R0 R0 A, C 0 A+1 No Shift
001 R1 R1 R1 A+B A+B+1 Shift right, IR = 0
010 R2 R2 R2 AB1 AB Shift left, IL = 0
011 R3 R3 R3 A1 A, C 1 0s to output bus
100 R4 R4 R4 AB
101 R5 R5 R5 AB Rotate left with C
110 R6 R6 R6 AB Rotate right with C
111 Input Data Input Data None A

All selection variable collectively forms the 16-bit control word shown in Figure 4 (b). This control word is used to
specify a micro-operation for the processor unit. The Table 5 list some examples of micro-operations and corresponding
control word for processor.

Table 5: Examples of micro-operations for processor

Micro-operation Control word Code in Hex Function
BH Cin F D B A
R0 R1 + R2 000 0 001 000 010 001 0211 Add R1 and and R2 and store result in R0
R2 R1 000 1 010 111 001 010 15CA Compare R2 and R1
R5 R2 000 0 000 101 111 101 017D Transfer R2 to R5
R2 0 011 0 000 011 000 000 60C0 Clear R3
R4 Shl R4 010 0 000 100 111 100 413C Shift left R4 with lL = 0
R6 RR R6 110 0 100 110 110 110 C9B6 Rotate right R6 with carry

* *