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To use a logic voltage other than 5V,
remove JMP1 and connect the supply
voltage to the VDD test point.
OUT IN
GND GND
JMP1 GND GND
C12 10uF C11 0.1uF
N/C N/C
A J1 A
U2 PGND
VDD C1 C2
VDD
C4 0.1uF D1
1000uF 1000uF
R1 GH_A
Q1
C5 0.1uF C6 47.5 PGND PGND PGND
R7
0.68uF
VBB 470k
R2 GH_B
Q2
C7 47.5
R8
0.47uF
25
26
27 GHA 1 2 470k
4
SLUG
GND
GND R24 13 R4 GL_A
Q4
GLC
CN2 12 GLB 9 10
40.2k LSS GLB_IN GLB_OUT
47.5
GLC 15 16 R10
28
29
1 HA GLC_IN GLC_OUT
2 HC
CN4 470k
3 HB R5 GL_B
Q5
4
C PGND 47.5 C
CN3 VDD R11
R15
470k
R6 GL_C
Q6
FAULT
1k
47.5
LED1 R12
470k
LSS LSSEXT
R13 0 R14 0
PGND PGND
Title
D Board, Demo, A4915 D
W1 W2 Size Number Revision
85-00561-000-SCH 2
A
A4915-DB
Date: 1/13/2012 Sheet 1 of 1
File: C:\altium\..\A4915Rev2.SchDoc Drawn By: Bob Pickett
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A4915 Demo Board Schematic/Layout
LAYOUT
A4915Rev2.zip
Layer: A4915Rev2.GTO
16 Jan 2012,09:12 AM
A4915Rev2.zip
Layer: A4915Rev2.GTL
16 Jan 2012,09:12 AM
A4915Rev2.zip
Layer: A4915Rev2.GBL
16 Jan 2012,09:12 AM
A4915Rev2.zip
Layer: A4915Rev2.GBO
16 Jan 2012,09:12 AM
BOARD,DEMO,A4915
BILL OF MATERIALS
85-0561-000-BOM Rev. 3
All Devices MUST be ROHS Compliant
Page 1 of 1
Bill of Materials 2/7/2012
Page 1
Revision History
Number Date Description
September 6, 2016 Initial release