Microprocessor systems

(EMISY)

Tomasz Starecki

1
Organization of the course

lectures: Tomasz Starecki

projects: Tomasz Starecki
labs: Tomasz Starecki, Mariusz Suchenek

consultation hours: Tuesday & Thursday 11:00-12:00 (room 269)

(except Faculty meetings once a month)
e-mail: tomasz@starecki.com

group representative?

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Getting credits for the course

function passing_the_course(test1, test2, last_chance_test,

project: real): boolean;

begin
if (((test1 + test2) >= 5.0) or (last_chance_test >= 2.5))
and (project >= 2.5)) then
passing_the_course := true
else
passing_the_course := false;
end;

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Tests

P two written tests (the first one in mid-semester, the second at

the end) - scored 0-5 points each (T1, T2)
P last chance test during first week of the session - for those
who failed the regular tests (average from the regular tests
below 2.5 point) or anybody who wants to improve the regular
tests -scored 0-5 points (LCT)
P test tasks are based on the lecture material - usually require
some basic knowledge + thinking
P final score for the tests (FTS) is calculated as:

FTS = MAX ( T 1+2T 2 ; LCT )

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Project

P individual topics
P teaching based on consultations
P proposed solution must be based on a '51 family
microcontroller (use of e.g. AVR will result in failing the
project)
P project score (PS) is based on project report (max. 5 points)
P deadline for the project reports - one week before the last
lecture, 12:00 noon
P for being late: minus 0.5 point from the project score for every
started working day (counting from the deadline)

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Project report contents

detailed circuit diagram

P values/types of all the components must be given on the
circuit diagram
P no black boxes allowed
P power supplies don't have to be designed, i.e. can be
assumed as given (excluding "Programmable power supply"
topic), but reference voltages must be designed in details
P labels
analysis of the project
P commercial application approach
P discussion of the project assumptions
P discussion of the solution (showing way of thinking when
designing rather than being just a description of the
circuit diagram) 2
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Labs

P two options: stationary labs or work with the labkits taken out
P individual topics
P all the labkits are based on '51 family microcontrollers
P simple program written in assembler
P it is possible to pass the course with the labs failed, but score
for the labs has impact on the final score for the course
P the stationary labs start at about half of the semester
P score for the labs (LS) is plus/minus one or zero

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Final score for the course

function final_score(FTS, PS, LS: real): real;

var
temp: real;
begin
temp := Round(FTS + PS + 0.7 * LS);
{averaged tests + project + lab}
if ((FTS = 2.5) and (PS = 2.5)) then
temp := 6;
final_score := temp / 2.0;
end;

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Tomasz Starecki

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References (books)

1. J.W. Coffron, W.E. Long - Practical Interfacing Techniques

for Microprocessor Systems
2. J.W. Coffron - Getting Started with 8080, 8085, Z80, and
6800 Microprocessors
3. R.J. Tocci, N.S. Widmer - Digital Systems: Principles and
Applications
4. W. Kleitz - Digital and Microprocessor Fundamentals: Theory
and Applications
5. J. Uffenbeck - Microcomputers and Microprocessors: The
8080, 8085, and Z-80 Programming, Interfacing, and
Troubleshooting
6. J.W. Stewart, K.X. Miao - The 8051 Microcontroller:
Hardware, Software and Interfacing
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Other references

P Databooks (Analog Devices, Atmel, Cypress, Fairchild,

Freescale, Intel, Maxim/Dallas, Microchip, NXP, Silicon Labs,
Texas Instruments, Zilog, etc.)
P Application Notes
P EMISY bundle: http://www.ise.pw.edu.pl/impuls/emisy1.html

NOT RECOMMENDED (STRONGLY):

P Wikipedia
P amateur designs published on the Internet
P radio-amateur magazines
P etc.
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INTRODUCTION

Tomasz Starecki

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 Historical and "philosophical" background

P Intel 8008 in 1971

P rapid development (current PC = a bit older mainframe)
HENCE
P checking current technology is a must
P short time-to-market is often critical
BUT
P design philosophy remains relatively constant
P overloading with technology is not cost-efficient

Keep yourself up-to-dated with modern technology, but use it wisely

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Basic logic circuits

Gates
NAND
NOR
AND
OR
XOR
3-state
buffer (unidirectional), transceiver
flip-flop, latch, shift register (SIPO, PISO)
multiplexer, demultiplexer / decoder
counter

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3-bus architecture

Bus?

P address bus
P data bus
P control bus

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Internal architecture of a microprocessor /
microcontroller (simplified)

internal data bus

ROM+RAM+I/O
ALU registers
(optional)

internal address bus

internal control bus

timing
& control

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Microprocessor architecture
and control bus signals
Number of control bus signals and their functions depend on the
microprocessor - in particular on its architecture, e.g.:
P Z80, 8085 - separated I/O and memory address
space, common program and data memory address
space, Intel control signals convention
P 8051 - common I/O and data memory address
space, separated program memory address space,
Intel control signals convention
P 6800 - common address space for all devices,
Motorola control signals convention

All the above devices have von Neumann architecture

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Web-based concept of communication

www = what, where, when

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Intel and Motorola control signals conventions

Intel:
separate, negative strobes for write (WR) and read (RD)

Motorola:
control signal for operation mode - read/not write (R/W)
and positive enable (E) strobe

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Write operation timing (Motorola mode)

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Write operation timing (Intel mode)

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Read operation timing (Motorola mode)

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Read operation timing (Intel mode)

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ADDRESS DECODING

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Memory map

P describes assignment of individual memory and I/O resources

to the microprocessor address space
P helps in further hardware and firmware development
P is particularly useful in case of microprocessor systems
containing many memory chips and I/O devices

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Memory map example

P system based on Z80 microprocessor

P 32 KB of program memory (single 27C256 chip)
P 16 KB of data memory (two 6264 memory chips)

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Address decoding
ROM: 0000H - 7FFFH
RAM1: 8000H - 9FFFH
RAM2: 0A000H - 0BFFFH

0 = 0000B, 7 = 0111B (A15 = 0, A14 = X, A13 = X, A12 = X)

8 = 1000B, 9 = 1001B (A15 = 1, A14 = 0, A13 = 0, A12 = X)
A = 1010B, B = 1011B (A15 = 1, A14 = 0, A13 = 1, A12 = X)

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Partial address decoding

P simpler address decoding circuit

P must not result in address range overlaps

Step1:
RAM1: A15=1, A14=0, A13=0
RAM2: A15=1, A14=0, A13=1

Step2:
RAM1: A15=1, A14=0, A13=0
RAM2: A15=1, A14=1, A13=0

Step3:
RAM1: A15=1, A14=0, A13=X
RAM2: A15=1, A14=1, A13=X

Step2a ?

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Most common methods of address decoding
implementation

P gates
P direct control by address lines
P decoders / demultiplexers
P programmable chip selects
P programmable logic circuits (GALs) "0" A13
A13 "1"

A13
A14
A15

"1"
"0"
"0"

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Combined address decoding and control

Combined address
decoding and control is
used when the controlled
device has no chip select
inputs, eg. output registers,
input buffers, etc.

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Simple system with Z80
gates-based address decoding

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Simple system with Z80
decoder-based address decoding

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Bus multiplexing

latch
or
D flip-flop?

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Simple system with 8085
gates-based address decoding

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Simple system with 8085
decoder-based address decoding

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BUFFERING

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Buffering

Reasons for buffering:

P bus loading resulting from digital logic inputs connected to
the signal line
P capacitive bus loading
P interoperation of circuits powered from different supply
voltages
P separation of the signal lines from the external circuits
(expansion boards, etc.)

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Characteristics of the most common
digital logic families

IOH $ IIH1 + IIH2

IOL $ IIL1 + IIL2
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Insufficient driving capabilities example

driving capabilities of
8085A signal lines:

2.0 mA @ "0" (0.45 V)

400A @ "1" (2.4 V)

standard 74Fxx (NXP) input load: driving capabilities of

0.6 mA @ "0" 20A @ "1" digital I/O port lines of 80C51:

but e.g. OE input of 74F245: 1.6 mA @ "0" (0.45 V)

1.2 mA @ "0" 40A @ "1" 60A @ "1" (2.4 V)

It is not enough to check if the microprocessor driving capabilities

are sufficient. Every output in the system should be checked.
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Capacitive loading of the signal lines

PCB traces, connectors and even IC pins introduce capacitance

1 m of a cable . 100 pF
du du
I ' C '> d t ' C
dt I

2.0 V
30 pF ' 37.5 ns
1.6 mA

2.0 V
30 pF ' 1 s
60 A

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Output current driving capabilities of buffers

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The most common buffers/transceivers

DIR = "1": A => B

DIR = "0": A <= B
Note: Some latches / flip-flops (e.g. '573 / '574) have internal
output buffers. In such a case there is no need for additional
buffering.
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Interaction of circuits from different logic families

VOH $ VIH

VOL # VIL

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Interaction of logic circuits powered from
different voltages

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Simple system with Z80;
address bus and data bus buffered

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Simple system with Z80; address bus, data bus
and control signals buffered

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Simple system with 8085;
address bus and data bus buffered

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Simple system with 8085; address bus, data bus
and control signals buffered

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Simple system with 80C51

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TIME DEPENDENCIES

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Checking time dependencies
P determine connections between the circuits being checked
P get appropriate time charts from the datasheets
P find corresponding time markers on the time charts
P for each required time dependency define formulas describing
the same timing on both time charts
P from each pair of such formulas calculate value of the
parameter being analysed
P from all the calculated values select the one considered as the
worst case

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 Program memory timing example:
determination of connections

O 0..7 = PORT 0
OE = PSEN
CE = "0"
A 8..15 = PORT 2
A 0..7 = Q 0..7 (LATCH)
D 0..7 (LATCH) = PORT 0
C (LATCH) = ALE
OC (LATCH) = "0"

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Program memory timing example:
finding corresponding time markers

O 0..7 = PORT 0
OE = PSEN
CE = "0"
A 8..15 = PORT 2
A 0..7 = Q 0..7 (LATCH)
D 0..7 (LATCH) = PORT 0
C (LATCH) = ALE
OC (LATCH) = "0"

tACC = tAVIV
tOE = tPLIV
tOH = tPXIX
tDF = tPXIZ
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 Program memory timing example:
using microprocessor timing specifications

tACC = tAVIV = 5 tCK 105 [ns]

tOE = tPLIV = 3 tCK 105 [ns]
tOH = tPXIX = 0
tDF = tPXIZ = tCK 25 [ns]

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Program memory timing example:
finding appropriate memory
For fOSC = 10 MHz, tCK = 1/fOSC = 100 ns
For fOSC = 20 MHz, tCK = 1/fOSC = 50 ns
tACC = tAVIV = 5 tCK 105 [ns] = 500 105 = 395 [ns] = 250 105 = 145 [ns]
tOE = tPLIV = 3 tCK 105 [ns] = 300 105 = 195 [ns] = 150 105 = 45 [ns]
tOH = tPXIX = 0
tDF = tPXIZ = tCK 25 [ns] = 100 25 = 75 [ns] = 50 25 = 25 [ns]

tCE = tPLIV = 3 tCK 105 [ns] = 150 105 = 45 [ns]

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 Program memory timing example:
calculating maximum system clock frequency

tACC = tAVIV = 5 tCK 105 [ns] tCK = (tACC + 105) / 5 = (120 + 105) / 5 = 45 [ns]
tOE = tPLIV = 3 tCK 105 [ns] tCK = (tOE + 105) / 3 = (50 + 105) / 3 = 51.67 [ns]
tOH = tPXIX = 0
tDF = tPXIZ = tCK 25 [ns] tCK = tDF + 25 = 40 + 25 = 65 [ns]

The worst case is 65 ns, which corresponds to 15.38 MHz.

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 Influence of latch on the timing characteristics

tACC = tAVIV
tACC = tAVIV ! tLATCH

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 INTRODUCTION TO
8051 ARCHITECTURE

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Addressing modes

The most commonly used addressing modes are:

P immediate
P register
P direct
P indirect
P indirect with offset
P relative

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Immediate addressing

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Register addressing

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Direct addressing

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Indirect addressing

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Indirect addressing with offset

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Basic information about 80C51 microcontroller

P 4 KB of internal program memory

(ROM - 80C51, EPROM - 87C51 or flash - 89C51)
P 64 KB of program memory address space
P 128 bytes of internal RAM
P 64 KB of external data memory (RAM + I/O) address space
P two 16-bit timers/counters
P USART
P 32 I/O lines
P price at the level of 1$/pc at small quantities

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Program memory in '51

MOV A, #37H
MOVC A, @A+PC
MOVC A, @A+DPTR

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Internal data memory in '51

MOV A, R5
MOV A, 17H
MOV A, SBUF
MOV A, @R1
PUSH ACC

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SFRs and internal peripheral circuits in '51

MOV R5, SCON

CLR TI
CLR SCON.1
ANL SCON, #00000010B
SETB ACC.7

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External data memory (and I/O) address space
in '51
Interface:
P0 - multiplexed lower byte of address / data bus
P2 - higher byte of address
P3.7 - negative read strobe
P3.6 - negative write strobe

MOVX A, @DPTR ; read operation (16-bit indirect addressing)

MOVX @DPTR, A ; write operation (16-bit indirect addressing)

MOVX A, @R1 ; read operation (8-bit indirect addressing)

MOVX @R0, A ; write operation (8-bit indirect addressing)

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I/O PORTS

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Internal structure of the I/O port lines in 80C51

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Structure of the I/O output stage in 80C51

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Read-modify-write instructions

P ANL P2, A
P ORL P1, #10
P XRL P3, A
P JBC P1.3, next
P CPL P1.0
P INC P2
P DEC P3
P DJNZ P2, alpha
P MOV Px.y, C (eg. MOV P1.0, C)
P CLR Px.y (eg. CLR P1.1)
P SETB Px.y (eg. SETB P2.3)

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Differences between read-modify-write and
read/write instructions
read/write instructions:
MOV A, P1
ANL A, #0FFH
MOV P1, A

read-modify-write instruction:
ANL P1, #0FFH

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Another approach to digital I/O lines control
on the example of AVR microcontrollers
DDxn PORTxn I/O mode Pull-up Description
0 0 input no Hi-Z (tri-state)
0 1 input yes the pin will source current if
externally pulled low
1 0 output no push-pull low (sinking current)
1 1 output no push-pull high (sourcing current)

For reading state of the pins the PINxn register is used

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 Typical output characteristics of digital I/O lines
in AVR microcontrollers

VOL(MAX) < 0.8 V @ IOL = 20 mA, VCC = 5V

VOH(MAX) > 4.0 V @ IOH = -20 mA, VCC = 5V

Absolute Maximum Ratings:

DC current per I/O pin ............................................... 40.0 mA
DC current VCC and GND pins................................ 200.0 mA
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SYSTEM CLOCK
AND RESET

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System clock

Typical system clock solutions:

P external oscillator
P onboard oscillator with external crystal or ceramic resonator
P onboard PLL-based oscillator with external crystal resonator
P onboard oscillator with external LC or RC circuit
P onboard RC oscillator
P onboard high-precision oscillator
eg. in PIC 12F629 tolerance of the oscillator frequency is:
1% @ 3.5 V, 25EC
2% @ 2.55.5 V, 080EC

Problems:
P high frequency crystal resonators
P power consumption
P input pins for external clock
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System reset

P purpose and results of the reset

P reset sources
< power-on
< watchdog circuits
< manual reset
P implementation of the reset
< simple RC circuit
< internal reset circuit
< specialized external reset circuit

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INTERRUPTS

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 Basic philosophy of interrupts

The main reason for invention of interrupts was need for

hardware triggered change of the program flow in response to
external events, as software testing:
P puts additional load on the CPU
P is slow and can miss some signals (eg. short pulses)

Soon, it turned out that interrupts can be also used for:

P simplification of the software
P diagnostic purposes (eg. detection of division by 0,
stack overflow or underflow, etc.)

Some simple microcontrollers do not support any interrupts,

eg. PIC16C5X
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Servicing of an interrupt

Servicing an interrupt causes the microprocessor to stop

executing current software task and to perform a call to a
dedicated interrupt service routine.

When the microprocessor finishes the routine it returns to the

point at which the program was stopped and execution of the
interrupted section of firmware is resumed.

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Hardware-generated instructions concept
(Intel 8080)
INT interrupt input pin (the only
interrupt input in 8080)
INTA interrupt acknowledge signal
used as a strobe for putting onto the
data bus a byte of code (instruction)
to be executed in response to the
interrupt
typically RSTn (n = 0..7) instructions
were used for this purpose, but any
other can also be used (including
multi-byte instructions)
INT state is tested once every
machine cycle; if it is noticed as
active, the acknowledge signal is
generated in the following cycle
the interrupt is level sensitive

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Problems with level-sensitive interrupts

P interrupt signal must be active long enough to be noticed by the

interrupt system (including situations when another interrupt is in
progress)
P interrupt signal must not be active too long or it will be recognised as
multiple interrupt request

Potential solutions:
P convert the interrupt into edge-triggered (requires additional
hardware)
P mask the interrupt

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Edge-triggered interrupts

P eg. RST7.5 and TRAP interrupts in 8085 are rising-edge sensitive

P edge-sensitive means there is a flip-flop that is set in response to the
active (eg. rising) edge of the interrupt signal, but it does not mean
that the flip-flop is directly and asynchronously triggered by the
interrupt signal
P in some microprocessors such a flip-flop is automatically reset when
the interrupt is serviced

Edge-sensitive interrupt does not mean that every pulse (in

particular a very short one) will trigger the interrupt.

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Masking interrupts

P masking an interrupt means making it insensitive to the active

interrupt request signal
P depending on a microprocessor masking is supported by means of
dedicated instructions (eg. DI, EI in 8080) or by manipulation of
interrupt enable bits (eg. in 80C51)
P usually the default state of the interrupt system after reset is
"disabled"
P usually when the interrupt system starts servicing an interrupt, it
masks it out, so that the system will not accept another interrupt from
the same interrupt source before service of the currently active
interrupt is completed

Some interrupts can be non-maskable (eg. TRAP in 8085, NMI in

Z80, etc.).

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 Multiple interrupt sources

Problem of multiple interrupt sources can be solved as follows:

P in the single interrupt input system an interrupt priority encoder can be
used or the interrupt signals can be OR-ed (detecting of the interrupt
requesting device can be done by means of additional polling)
P more efficient is use of separate interrupt inputs for every interrupt
source (eg. INTR, RST5.5, RST6.5, RST7.5, TRAP in 8085)

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Fixed-address interrupt vector system
in Intel 8085
In the fixed-address interrupt vector system the address vectors of the
interrupts are fixed and cannot be changed, eg. in 8085:

TRAP => CALL 24H

RST7.5 => CALL 3CH
RST6.5 => CALL 34H
RST5.5 => CALL 2CH

Before branching to the interrupt vector the microprocessor pushes

the PC (program counter) contents onto the stack.

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Priority of interrupts

Existing of a few different interrupt sources with different address

vectors means there must be a method of resolving conflicts
between two (or more) simultaneous interrupt requests.
The problem can be solved by assigning different priority to every
interrupt source.
In 8085 the interrupts have fixed priority, but in some other
microprocessors / microcontrollers interrupts can have
programmable priority (that can be even dynamically change at run-
time).
In 8085 the interrupts have request-priority only, which means that
as soon as EI instruction is executed the interrupt being currently
serviced can be interrupted by any other interrupt (even of lower
priority).

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 Zilog Z80 interrupts

P interrupt inputs: INT and NMI

P NMI is non-maskable, with fixed interrupt address vector (66H),
automatically disables INT when active
P INT can be used in three different modes:
< 8080 compatible mode (INTA = IORQ or M1)
< fixed interrupt address vector (38H)
< mixed (hardware-software)
mode interrupt address
vector selection

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Motorola 6800 interrupts

Motorola 6800 is an example of microprocessor with software

defined interrupt address vectors:
program memory address interrupt

0FFFFH (LSB)
0FFFEH (MSB) } restart
0FFFDH (LSB)
0FFFCH (MSB) } NMI
0FFFBH (LSB)
0FFFAH (MSB) } software interrupt
0FFF9H (LSB)
0FFF8H (MSB) } INT

The software interrupt in 6800 is invoked by execution of the SWI

instruction.
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Interrupt system in 80C51

P levels of priority (IP register)

P natural priority within level (fixed)
P individual enable bits and global interrupt enable bit (IE register)
P priority can be dynamically changed at run-time
1 0 0 0 1
PS PT1 PX1 PT0 PX0 IP (0B8H)

1 1 1 0 1 1

EA ES ET1 EX1 ET0 EX0 IE (0A8H)

INT0
SI
T0
INT1
T1

SI T1 INT1 T0 INT0
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Saving and restoring PSW

In case of vectorized interrupts,

service of an interrupt begins
with pushing the return address
onto the stack. In case of some
microprocessors PSW register is
also automatically pushed onto
the stack and popped back when
the interrupt service routine is
finished.
1) Why is it so important /
advantageous?
2) What can be done and how if
PSW saving is not hardware
supported?
3) What about working registers?

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Returning from interrupt

In most of microprocessors there are dedicated instructions for

returning from interrupt (eg. in 80C51 it is RETI in comparison to
RET used in case of standard routine).
RETI restores the interrupt system to the state from before the
interrupt (eg. restores PSW if automatically pushed onto the stack).
Hence, it is critical to use these dedicated instructions as use of
standard RET instead of RETI will in most cases result in latch-up
of the interrupt system or sometimes even in hangup of the whole
microprocessor system

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Priority inversion

wrong

right

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 Peripheral event controller and some interrupt
features in 'C166 family of microcontrollers
Interrupt control register for source xx: Interrupt control functions in PSW:
xxIR xxIE ILVL GLVL xxIC ILVL IEN ) ) ) PSW (MSB)

GLVL - interrupt group priority IEN - global interrupt enable bit

ILVL - interrupt priority level
xxIE - interrupt enable bit
xxIR - interrupt request flag

PEC channel n control registers:

) ) ) ) ) INC BWT PECCn (MSB)

COUNT PECCn (LSB)

COUNT - if 0FFH then continuous mode,

else decrementation after each transfer
BWT - 0 for word, 1 for byte transfer
INC - 00B - no pointer incrementation
01B - destination pointer incrementation
10B - source pointer incrementation
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TIMERS & COUNTERS

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Timers / counters in 80C51 (mode 0, 1)

T1 T0 TMOD (89H)

GATE C/T M1 M0 GATE C/T M1 M0

TCON (88H)

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

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Timers / counters in 80C51 (mode 2)

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Timers / counters in 80C51 (mode 3)

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Timer 2 in 80C52 (autoreload mode)

T2CON (0C8H)

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2

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Timer 2 in 80C52 (capture mode)

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Timer 2 in 80C52 (baudrate generator mode)

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USER INTERFACE
(KEYBOARD)

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Simple keyboard
VCC

Why connecting such a keyboard to

external interrupt inputs does not
have to be a good idea?
P limited number of interrupt inputs
P keyboard servicing is not a time-critical task
P multiple "key pressed" detection

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Key debouncing

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Matrix keyboard

01
1 01
001 VCC
outputs

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Small keyboard as external I/O

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Keyboard with serial input

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USER INTERFACE
(DISPLAY)

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Most common display components

P LED displays
< LED diode
< 7-segment display
< 16-segment display
P LCD displays
< LCD display with individually driven segments
< alphanumeric LCD module
< graphic LCD display (monochrome or colour)
P fluorescent displays
< alphanumeric module
< graphic module

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LED diode

P forward voltage vs. current characteristics of LED is similar to

standard diode; just VF value is different
P LED brightness is proportional to the average value of its forward
current IF
P in older LEDs level of IF corresponding to noticeable brightness
was a few mA, while in modern LEDs it is 0.5 -1.0 mA for low
power (high brightness) LEDs which IF max is at the level of 20 mA

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 LED diode characteristics

P typical VF values for different LED [mA]

colours:
< red 1.6 to 2.0 V damage threshold
< orange 2.0 to 2.5
< yellow 2.2 to 3.5 V
< green 2.5 to 3.5 V
< blue 3.5 to 5.0 V
< white 3.3 to 4.8 V

P typical VF value may be 1.85V, but

maximum VF for the same led at the
same IF can be 2.5 V
(eg. SA52- 11SRWA)
noticeable brightness [V]
LEDs should be current-driven
(not voltage-controlled)!
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7-segment and 16-segment displays

P Segments may consists of a few

LED in serial connection
P In some displays number of such
LEDs may depend on segment

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Simple LED display (static)

A B C D

1. Which of the above circuits will not work and why?

a. if the microcontroller is 80C51
b. if the microcontroller is AVR
2. How the resistor values should be calculated?

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 Typical output characteristics of digital I/O lines
in AVR microcontrollers

VOL(MAX) < 0.8 V @ IOL = 20 mA, VCC = 5V

VOH(MAX) > 4.0 V @ IOH = -20 mA, VCC = 5V

Absolute Maximum Ratings:

DC current per I/O pin ............................................... 40.0 mA
DC current VCC and GND pins................................ 200.0 mA
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 Dynamic LED display

1. How the resistor

values should be
calculated?
2. Is the resistance the
only important
parameter of these
components?
3. How the transistors
should be selected?
4. Is it possible to
implement
programmable
brightness control in
the given LED
display?

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Peripheral driver ICs examples (ULN2803A)

P 500-mA rated collector current (single

output)
P high-voltage outputs (up to 50 V)
P output clamp diodes
P inputs compatible with various types of
logic
P relay driver applications

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ULN2803A characteristics

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Peripheral driver ICs examples (TPIC6A595)

P low rDS(on) . . . 1 typ

P output short-circuit protection
P avalanche energy . . . 75 mJ
P eight 350-mA DMOS outputs
P 50-V switching capability
P devices are cascadable
P low power consumption

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 Peripheral driver ICs examples (NE590 / 591)

The NE590/591 addressable

peripheral drivers are high current
latched drivers. The device has
eight Darlington power outputs, each
capable of 250mA load current. The
outputs are turned on or off by
respectively loading a logic high or
logic low into the device data input.
The required output is defined by a
3-bit address. The device must be
enabled by a CE input line. A
common clear input CLR turns all
outputs off when a logic low is
applied. The NE590 has eight open-
collector Darlington outputs which
sink current to ground. The NE591
has eight open-emitter Darlington
outputs which source current to an
external load from a common
collector line VS. This VS line need
not necessarily be the same as the
5V VCC supply. NE590 is pin
compatible with 74'259

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 LED control ICs examples (NE587)

The NE587 is a latch / decoder

/ driver for 7-segment common
anode LED displays. The
NE587 has a programmable
current output up to 50mA
which is essentially independent
of output voltage, power supply
voltage, and temperature. The
data (BCD) inputs and LE (latch
enable) input are low-loading so
that they are compatible with
any data bus system.
The 7- segment decoding is
implemented with a ROM so
that alternative fonts can be
made available.

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LED control ICs examples
(NE587 in dynamic mode)

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LED control ICs examples
(NE587 and NE591 in dynamic display)

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LED control ICs examples (MAX7221)

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 LED control ICs examples (SAA1064)

SAA1064 LED-driver is especially

designed to drive four 7-segment LED
displays with decimal point by means of
multiplexing between two pairs of digits.
It features an I2C-Bus slave transceiver
interface with the possibility to program
four different SLAVE ADDRESSES, a
POWER RESET flag, 16 current sink
OUTPUTS, controllable by software up
to 21 mA, two multiplex drive outputs for
common anode segments, an on-chip
multiplex oscillator, control bits to select
static, dynamic and blank mode, and
one bit for segment test.

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LED control ICs examples
(SAA1064 in dynamic mode)

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Simple LCD display (non-multiplexed)

P direct access to individual segments

P simple to drive
P low power consumption
P requires many I/O pins

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 Simple LCD display (multiplexed)

P no direct access to individual segments

P complex driving waveforms
P low power consumption
P requires less I/O pins than similar non-
multiplexed LCD
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 Alphanumeric LCD modules

P 1 to 4 lines 8 to 40 characters each

P low power consumption
P on-board LCD controller + character RAM
P 7-bit ASCII compatible
P 8 user-defined characters
P optional LED backlight
P 4-bit or 8-bit standard microprocessor
interface (Motorola mode)
P reasonable price
P small characters
P simple software initialization

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LCD interface timing

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LCD in the external data memory space

89S8252
1 39 7 2
2 T2 P0.0 38 8 D0 VCC VCC
3 T2EX P0.1 37 9 D1
P1.2 P0.2 D2
4 P1.3 P0.3 36 10 D3
5 SS P0.4 35 11 D4
6 MOSI P0.5 34 12 D5
7 MISO P0.6 33 13 D6
8 SCK P0.7 32 14 D7
VCC 9 RST EA 31 VCC 6 E
ALE 30 5 RD/-WR
2u2 10 29 4
11 RXD PSEN 3 RS 1
TXD VO GND GND
12 INT0 P2.7 28 1 4
13 27 3 6 LCD1
14 INT1 P2.6 26 2 5
15 T0 P2.5 25
T1 P2.4
16 WR P2.3 24 74HC00 74HC00
17 RD P2.2 23
P2.1 22
21
P2.0
X X
2 1
VCC GND
1 1
8 9 1 10K
GND GND 1
27p 27p
10MHz 74HC00

1 1
2 3

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LCD in 8-bit mode
connected to the I/O lines

89C2051
1 19 7 2
VCC 2 RST P1.7 18 8 D0 VCC VCC
2u2 3 RXD P1.6 17 9 D1
6 TXD P1.5 16 10 D2
7 INT0 P1.4 15 11 D3
8 INT1 P1.3 14 12 D4
9 T0 P1.2 13 13 D5
T1 P1.1 D6
11 P3.7 P1.0 12 14 D7
X X 6
1 2 5 E
5 4 4 RD/-WR
3 RS 1
VO GND GND
LCD1
GND GND
27p 27p
10MHz

VCC GND
10K

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LCD in 4-bit mode
connected to the I/O lines

7 2
8 D0 VCC VCC
9 D1
D2
89C2051 10 D3
1 19 11
VCC 2 RST P1.7 18 12 D4
2u2 3 RXD P1.6 17 13 D5
6 TXD P1.5
16 D6
INT0 P1.4 14 D7
7 INT1 P1.3 15
8 T0 P1.2
14 6
9 13 5 E
11 T1 P1.1 12 4 RD/-WR
P3.7 P1.0 RS
3 VO GND 1 GND
X X
1 2 LCD1
5 4

GND GND
27p 27p
10MHz

VCC GND
10K

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SERIAL INTERFACES

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 Internal serial interfaces most commonly used
in microprocessor systems
P UART / USART
P SPI
P I2C
P 1-Wire
P CAN

The main advantage of serial interfaces is smaller number of signal

lines resulting in smaller packages and connectors, easier PCB
routing, hence lower cost.

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USART in 8051 in mode 0 (synchronous)

SBUF (99H)

SCON (98H)

SM0 SM1 SM2 REN TB8 RB8 TI RI

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USART in 8051 in mode 1 (asynchronous)

SCON (98H)

SM0 SM1 SM2 REN TB8 RB8 TI RI 2

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USART in 8051 in mode 2, 3 (asynchronous)

2SMOD fOSC
BR2 '
64
2SMOD fOSC
BR1, 3 '
32 @ 12 @ (256 & TH1)

fOSC
BR1, 3 '
32 @ (65536 & RCAP2)

SCON (98H)

SM0 SM1 SM2 REN TB8 RB8 TI RI 2

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 Multiprocessor communication;
enhanced serial port in 8051
P set SM2 in all the processors and put them in 2 or 3 USART mode
P master sends slave address with 8th bit set
P all the slaves interpret the address; the addressed slave clears SM2, all the
other set their SM2 bits
P master and the addressed slave perform uni- or bidirectional transmission of
data with 8th bit cleared
P master starts another transmission (repeat the steps above)

SADDR = 1 1 0 0 0 0 0 1 SADDR = 1 1 0 0 0 0 1 0
SADEN = 1 1 1 1 1 1 1 0 SADEN = 1 1 1 1 1 1 0 1

active =1100000X active =110000X0

11000001 - the first; 11000010 - the second; 11000000 - both; XXXXXX11 - none

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SPI

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1-Wire

initialization

write

read

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 I2C

P two signal lines (SDA, SCL)

P multiple devices can be connected to the same I2C bus
P bidirectional transmission
P unique addresses (7-bit or 10-bit) of the devices
P transmission controlled by a master
P multiple masters allowed
P simultaneous transmission conflicts resolved immediately without loss of data
P transmission speed automatically adjusted to the slowest connected device
P number of the devices limited only by the total bus lines capacitance of 400 pF

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INDUSTRIAL AND COMPUTER
INTERFACES

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 Most common industrial and computer interfaces

P RS-232
P RS-485
P Centronics, Bitronics (IEEE 1284)
P Firewire (IEEE 1394)
P SCSI
P PCI
P PCI Express
P (E)IDE
P SATA
P IEEE488
P VXI
P USB
P Ethernet

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Single-ended and differential data transmission

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Data transmission topologies

Some other common topologies are:

P star
P daisy chain
P ring

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RS-232

P common computer and industrial interface

P very low cost
P very simple implementation
P low speed
P max distance limited to 15 meters
P point-to-point connection
P single-ended
P non-standard voltage levels

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Example of RS-232 implementation

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 RS-485

P common industrial interface

P very low cost
P very simple implementation
P high speed
P max distance of 1200 meters
P multipoint connection possible
P differential data transmission

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Comparison of RS-232, RS-422, RS-423
and RS-485

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 USB

P network with master CPU in

tiered star topology
P up to 127 devices (hubs may
be required)
P data rates of 1.5 Mbps,12
Mbps, and 480 Mbps
P 4 wires, max. length 5 m
P differential data transmission
P power distributed via the
interface
P auto configuration upon
connection for real plug and
play
P assured bandwidth for real-
time applications
P requires substantial amount of
firmware
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Ethernet

P virtually unlimited number of hosts

P twisted pair cable as the most common connection media
P data rates of 10 Mbps, 100 Mbps, and 1 Gbps over twisted pair
P up to 100 m between the twisted pair nodes
P differential data transmission
P PoE (power over ethernet) possible
P assured bandwidth for real-time applications
P requires substantial amount of firmware

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D/A CONVERTERS

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D/A converter

A digital-to-analog converter (also known as a DAC or a D/A converter) is an

electronic circuit that converts a digital code (usually a binary code) into a
corresponding discrete analog value (a voltage or current at the DAC's
output). The word "discrete" is very important to understand, because a DAC
cannot provide a continuous-voltage output signal. Rather, it provides analog
steps. By increasing the resolution of the DAC, the number of discrete steps is
increased and the step size is reduced (which reduces the quantization error).
The steps can be lowpass filtered to obtain a signal that closer approximates a
continuous-time signal.

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Basic DAC selection criteria

P resolution
P INL and DNL, gain and offset errors
P output signal (current or voltage)
P bipolar or unipolar output
P output voltage/current range
P internal or external reference voltage
P bandwidth of the reference signal in the DAC is multiplying
P maximum output current
P speed
P number of channels
P microprocessor interface
P power consumption

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Specialized DAC examples

P digital potentiometer
< wiper resistance is definitely of non-zero value
< works properly only if powered
< works properly only with signals within the supply rails
< settings are usually lost when power is off
< bandwidth depends on the input code
< temperature coefficients are often relatively high

P DDS (direct digital synthesis)

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 Internal DACs (in microcontrollers)

P 8-16 bits of resolution

P speed up to Msps
P usually resistor-string technology resulting
in guaranteed monotonic transfer function
P boundary code ranges are often excluded
from the given linearity specifications
P multiple channels (usually 1-4 DACs)

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 PWM based DAC implementation;
example of dedicated PWM outputs in 80C552
P use a square wave of a
frequency f, duty factor DF
and voltage levels equal
GND and Vcc
P pass the signal through a
low-pass filter, which corner
frequency is much lower
than f

fosc
fPWM '
2 @ 255 @ (1 % PWMP)

PWMn
PWMnduty factor ' Vout . Vcc @ DF
255

PWM outputs can be also easily implemented on PCA, CCU or other

timer/counter blocks
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A/D CONVERTERS

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A/D converter

An analog-to-digital converter (also known as an ADC or A/D converter) is an

electronic circuit that measures a real-world signal (such as voltage,
temperature, pressure, acceleration) and converts it to a digital representation
of the signal.

A/D converter compares the analog input voltage to a known reference

voltage and then produces a digital representation of this analog input (a
digital code). Every ADC introduces a quantization error, which is simply the
information that is lost. This error occurs because there are an infinite number
of voltages for a continuous analog signal, but only a finite number of ADC
digital codes. Therefore, the more digital codes the ADC can resolve, the
higher resolution it has and the less information ls lost due to quantization
error.

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ADC errors

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Most common A/D conversion methods

Nowadays, the most common A/D

converting techniques are:
P flash
P pipelined
P successive approximation (SAR)
P integrating (dual- or multi-slope)
P sigma-delta

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Flash ADCs

Flash ADCs are fastest (up to a few Gsps),

but are limited to low resolutions (6-8 bits).
For an N-bit converter, the circuit employs
2N-1 high-speed comparators, which results
in high power consumption and high price.
Flash ADCs are used only in the most
demanding (in terms of speed) applications
and are too fast to be served directly by a
microprocessor.

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Pipelined ADCs

The pipelined ADC are the most

popular ADCs for sampling with rates
from a few Msps up to a few hundreds
Msps. Their resolution is in the range of
8-16 bits. Pipelined ADCs have
moderate power consumption and
moderate price.
The pipelined ADC is multistage and
accepts a signal before completing the
conversation of the previous signal. In
this method, one stage processes data
received from the previous stage during
a clock cycle. At the end of the clock
cycle, the output of a given stage is
passed to the next stage using T/H
(track & hold) and new data is fed to the
previous stage.

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Integrating ADCs

Integrating ADCs have low speed (typically up to ksps), moderate-to-high resolution

(12-28 bits), very good linearity, line rejection, low noise, low power consumption,
low-to-moderate price.
single slope dual slope

Accuracy of a single-slope circuit depends

on the tolerances of the R and C values.
This makes measurement repeatability
relatively low. To overcome this problem
dual-slope architecture is used.

Multi-slope solutions increase conversion

speed.
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 Sigma-delta ADCs

The sigma-delta ADCs offer moderate speed (up to a The Sigma-delta Modulator
few Msps), high resolution (16-32 bits), line rejection,
low power consumption, low price, and low noise.
The density of 1s at the modulator output is
proportional to the input signal. The integrator acts as
a lowpass filter to the input signal and a highpass
filter to the quantization noise. Thus, most of the
quantization noise is pushed into higher frequencies.
Oversampling has changed not the total noise power,
but its distribution.

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Successive approximation ADCs

Successive approximation (SAR)

ADCs have moderate speed (typically
up to a few Msps), low-to-moderate
resolution (8-18 bits). Their typical
advantages are also low power
consumption, serial interface (usually
SPI or I2C) resulting in small form
factor, and low price. Successive
approximation ADCs are often
available as multichannel converters.

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Internal ADCs (in microcontrollers)

P successive approximation:
kbps to Msps @ 8-16 bits
P sigma-delta:
usually much slower (100-1000 times)
but with higher resolution (16-24 bits)
P usually multiple (multiplexed) analog
inputs

P usually higher errors in comparison to

standalone ADCs
P usually unipolar input voltages only
P input impedance, slew rate, etc. may
introduce strong limits or problems

P usually $(ADC) < $(C) + $(AD)

similar relationship refers to size
P internal ADC increases reliability and
simplifies firmware and debugging
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Specialized ADC examples

P digital thermometers (eg. DS18S20)

P capacitance to digital converters (eg. AD7745)
P digital humidity sensors (eg. SHT15)
P digital pressure sensors (eg. BMP085)
P digital microphones (eg. ADMP421)

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POWER CONSUMPTION

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Influence of CMOS technology
on power consumption

P % C @ VCC2 @ f

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Power reduction modes - Idle

P Idle is entered by setting appropriate

control bit located in SFR area
P when Idle is entered the CPU is stopped
P peripheral circuits and interrupt system
still work
P contents of the SFRs and internal
memory is preserved
P I/O pins are held in the previous state,
unless changed by working peripherals or
forced externally
P in order to further reduce power
consumption all the peripherals which are
not needed should be switched off
P Idle mode can be terminated by an
interrupt (external or internal) or reset
P during Idle mode power consumption is a
few times lower than during normal active
mode
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Power consumption vs. system clock frequency
in active and idle modes of '51

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Power reduction modes - Power Down

P Power Down is entered by setting

appropriate control bit located in SFR
area
P when Power Down is entered the clock is
stopped
P as a result peripheral circuits don't work
P contents of the SFRs and internal
memory is preserved
P I/O pins are held in the previous state,
unless forced externally
P Power Down mode can be terminated by
a hardware reset or (only in some cases)
by an external interrupt (level-activated)
P during Power Down mode power
consumption is reduced to the level of
single microamperes and can be further
reduced by lowering Vcc

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Power consumption vs. supply voltage of '51

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Power reduction modes - Slow Down

P Slow Down is entered (quit) by setting (clearing) appropriate control bit

located in SFR area
P when Slow Down is entered, frequency of the clock is substantially lowered
P changing of the clock frequency may be obtained by means of a clock
prescaler (divider), selection of another clock source (eg. internal RC
oscillator) or both
P as a result CPU and internal peripheral circuits work much slower, which
may result in some side effects (eg. change of the serial port baudrate,
frequency of the timer's overflow, etc.)
P Slow Down can be used independently from Idle or simultaneously with Idle
mode

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 Power consumption of different microprocessors
and microcontrollers
P common sensor node processors: AVR, 8051, StrongARM, XScale, ARM
Thumb, SH Risc, MSP430, PIC
P exemplary values of power consumption:
< 4 nJ/instr ATMega128L @ 4 MHz, 3.0 V
< 2 nJ/instr AVR32 UC3A @ 66 MHz, 3.3 V
< 2.1 nJ/instr ARM Thumb @ 40 MHz, 3.0 V
< 1.0 nJ/instr Cygnal C8051F35x @ 50 MHz, 3.0 V
< 0.5 nJ/instr MSP430x20xx @ 1 MHz, 2.2 V
< 0.11 nJ/instr PIC16LF72X @ 4 MHz, 1.8 V
< 0.8 nJ/instr TMS320VC5510 @ 200 MHz, 1.5 V
< 1.3 nJ/instr IBM 405LP @ 380 MHz, 1.8 V
< 0.35 nJ/instr IBM 405LP @ 152 MHz, 1.0 V
< 1.1 nJ/instr Xscale PXA250 @ 400 MHz, 1.3 V
< 1.9 nJ/instr Xscale PXA250 @ 130 MHz, 0.85 V

The above values dont take into consideration operand size differences!
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Selecting energy-efficient components

P eg. when looking for an ADC capable of working with the speed of 100 ksps
< AD 7853 (12-bit; 200 ksps max) - 6.0 mW @ 3.0 V, 100 ksps; 6.5 - 12$
< AD 7694 (16-bit; 250 ksps max) - 1.7 mW @ 3.0 V, 100 ksps; 6.1 - 7.6$
P modern solutions and higher level of integration usually result in lower power
consumption
P display:
< alphanumeric LCD: 0.5 - 1.0 mA (but the backlight can draw 30 mA!)
< single LED: 1.0 - 2.0 mA
P all the peripherals which are not needed at the moment can be powered
down or switched off (but care should be taken about the inputs of such
components)
P resistor values should be increased if possible
P etc.

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 Power supply design - use of linear regulators
LM7805C:
P output current in excess of 1A
P 2.5 V (typ) dropout voltage
P 50 mV (max) of line regulation
P 50 mV (max) of load regulation
P 8.5 mA quiescent current
P 40 VRMS output noise
P internal thermal overload
protection
P no external components
required
P internal short-circuit protection
P TO-3 and TO-220 packages
66% @ 5.0/7.5 V
Tomasz Starecki
MAX1793:
P guaranteed 1 A output current
P low 210 mV dropout @ 1 A
P up to 1% output voltage
accuracy
P preset at 1.5 V, 1.8 V, 2.0 V,
2.5 V, 3.3 V or 5.0 V
P adjustable from 1.25 V to 5.0 V
P low 125 A ground current
(200 A @ 0.5 A output current)
P 0.1 A shutdown
P low 115 VRMS output noise
P thermal overload protection
P output current limit
P TSSOP power package (1.5 W)
94% @ 3.3/3.51 V
66% @ 3.3/5.0 V
179
MAX8902:
P guaranteed 0.5 A output
current
P 100mV (max) dropout @ 0.5 A
P 1.5% output accuracy over
load, line, and temperature
P 1.7 V to 5.5 V input voltage
P 0.6 V to 5.3 V output voltage
P 80 A operating supply current
P < 1A shutdown supply current
P 16 VRMS output noise
P 0.7 A short-circuit protection
P thermal-overload protection
P output-to-input reverse current
protection
97% @ 3.3/3.4 V
66% @ 3.3/5.0 V
2
Power supply design - use of DC-DC regulators
(MAX1951A example)
MAX1951A features:
P Efficiency Up to 94%
P 1.5% Output Accuracy Over
Load, Line, and Temperature
P Guaranteed 2A Output Current
P Operates from 2.6V to 5.5V
Supply
P Adjustable Output from 0.8V to
VIN
P Internal Digital Soft-Soft
P Short-Circuit and Thermal-
Overload Protection
P 1MHz Switching Frequency
Reduces Component Size
P Enable Input Audio Shutdown for
Reducing Power Consumption

92-93%@ 3.3/5.0 V
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Basic hints in reducing power consumption in
microprocessor systems (summary)
P use CMOS whenever possible
P never leave CMOS inputs floating; connect unused inputs to GND or VCC
P use power saving modes efficiently
P use lower frequency of operation
P use lower supply voltage
P select energy-efficient components (in particular low-power microprocessor)
P switch off (power off) all the peripherals which you don't need at the moment
P use LCD instead of LEDs, don't use graphic LCD, neither backlight if it is not
critical
P modern technology and higher level of integration usually result in lower
power consumption
P remember that pull-ups, polarization resistors, etc. also draw current
P use high-efficiency DC/DC instead of linear regulators

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PROGRAM MEMORY

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Program memory options

P mask-ROM eg. 80C51

< lowest possible cost but only in high volume orders (eg. 10 000 pcs.)
< price depends on the order quantity (masks development costs are fixed)
< contents of the program memory cannot be changed
P EPROM eg. 87C51
< user-programmable, erasable
< erasing/reprogramming possible but number of erase cycles strongly limited
< erasing by means of UV light, hence ceramic package with quartz window required
< high cost due to the package
P PROM / OTP EPROM eg. 87C51
< user-programmable, OTP = One Time Programmable
< plastic package, hence much lower cost
P EEPROM (Flash) eg. 89C51
< user-programmable
< erasing/reprogramming possible, number of erase cycles very high (eg. 10 000)
< cost similar to OTP
< usually ISP (in-system-programmable) by means of SPI, JTAG, UART, etc.
P ROM-less eg. 80C31
< cost as of mask-ROM versions, but no on-board program memory

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Program memory protection

P lock bits
P encryption table

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Data EEPROM

P should not be mistaken with program flash memory

P can be used for storing system IDs, passwords, user settings,
calibration coefficients, etc.
P in some cases can be used for storing or backing up the most
important data
P if not present in the microcontroller can be easily added externally
P is of relatively low cost - eg. in 2009 a 16 Mbit serial flash EEPROM
with SPI interface was easily available at the price level of $2.00/pc
(price for small quantity orders)

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WATCHDOG CIRCUITS

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Purpose of watchdog circuits

The main philosophy which stands behind use of watchdog circuits is to

prevent the microprocessor system from entering improper state and/or if
such a situation happens, to let the system get to a known (default) state.
Hence, use of a watchdog circuit increases reliability of the system.
There are at least three kinds of circuits that can be treated as watchdogs:
P watchdog timers
P watchdog oscillators
P power supply monitoring circuits (voltage monitors)

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 Watchdog timer

P kinds of watchdog timers

< dedicated, internal
< optional, internal (eg. based on a PCA unit)
< external
P watchdog timer clock sources
< system clock (machine cycles)
< dedicated internal oscillator
P starting and stopping watchdog timer
< automatic, in some cases hardware enabled/disabled
< by setting an appropriate bit in the SFR area
< stopping watchdog timer is usually impossible (reset may be the only way)
P watchdog timer refreshing
< by setting an appropriate bit in the SFR area (often by means of a protected instruction)
< if refresh fails, the watchdog timer will overflow, resulting in the system reset
< depending on watchdog timer, its refresh period may be programmable or fixed
< timer interrupts must not be used as a method of the watchdog timer refresh

Watchdog timer must not be treated as a remedy for firmware bugs

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Watchdog oscillator

P prevents the system from being left in a random undetermined state if

something wrong happens to the system clock
P continuously compares system clock frequency with the frequency of its
dedicated (RC) oscillator
P puts the microcontroller in reset if the system clock frequency is lower
P automatically switches internal microcontroller clock to the higher frequency
source

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Power supply monitoring circuit

Typically power supply monitoring circuit:

P sets a flag (which can be
usually used as an interrupt
request flag) if the VCC is
below certain warning level
P forces microcontroller reset
(and sets another flag) if the
VCC is below certain
operational level

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Microprocessor supervisory circuits
(example of MAX 69x)

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 Other watchdog issues

P recognizing source of reset

< every watchdog circuit has at least one dedicated status flag
< the flag is set by the watchdog if the system reset resulting from watchdog
operation is triggered
P power saving modes and use of watchdogs
< watchdog timer and oscillator watchdog must be disabled if power down
mode is to be used
< in many cases simultaneous use of watchdog timer and slow down or idle
mode may also result in a watchdog-triggered reset
P hardware enabling/disabling watchdogs
< some microcontrollers have pins which can be used for the purpose of
hardware enabling/disabling watchdog circuits
< often the same pins are simultaneously used for disabling/enabling power
saving modes accordingly

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DEBUGGING

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General classification of debugging tools

P hardware tools
< oscilloscopes
< logic probes
< logic state analysers
< short-circuit testers
< microprocessor bus testers
P software tools
< assemblers + linkers
< high-level language compilers (eg. C, Java, Modula, Ada, Pascal)
< microprocessor simulators
P mixed tools
< EPROM memory emulators
< in-circuit debuggers
< microprocessor emulators

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Typical sequence of debugging

1. basic microprocessor system (P + external ROM & RAM; tested with

hardware tools)
a. power supply voltages
b. system clock (PSEN, ALE, XTAL signals, etc.)
c. default state of the I/O pins
d. square wave on a given I/O
2. BIOS (99% written in assembler; tested with all the available tools as
needed)
a. display - can be used for further debugging even if not present in target
system (parallel interface - goldpins; I2C; PC as a terminal via RS-232C)
b. interrupts and all the other routines that control internal peripheral
circuits
3. rest of the interrupt service routines
4. other routines

Firmware code consists of initialization + main loop

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