Sei sulla pagina 1di 32

JEDEC

STANDARD

Procedure for Wafer-Level DC


Characterization of Bias Temperature
Instabilities

JESD241

DECEMBER 2015

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION


NOTICE

JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal counsel.

JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.

JEDEC standards and publications are adopted without regard to whether or not their adoption
may involve patents or articles, materials, or processes. By such action JEDEC does not assume
any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.

The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
publication may be further processed and ultimately become an ANSI standard.

No claims to be in conformance with this standard may be made unless all requirements stated in
the standard are met.

Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under
Standards and Documents for alternative contact information.

Published by
JEDEC Solid State Technology Association 2015
3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2107

This document may be downloaded free of charge; however JEDEC retains the
copyright on this material. By downloading this file the individual agrees not to
charge for or resell the resulting material.

PRICE: Contact JEDEC

Printed in the U.S.A.


All rights reserved
PLEASE!

DONT VIOLATE
THE
LAW!

This document is copyrighted by JEDEC and may not be


reproduced without permission.

For information, contact:

JEDEC Solid State Technology Association


3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2107

or refer to www.jedec.org under Standards-Documents/Copyright Information.


JEDEC Standard No. 241

PROCEDURE FOR WAFER-LEVEL DC CHARACTERIZATION OF BIAS TEMPERATURE


INSTABILITIES

CONTENTS

1 Scope ......................................................................................................................................................... 1

2 Normative references ............................................................................................................................... 1

3 Terms and definitions ............................................................................................................................... 2

4 Technical requirements ............................................................................................................................. 4


4.1 Constant current threshold Voltage VT(ci) determination..4
4.2 Characterization of linear mode VT(ci) BTI VT shifts .............................................................................. 6

5 BTI Stress/test procedure .......................................................................................................................... 6


5.1 Description of adopted VGS/VDS stress/test waveforms ........................................................................... 6
5.2 Selection of Device under test (DUT).................................................................................................... 8
5.3 Initial (before stress) VT(ci) estimation at time t0 (typically 0 s). ............................................................. 8
5.4 Stress/test Cycle ..................................................................................................................................... 8
5.5 Evaluation of tfit, tf, for a given ......................................................................................................... 10
5.6 IV characterization after tf .................................................................................................................... 12

6 DC BTI fast switching technical requirements ....................................................................................... 12


6.1 Wafer level equipment requirements ................................................................................................... 12
6.2 Test structure requirements .................................................................................................................. 12
6.3 Measurement requirements .................................................................................................................. 12
6.4 Hardware sampling requirements ........................................................................................................ 13

7 DC BTI End of Life (EOL) estimation for a wide device....................................................................... 13

8 Required reporting .................................................................................................................................. 14

Annex A (informative) Recommendations to estimate alternate device parameters ................................. 16

Annex B (informative) Selection of a wide device .................................................................................... 18

Annex C (informative) Experiment design to find wide device dc BTI model parameters ....................... 21

-i-
JEDEC Standard No. 241

Foreword

This test procedure was drafted and approved by JEDEC JC-14.2 Wafer-Level Reliability Committee
consisting of recognized bias-temperature instability industry experts from foundries and fabless member
companies.
The objective of this Bias Temperature Instability (BTI) stress/test procedure is to provide a minimum
recommendation for a simple and consistent comparison of End of Life (EOL) mean threshold voltage
(VT) shift due to BTI aging at agreed worst dc use conditions. Both PTBI and NBTI are addressed in this
characterization procedure and can be easily implemented to allow comparison of BTI on different mature
CMOS processes. Bias-temperature instabilities are investigated in a capacitor-like configuration with the
MOSFET gate biased (|VGS| > 0) at high temperature while other contacts are grounded (no channel
conduction) (VDS = 0). Typically physical BTI damage results in the degradation of the voltage threshold
(VT), as well as changes in the channel mobility and transconductance. As a consequence of the
degradation of device parameters the circuit may fail to fully meet functional requirements.
The procedure enables only:
Comparison of stable and manufacturable CMOS processes and technologies in which the
process variation is low and the yield is mature.
Estimate BTI aging of large area MOSFET transistor with a channel width, Wdes
(Wdes Wmin see Annex B) and length Ldes.
Estimate of linear mean VT shift as a measure of device flatband shift dependence on BTI aging.
Annex A. provides recommendations to estimate other device parameters associated to BTI
induced mobility and transconductance degradation.
BTI qualification and accept-reject criteria are not given in this document. Historical discrepancies
resulting from inconsistent observation, metrology capabilities and quantification of BTI damage on the
same CMOS process and technology are addressed by using this procedure as benchmark for BTI
comparison.
The stress/test BTI dc characterization methodology can be used within the limits of this procedure as a
benchmark to monitor BTI damage as related to flatband VT shift. Future revisions this proposed
methodology will be introduced as more experimental findings become available.

ii
JEDEC Standard No. 241
Page 1

PROCEDURE FOR WAFER-LEVEL DC CHARACTERIZATION OF BIAS TEMPERATURE


INSTABILITIES

(From JEDEC Board Ballot JCB-15-22, formulated under the cognizance of the JC-14.2 Subcommittee on Wafer-
Level Reliability.)

1 Scope

The scope of this document is to provide a minimum common protocol for foundries and fabless
customers to compare the dc BTI induced mean VT shift at an agreed End of Life (EOL) of a MOSFET
transistor with a channel width, Wdes (Wdes Wmin See Annex B) and length Ldes of a manufacturable
CMOS process and technology. The BTI comparison is proposed at an assumed worst dc use conditions
(VDDmax, TJmax). The procedure applies to both Negative (VGS < 0) (NBTI) and Positive (VGS > 0) (PBTI)
BTI conditions for both pMOSFET and nMOSFET transistors.
The proposed procedure consists of two parts:
1) BTI stress/test characterization methodology
A two-step stress/test waveform with VGS and VDS switching between a capacitor-like BTI stress
with no channel conduction (VGS = VGSstr, VDS= VDSstr = 0) and a single drain current, ID,
measurement in linear mode (VGS =VGStst, VDS = VDStst < VDsat). The VGStst is chosen to estimate the
constant current VT (VT(ci)) in the linear region of the weakly inverted region of the device IV
characteristics to mainly monitor the associated flatband voltage shift (charge accumulation in the
gate dielectric stack). Measurement is accomplished with a selected measuring delay
(1 s 2 ms) from stress to test bias conditions. The procedure to determine is given in
paragraph 6. As a reference, a procedure to determine ID shifts in linear or saturation mode and
VT(ci) shift in saturation mode during dc BTI stressing is given in Annex A.
2) DC EOL VT shift estimation at worst VDDnom/T dc use conditions.
Estimation of dc VT shift at a given EOL is performed once a phenomenological BTI model is
derived that is representative of the dc BTI sensitivity of the CMOS processes and/or
technologies under evaluation. Section 7, describes this procedure and Annex C suggests a
possible VGSstr/Tstr design of experiments to estimate the DC BTI model parameters.

2 Normative references

ASTM F616-86, Standard Method for Measuring MOSFET Drain Leakage Current.
ASTM F617-86, Standard Method for Measuring MOSFET Linear Threshold Voltage.
ASTM F1096-87, Standard Method for Measuring MOSFET Saturated Threshold Voltage.
JEP001, Foundry Process Qualification Guidelines (Wafer Fabrication Manufacturing Sites).
JEP122, Failure Mechanisms and Models for Semiconductor Devices.
JESD60, A Procedure for Measuring P-Channel MOSFET Hot-Carrier Induced Degradation Under DC
Stress.
JESD77, Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices.
JESD90, A Procedure for Measuring P-Channel MOSFET Negative Bias Temperature Instabilities.
JESD91, Method for Developing Acceleration Models for Electronic Component Failure Mechanisms.
JEDEC Standard No. 241
Page 2

3 Terms and definitions

For the purposes of this standard, the terms and definitions given apply.

alternating current, ac: The voltage bias applied at alternating current bias conditions.

bias temperature instability, BTI: A temperature-activated intrinsic wear out mechanism in MOSFETs
operating with the channel in inversion or accumulation.
NOTE 1 (|VGS| > 0) with no channel conduction (VDS = 0).
NOTE 2 Wearout results in an increase in the |V(TO)| with consequential decrease in drain current and possibly
transconductance. BTI aging with VGS < 0 is called NBTI (Negative BTI), while with VGS < 0 it is called PBTI
(Positive BTI).

BTI power law time exponent, n: The BTI aging exponent that describes a typical power law
dependence on stress time.

channel length, Ldes: The MOSFET channel length by design.

channel width, Wdes: The design channel width.

cumulative stress time, tstr: The cumulative stress time.

current threshold voltage, constant VT(ci): The threshold voltage at a constant current.

direct curent, dc: A constant voltage bias condition. (No alternating component.)

drain current, ID: The direct current into the drain terminal.

drain supply voltage, dc, VDD: The drain supply voltage.

drain-to-source voltage, VDSlin: The drain-to-source voltage in the linear region of the IV curve
(VDS << VDsat).

drain-to-source voltage, VDSsat: Drain-to-source voltage in the saturation region of the IV curve
(VDS VDsat).

gate current dc, IG: The direct current into the gate terminal.

gate-source voltage, dc, VGS: The dc voltage between the gate and source terminals.

linear drain current, IDlin: The linear drain current measured when the transistor is biased in the linear
region.

maximum drain supply voltage, VDDmax: The maximum rated supply voltage of the technology.

measurement delay, : The measurement delay determined from the minimum equipment timestamp to
reach a stable ID measurement during testing.
JEDEC Standard No. 241
Page 3

3 Terms and definitions (contd)


metal-oxide-semiconductor field-effect transistor, MOSFET: An insulated-gate field-effect transistor
in which the insulating layer between each gate electrode and the channel is oxide material and the gate is
metal or another highly conductive material. (Ref. IEC 747-8.)
NOTE See JESD77 for MOSFET terms.

MOSFET gate oxide thickness, Tox: The oxide thickness parameter used for inline monitoring (Tox,gl,
Tinv etc.).

n-channel field-effect transistor, nFET: A field-effect transistor that has an n-type conduction channel.
(Ref. IEC 747-8.)

nominal drain supply voltage, dc, VDDnom: The nominal drain supply voltage, dc.

p-channel field-effect transistor, pFET: A field-effect transistor that has a p-type conduction channel.
(Ref. IEC 747-8.)

saturation drain current, IDsat: The drain current when the transistor is biased in the saturation region.

stress gate-source voltage dc, VGSstr: The VGS at stress conditions.

stress mode: The bias condition at which a MOSFET device is stressed.

stress temperature, Tstr: The chamber ambient temperature at which the DUT is stressed during BTI
stress.
NOTE When only one temperature experiment is run, the stress temperature should be the maximum allowed
during circuit operation.

test gate-source voltage dc, VGStst: The VGS at test conditions.

test mode: The bias condition at which a MOSFET device parameter is monitored during test.

test temperature, Ttst: The chamber ambient temperature at which the DUT is tested during the test of
the device which is typically Ttst=Tstr during the BTI stress.

test time, ttst: The cumulative test time that includes stress delay time (tstr + ).
NOTE is the stress delay time defined later in the definition list.

threshold voltage, linear, VTlin: The threshold voltage tested in linear mode.

threshold voltage, linear, VTsat: The threshold voltage measured in saturation mode.

threshold voltage, VT: The threshold voltage is the gate voltage at which an inversion layer forms at the
interface between the insulating layer (gate dielectric) and the substrate (body) of a MOSFET transistor.

well current dc, IW: The direct current into the well contact.
NOTE If the well is an n-well then IWn = IW, if a p-well then IWp=IW.

well to source voltage, stress, VWSstr: The Vws at stress conditions.

well to source voltage, VWS: The well to-source voltage.


JEDEC Standard No. 241
Page 4

4 Technical requirements

4.1 Constant current threshold Voltage VT(ci) determination

For a MOSFET at a given VDS and VWS bias condition, the constant current threshold voltage (VT(ci)) is
defined as the VGS applied to the device to result in a given ID value (IVT) at test such that VT(ci) VGS at
IVT). A typical selected value for IVT is; IVT=ID0 x (Wdes/Ldes) with ID0 being the drain current per square of
channel corresponding to a constant inversion charge density. Typically an ID0 of between 50-300 nA is
selected corresponding to a VT measured in the weakly inverted region of the device.

Figure 1 Normalized ID/IDmax (linear-log scale) as function of VGS/VDDnom in the linear region (VDS
< VDSsat). IVT=ID0 x (Wdes/Ldes) is selected such that VT(ci) is a VGS value in the weakly inverted region
of the I-V characteristic curve

By the definition of IVT, the linear VT(ci) shift relates to the VGS associated with the same amount of
inversion charge density during the BTI stress. As such, it is directly related to the induced voltage flat
band shift and mainly dependent on the VGSstr during BTI aging in a capacitor-like (VDSstr = 0) stress
configuration.

The VT(ci) extraction methodology is described in Figure 2 where, in this case, VT(ci) is obtained in the
following steps:

1) Measure the I-V curve with a given VGS step at the applied VDS and VWS bias conditions.

2) For the VGS(i) and VGS(i-1) values corresponding to ID(i-1) and ID(i) (absolute values) such that ID(i-1)
< IVT < ID(i) is used to estimate VT(ci) by the linear interpolation:

( )
( ) = ( ) ( ) ( 1) (1)
() ( )
JEDEC Standard No. 241
Page 5

4.1 Constant current threshold Voltage VT(ci) determination (contd)

The VGSstep( VGS(i) - VGS(i-1)) is selected to be small enough to validate the linear interpolation.
Generally, a VGSstep of 1025 mV is appropriate for this procedure.

Figure 2 VT(ci) definition and extraction methodology in the weakly inverted region of the IV
characteristic curve

If the selected IVT is in the log(ID)_VGS sub-threshold linear region, it is easy to show that eq. 1 describes
the VT(ci) extracted from a best fit linear interpolation of log(ID)_VGS such that:

( ) = ( ) (2)

SS is the sub-threshold slope SS = ( ( ) and B is the VGS axis intercept.

The measurement technique and step selection (VGSstep, IV averaging etc.) must result in a VT(ci) to within a
1 mV resolution. It is recommended to select the VGS steps equally distributed around the VGS value at
which VT(ci) is estimated as a mid-point interpolation.

A procedure to extract VT(ci) in step 2 of DC BTI stress/test procedure is described in section 5.


JEDEC Standard No. 241
Page 6

4.2 Characterization of linear mode VT(ci) BTI VT shifts

As indicated, the key objective of the proposed BTI dc stress/test procedure is to allow a simple and direct
measurement of the VT shift as a measure of flat band shift during a capacitor like BTI stress to compare
the BTI sensitivities of different CMOS processes or technologies. For this reason, it is necessary to
monitor a MOSFET parameter directly related to the charge build-up generated uniformly along the
channel during the BTI capacitor-like (VDS = 0) stress. The linear VT(ci) shift (see 4.1) is the most adequate
device parameter to monitor these dependencies for the following reasons:

1. In the linear region both Drain Induced Barrier Lowering (DIBL) and punch-through effects
experienced in saturation conditions are minimized.
2. By measuring the linear (VDStst << VDSsat) |VT(ci)| shift, (where << is much less than), we monitor the
effect of BTI stress induced charge buildup in a bias condition similar to the BTI-capacitor-like stress
configuration. In addition |VT(ci)| is less dependent on Source and Drain engineering and gate-length
(no dependence on short channel effects)
3. The IDlin shift is not an appropriate device parameter to use since is also very sensitive to mobility
degradation occurring during the BTI stress.
4. The BTI induced shift of other device parameters such as IDsat and VTsat are not appropriate to monitor
flatband shifts since they are strongly dependent on short channel effects.

As described, this procedure applies to the case that the BTI induced VT shift is mostly dominated by
charge build up in the gate oxide (flat band shift). In the case that mobility degradation is associated to
the BTI damage, other device parameters such as ID could be used as a possible monitor of BTI
degradation. Recommendations on how to extend this procedure to measure ID shifts (in linear or
saturation conditions) and VT(ci) shift (in saturation) during dc BTI stressing are given in Annex A.

5 BTI Stress/test procedure

This section details the BTI DC stress/test procedure to determine the mean linear VT(ci) shift
(VDS < VDSsat). The definition and methodology to estimate VT(ci) is described in section 4. As discussed,
IVT is selected in the weakly inverted region of the device IV curve to track the VT shift associated with
voltage flat band change during the BTI stress. Recommended procedures to measure VT(ci) shift in
saturation and IDsat, IDlin shifts are given in Annex. A. All the measurements are done at stress
temperature.

5.1 Description of adopted VGS/VDS stress/test waveforms

A flow chart showing the wafer level stress and test procedure to measure the VT(ci) during DC BTI aging
is given in Figure 3. Figure 4 describes the |VGS| and |VDS| stress and test waveforms associated with this
procedure.
JEDEC Standard No. 241
Page 7

5.1 Description of adopted VGS/VDS stress/test waveforms (contd)

Figure 3 Flow chart of the recommended Wafer Level BTI stress/test procedure

Figure 4 |VGS| and |VDS| stress/test waveforms in the BTI stress/test procedure
The key steps of the proposed stress and test sequence performed at constant temperature (Tstr = Ttst) are
given in this section.
JEDEC Standard No. 241
Page 8

5.2 Selection of Device under test (DUT)

Initial tests are used to select a good Device Under Test (DUT). The device to be stressed needs to meet
the design and process tolerances assumed in the technology.

5.3 Initial (before stress) VT(ci) estimation at time t0 (typically 0 s).

Estimate the initial VT(ci) (Figure 4(a)) of the unstressed device.


Follow the procedure described in 4.1 and 4.2 to estimate the initial VT(ci)(t0)
Select VGStst = VGS at IVT= VT(ci)(t0).

5.4 Stress/test Cycle

Initiate the stress/test cycle at the time t0 (typically 0 s).

During the stress cycle the device is biased using the selected stress bias (VGS = VGSstr, VDS = VDSstr = 0).
Since the typical BTI degradation follows a power law dependence with time, the recommended stress
intervals may be selected in decade time-steps in log-log scale. The cumulative stress time is

t str = t str,n where tstr,n is stress duration at a given stress cycle, n. For example, the cumulative stress
times (tstr) could be 1, 3, 10, 30, 100, 300, 1000, 3000, 10,000, and 30,000 s. In this example, the device
would be stressed for 1 s, after which, the device parameters are measured. Next, the device would be
stressed for 2 s more and the parameters are again measured followed by a 7 s stress and measurement.
This procedure continues until stress termination occurs when the final stress time (tf) is reached.

During the interim test phase at the stress time tstr, the drain current at the test time ttst = tstr+ ID(ttst) is
measured with VGStst= VGS at IVT after a given measuring delay defined as minimum equipment
timestamp to reach a stable ID measurement during testing. Guidelines on how to select are given in 5.5.

The VT(ci) shift, (VT(ci)(ttst) = VT(ci)(ttst) VT(ci)(t0)), corresponding to measured ID decrease at the test time,
ttst, is estimated as follows (see Figure 5.):

Find the ID(i)(ttst) and ID(i-1)(ttst) (absolute value) of the t0, I-V curve such that ID(i-1)(ttst) < ID(ttst) <
ID(i)(ttst) with ID(ttst) being the measured ID value at ttst.
Given AB = CD , by linear interpolation between the corresponding VGS(i-1)(ttst) and VGS(i)(ttst); the
VT(ci)(ttst) associated to ID(ttst) is given by:
( )( ) ( )
( ) = ( )( ) ( )( ) ( )( ) ( 1)( ) (3)
( )( ) ( )( )

If IVT is selected in the sub-threshold region of the IV curve at time t0, then following Figure 6, it is easy to
show that VT(ci)(ttst)is given by:
( )( )( )
( )( ) =
( )
(4a)

where: =

SS(t0) = the initial value (before stress) of the sub-threshold slope that is defined as the slope of the linear
fit of the log(IDS)_VGS in the linear part of the sub-threshold region.
JEDEC Standard No. 241
Page 9

5.4 Stress/test Cycle (contd)

Figure 5 VT(ci) extraction in the log(ID)_VGS with IVT selected in the weakly inverted region in
the I-V curve

Figure 6 VT(ci) extraction from the relation between log(ID)_VGS with IVT selected in linear sub-
threshold region of the I-V curve

It is recommended to step the VGS by 10 mV in the regression fitting region. The estimation of the
measuring delay (given that ttst = tstr+) is discussed in the following section. The testing time, ttst, is
fixed during each stress phase. The VT(ci)(ttst) shift is recorded during the BTI stress.
JEDEC Standard No. 241
Page 10

5.4 Stress/test Cycle (contd)

Table 1 Bias (Vds/Vds) and timing (tstr,n /ttst) associated with the dc BTI WL stress/test
procedure
Stress Test
t associated to tstr,n is increasing with the increasing ttst=fixed
stress/test cycle stress cycle n such that = ,
VGS VGSstr VGStst = VGS at (IVT) = VT(ci) (t0)
Measured at t0 and kept constant in
interim testing during stress
VDS VDSstr = 0 VDStst < VDsat ( 50 mV) (linear region)

5.5 Evaluation of tfit, tf, for a given

For a realistic end of life dc, VT shift estimate, it is important to make sure that the BTI damage generated
at the selected VGSstr and Tstr accelerated stress conditions is representative of the BTI aging at the VDDmax
and Tmax worst dc use conditions. BTI aging typically follows a power law dependence on stress time with
an n-exponent typically lower than 0.25. It is expected that for a VGSstr condition dominated by BTI
damage n(VGSstr) n(VDDmax) .

In Figure 7, for a given n time exponent (n(VGS1) n(VGS2) n(VDDmax)), the stress voltages VGS1 and VGS2
are adequate VGSstr conditions to investigate BTI damage. As indicated by the figure, time evolution can
be further confirmed by an observed similar time exponent n, (typically estimated at 100 khz, 50% duty
cycle) for the stress voltage VGS1. The VT shift evolution at the VGSstr condition VGS3 should not be
considered in the BTI analysis since it is representative of the time evolution due to possible hot carrier
substrate injection, HCI, damage. This region is expected to yield a large time exponent n ( 0.4 0.5).
As a guideline, it has been observed that the BTI stressing condition (n(VGSstr) n(VDDmax)) maybe met at
VGSstr range between 1.2 VDDnom and 1.7 VDDnom. This voltage range must be experimentally verified.

Figure 7 Schematic of VT(ttst) change as a function of ttst ( tstr+) for different VGSstr at
capacitor-like BTI stress conditions where a similar behavior is expected for NBTI and PBTI
degradation
JEDEC Standard No. 241
Page 11

5.5 Evaluation of tfit, tf, for a given (contd)

As described in 5.4, ttst = tstr+ where is the measuring delay. The selection of plays a critical role in
characterize the VT shift evolution as function ttst at given VGSstr and Tstr.

To illustrate this point, Figure 8 shows the generally observed trends of VT shift as function of ttst at
different values of . In the following tfit is defined as the minimum ttst value such that a similar time
exponent (n) is observed for ttst > tfit with the different VGSstr and Tstr stress conditions selected used to
develop the BTI model (similar to the graphic representation for VGS1 and VGS2 in Figure 7). It is
generally observed that a very large ( 1 s) and small ( 1 s) value of requires larger tfit to guarantee
that a similar power law exponent, n, can be used to describe the VT shift vs. tstr dependence across the
selected VGSstr and Tstr stress conditions. It is true that a VT shift power law dependence on ttst can be
obtained at any . It is, however, important that is selected to yield a similar n at the different selected
VGSstr and Tstr conditions. For a given , once tfit is defined, the time exponent, n, is obtained from a linear
fit of the log(|VT(ci)|) vs. log(ttst) relation with ttst in the time range tf ttst tfit with tf in the tf tfit time
interval that extends between 2-3 decades in time. Any values of , tfit and tf that are selected must be
demonstrated with the accelerated VGSstr and Tstr stress conditions such that a similar interval time
exponent, n, is estimated to characterize the dc BTI damage.

Figure 8 Example of the impact of selection to tfit showing that a large and small is correlated
to a larger tfit which is required for a power law regression of the VT shift vs. tstr

A minimum stress-to-test measuring delay of approximately 1 ms is typically needed from commercial


wafer level probers to allow stable settling times from waveform (VGSstr/VDSstr) to (VGStst/VDStst).
If 1 ms is adopted, a tfit 100 s is typically applicable for VGSstr range between 1.2 VDDnom and
1.7 VDDnom. For a value of much less than 1 ms, extra care needs to be paid to select tfit consistently with
its definition.

For tf > tstr > tfit the typical BTI model parameters (i.e., , Ea, n) can be estimated.

Annex C recommendations on the design of experiment involving VGSstr and Tstr to extract the BTI model
parameters.
JEDEC Standard No. 241
Page 12

5.6 IV characterization after tf

After stress, an optional IV measurement (Figure 4 (b)) may be carried out to verify that a parallel IV shift
occurs during stress which substantiates that the BTI shift is caused by flat-band shift change.

6 DC BTI fast switching technical requirements

6.1 Wafer level equipment requirements

The measurement system must be capable of the simultaneous application of voltage and measurement of
current at the gate, drain, and substrate terminals of the device. The system must be able to measure
100 nA with a 10% resolution. The voltage overshoot must not exceed 1% of the applied voltage. The
measuring delay should be on the order of a few milliseconds.

6.2 Test structure requirements

Only devices with large active area should be used to reduce the intrinsic statistical variation due to
random fluctuations in BTI induced by area scaling. Typically, a smaller channel area (Wdes x Ldes), will
require a larger sample size to reach a reasonable statistical confidence level. Refer to Annex B for
details.

MOSFETs with different gate dielectric thickness, allowed by the technology, must be evaluated. The
gate, drain and source terminals of the device must be contacted, i.e., they shall not be floating. The well
terminal used during stress/test must be at the same bias conditions as in operation (typically VW= 0 if
bulk). To minimize parasitic voltage drops between the probe pads (VProbe) and the device terminals
(Vdevice), the wiring resistances (RW) from the probe pads to the device gate, source, drain, and well are
selected such that the voltage drop (IRW) is less than 1% Vdevice.

To quantify the intrinsic BTI sensitivity, it is required to stress MOSFETs with MOL and BEOL
levels designed with the nominal antenna rules allowed by the technology design.

If a given BEOL level is protected by design rules then that gate protection must be used.

6.3 Measurement requirements

The device should be measured at the wafer-level on a stable probe station utilizing a vacuum chuck. The
chuck or fixture temperature shall be set at the stress temperature during stress and test. Once set, the
temperature must be maintained to within +/- 1.0 C of the set point for the duration of the test.

At the end of each BTI stress interval, the stress is terminated and device parameters are measured. The
stress time interval and the testing delay should be known to an accuracy of +/- 1% for stress time
intervals.
JEDEC Standard No. 241
Page 13

6.4 Hardware sampling requirements

A minimum of 3 lots with 2 wafers/lot representative of the nominal process of record (POR) hardware
should be used.

Depending on the measured variability of the BTI shifts for a given device an adequate sample size is
required to achieve an assumed statistical confidence level (90%).

A minimum recommended, 4 chips per stress bias per temperature are used for large area MOSFET BTI
characterization (see Annex B.).

7 DC BTI End of Life (EOL) estimation for a wide device

The absolute value of mean VT(ci)(shift, ( ( ) ), dependence on VGSstrs and tstr is typically given by
one of the following equations:

( ) = (5a)

or

( ) =C (5b)
where:
Tox has the value measured in line
Ea is the temperature activation energy (eV)
n is the stress time exponent.
is the voltage acceleration exponent.

In the tf tstr tfit range a procedure on how to estimate the values of the model parameters C, n, Ea and
is given in the Annex C.

The coefficients C, n, Ea and of the dc BTI model are estimated for a wide device and are representative
of the CMOS process under evaluation. A wide device is stressed to reduce the random fluctuation
contributions to BTI aging. Annex B gives the recommended procedure to select and design a large active
area device for BTI stressing. Typically a MOSFET with Ldes = Lnom and Wdes > 1 m can be used for BTI
modeling.

This procedure recommends a DC BTI mean VT(ci) shift estimate at a given End of Life (EOL) as a means
to compare BTI sensitivity between CMOS processes or technologies. From eq. 4, once the BTI model
parameters are estimated, the mean VT(ci) shift at an agreed dc EOL () for the worst case use conditions
VDDnom(VDDmax) and channel temperature (TMAX) is given by:

( ) =C (6a)
or

( ) = C (6b)

For an agreed dc lifetime a mean shift <VT(ci)> can be estimated. Comparison of different processes or
technologies is done using the estimated VT shift.
JEDEC Standard No. 241
Page 14

8 Required reporting

To ensure consistency, the following information relevant to the MOSFET BTI measurement shall be
reported.
Table 2 Parameters to be reported
Required information Description
Test Transistor Provide information sufficient to uniquely identify the MOSFET tested. Lot
Identification #, Wafer #, chip location in the wafer
Device Wdes/Ldes Wdes used to estimate process (Typically Wdes > 1 m) for Ldes = Lnom.
Technology/process Key elements of the MOSFET device design such as gate dielectric process,
features source/drain engineering etc.
VDDnom The nominal power supply for the technology under investigation.
TMAX The maximum junction temperature specified at use conditions for the
technology under consideration
Tox TOX value entered in the BTI model (Toxgl, Tinv, etc.) and adopted for the oxide
thickness of the selected device as part of the inline monitoring.
NOTE A description of the methodology adopted to estimate Tox is part of the
required reporting.
VGSstr, VGStst The MOSFET gate-source applied during stress and at test
VDSstr, VDStst The MOSFET drain-source applied during stress and at test
Stress and test The temperature at which the DUT has been stressed during the BTI stress.
temperature. It is assumed that the test temperature is the same as the stress temperature
(TMAX)
Initial values of The initial (pre-stress) values of the selected device parameters in the
selected device appropriate test mode condition such as SS(0) and VT(ci)(0).
parameters
VT(ci) shift at a given The expected linear VT(ci) shift at an assumed dc end of life at the worst-case
life use conditions VDDmax and Tmax.
VGS/VDS measuring Minimum equipment timestamp to reach a stable Id measurement during
delay () testing
tfit Minimum ttst values such that for ttst > tfit VT(ci) vs. ttst has power-law
dependence with time exponent, n (VGSstr, Tstr)constant in the selected VGSstr,
Tstr for the BTI stressing
n, , Ea BTI Model parameters.
JEDEC Standard No. 241
Page 15

8 Required Reporting (contd)

Table 3 Summary Table: Key elements of the recommended procedure


Features Criteria
Stress/test methodology Two-step VGS/VDS waveform (VGSstr, VDStst = 0 V) to (VGStst= VGS at IVT,
VDStst < VDsat) at controlled measuring delay (1 s 2 ms).
Device Wdes/Ldes Wdes selected to estimate Process (Typically Wdes > 1 m ) for Ldes = Lnom.
Characterization during ID measured at VGStst= Vgs at IVT and VDStst < VDsat. (linear region) (Single
interim testing Point measurement)
Device parameter VT(ci) in linear region
extracted during stress
Parameter shift to VT(ci) = VT(ci) (tstr +) VT(ci)(0) (Mean VT shift)
monitor during stress
Process/Technology Mean VT(ci) associated with a dc lifetime at the worst-case application
comparison. VDDnom (VDDmax) and temperature (Tmax)
VGS at stress selection VGstr selected at accelerated conditions to represent the BTI damage active
at the assumed dc use conditions
VDS @ stress VDSstr=0 V (capacitor-like stress)
Suggested total stress tf 100x-1000x tfit with tfit determined by (1 s 2 ms)
time
Sample size 3 lots/2 wafers/lot of nominal TOX with a minimum of 4 chips/wafer for
each selected VGSstr at each stress temperature.
Measuring delay. Evidence of a stable ID measurement after switching from
stress to test is required.
Voltage activation Extracted from power/exponential, VGSstr/TOX, law fit
n exponent Extracted from log-log linear fit in tfit < tstr < tf time range covering 3 orders
of magnitude for a given .
Provide evidence of power-law dependence on time No saturation effects.
JEDEC Standard No. 241
Page 16

Annex A (informative) Recommendations to estimate alternate device parameters

The preceding procedure is intended to be the most basic method for process comparison. To complement
the capacitor-like DC procedure for BTI the following additional information may be provided:

AC BTI characterization
Estimation of VT(ci) in saturation, IDsat, IDlin shift during BTI stress.

A.1 AC BTI characterization

An alternative way to insure that the n exponent estimated from the dc measurements is adequate to
describe the evolution of BTI physical damage another method is to compare the dc to ac BTI evolution
(ac conditions: 50% Duty Cycle and frequency range, f 10 kHz-100 kHz). At a given VGS and Tstr, the
VT shifts measured by dc stress/test methodology and ac (50% duty cycle) should follow the same time
evolution with the same time slope, n. If a difference is observed, further investigation is recommended.

A.2 Estimation of VT(ci) in saturation, IDsat, IDlin shift during BTI stress

The methodology so far proposed describes how to extract and model linear VT(ci) shift produced by BTI
damage as it relates to the voltage flat-band shift. It is sometimes required to establish a correlation
between the BTI damage and a key device parameter different from the linear voltage threshold change
measurement. Two procedures are recommended to monitor the shifts of VT(ci) in saturation, IDsat, IDlin.

Extension of the proposed stress/test procedure


Device parameter shift from correlation with VT(ci) linear shift.

A.2.1 Extension of stress/test procedure

The procedure described in section 6 can be extended to include measurements of the VT(ci) in saturation,
IDsat and IDlin shifts by setting VGStst=VGS, VDStst=VDS to measure the parameter of interest.

Table A.1 Stress/test bias conditions for each of the device parameters under consideration and
the corresponding shifts to be monitored
Stress Test Shift to monitor
VT(ci) in VGS = VGSstr VGStst = VGS at IVT VT(ci) (ttst) = VT(ci) (ttst) VT(ci) (0)
saturation VDS = 0 VDStst = VDDnom
IDlin VGStst = VDDnom IDlin (ttst)/IDlin (0) (fractional change)
VDStst < VDsat (50 mV)
IDsat VGStst= VDDnom IDsat(ttst)/IDsat (0)
VDStst= VDDnom

When testing in the saturation region it is extremely important to carefully quantify the measuring delay
such that no voltage VGS/VDS overshoot or undershoot conditions are allowed. The stress/test waveform
must be optimized to reduce CHC effects during switching and an appropriate quantification of tfit and tf
is required which, in turns, depends on the value of .
JEDEC Standard No. 241
Page 17

A.3 Estimation of IDsat, IDlin and VTsat saturation shift from the correlation with VT(ci)

The fractional IDlin and IDsat as well as VTsat (VT(ci) in the saturation region) are plotted as a function of
VTlin shift (VT(ci) in the linear region) in arbitrary units during the NBTI stress measured at different
delay times (between = 2 ms and = 1 s). Figure A1, describes the observed correlation between these
key device parameters NBTI damage related shifts measured using the DC BTI stress/test methodology.

Figure A.1 Fractional IDsat, IDlin and VTsat shift as function of VTlin shift

It can be observed that, for a given device geometry, use conditions (VDDnom) and stress temperature, a
linear relation can be established between these device parameters. This relation holds irrespective of the
VGstr conditions and . Similar trends, but with different linear dependence between these device
parameters, are also expected for PBTI stressing.

These findings suggest that a BTI characterization can be done as follows:

1. Monitoring and modeling of VT(ci) shift in linear region by use of the proposed stress/test BTI
methodology.
2. Characterizing the relation between the VT(ci) linear shift and the other three parameters of interest by
running IV testing during interim testing making sure that the IV testing is done with the same testing
sequence and delays during the BTI stress.
JEDEC Standard No. 241
Page 18

Annex B (informative) Selection of a wide device

For a MOSFET with a given design width Wdes(fixed Ldes) the standard deviation associated to the VT(ci)
cumulative distribution induced by BTI degradation is given by:
( ) = + ( ) (B.7)
where:
(<|VT(ci)|>) is the mean of the VT(ci) distribution
process is the standard deviation (constant with stress time) of the cumulative VT(ci) distribution
associated to the intrinsic variations (Tox, well profile variation, etc.) and tolerances of the adopted
CMOS process. This parameter is estimated by stressing a sufficiently wide MOSFETs with Wdes that
is much greater than Wmin and relates to BTI chip to chip, wafer to wafer and lot to lot variations.
process is associated to the cumulative distribution of the BTI model (see eq. 5) prefactor, C, as
follows. Typically the distribution of prefactor, C, is normal such that: N( <C>, 2(C)) with mean
<C> and variance 2(C). For (C)/<C> << 1 (mature POR process) the C distribution can be
approximated to a lognormal such that: ln(C) N(<C>, 2(C)/<C>2 ).
Since, ln ( ) ln(C) + f , , , + n ln ( ) for a control CMOS process
it is expected that:

), (C) (C)
ln ( ) N(C) + f , , , + n ln( C

so that the cumulative VT(ci) distribution at a given VGSstr,Tstr and tstr can be approximate to a
lognormal with mean:
( )( ) C + f , , , + n ln ( ), and
variance (|VT(ci)|) (C)/<C>2.
2 2

The last parameter being constant with stress time.


Figure B.1 describes the expected trends as function of stress time of the cumulative VT(ci) shift
distribution due to BTI shift for a wide MOSFET for a manufacturable CMOS process. For a mature
process 2(VT(ci)) 2(C)/<C>2 0.03-0.0.5. This means that the 2(|VT(ci)|) associated to the a
mature CMOS process variability is much smaller than the mean ( ) ( ) . This consideration
justify why a sample size of the order 8 per wafers are sufficient to get an estimate of ( ) ( )
with a reasonable 95% probability of 10% relative error.
narrow(<|VT(ci)|>) is the standard deviation associated to narrow width device BTI induced effects
given by random fluctuations and defined as:
( )
= (B.8)

Figure B.2 shows the expected BTI variance (2W) dependence on stress time as a function of Wdes for a
fixed Ldes.
In the proposed BTI stress/test procedure the recommended width of the MOSFET device (at fixed Ldes)
to be stressed is such that Wdes > Wmin with w(<|VT(ci)|>) process. The estimated value of Wmin strongly
depends on the assumed EOL VT(ci) shift as well the TOX, Ldes of the device under evaluation. Typically a
value around 1 um is acceptable.
JEDEC Standard No. 241
Page 19

Annex B (informative) Selection of a wide device (contd)

If the MOSFET to be evaluated has a design width Wdes less than the minimum width (Wmin) associated to
the defined technology/process, it is recommended to use a MOSFET based layout with total width (Wtot)
such that = with y Wmin/Wdes. Figure B.3 shows a possible MOSFET based layout to be
adopted. Other layouts are obviously possible.

Figure B.1 Typical large area device VT(ci) cumulative distribution as function of stress time for
a given VGSstr and Tstr.. <|VT(ci)(tstr)|> and process(VT(ci)) = constant are associated to process
variation.

NOTE Wmin is the minimum Wdes recommended in this stress/test BTI procedure.

Figure B.2 Typical BTI induced variance dependence on Wdes (fixed Ldes) as function of stress
time
JEDEC Standard No. 241
Page 20

Annex B (informative) Selection of a wide device (contd)

Figure B.3 Possible MOSFET layout to be adopted with = if Wdes < Wmin
JEDEC Standard No. 241
Page 21

Annex C (informative) Experiment design to find wide device dc BTI model parameters

Different Designs of an Experiment (DOE) involving VGSstr and Tstr combinations as well as hardware
needs can be adopted to estimate the BTI model parameters for an accurate EOL mean VT shift evaluation
at selected worst dc use conditions. In this standard this estimation is limited to the BTI mean VT shift
associated to the variability of a manufacturable CMOS process (not BTI induced random fluctuations) by
using a large area MOSFET (see Annex B).

Since the validity of the EOL mean VT shift estimation strongly depends on the values of the BTI model
parameters (see eq. 6), any DOE strategy can be adopted as long as the supporting statistical analysis on
the accuracy of the above parameters is provided.

Here we illustrate as an example, two different DOE requiring a combination of VGSstr and Tstr bias
conditions that can be used for the BTI model parameters estimation.

Example 1: One-factorial at the time DOE

It is assumed that in the voltage and temperature stress range under consideration there is no cross
interaction between the different BTI model parameters (i.e., Ea, , n are constant and not function of the
BTI mechanism physical drivers, VGSstr and Tstr). This means that the one-factor at a time DOE can be
applicable in this case.

Table C.1 provides an illustration of the minimum recommended VGSstr (5) and Tstr (3) stress
configurations distributed across 2 wafers/lot over 3 lots. As discussed in section 6, the VGSstr and Tstr are
selected to insure that:

BTI damage generated during the stress is controlled by the same physics that are activated in dc use
conditions.
Reasonable VT shift is measured within the expected wafer level stress time (<10ks)

A typical combination is VGSstr= 1.2 VDDnom, 1.4 VDDnom, 1.5 VDDnom 1.6 VDDnom, 1.7 VDDnom and Tstr = T1 <
Tnom, T2 = Tnom, T3 =Tmax. Any other selection of VGSstr and Tstr can be used as long as at accelerated stress
conditions the same BTI physics is activated as at use conditions. For each stress configuration, a
minimum of 8 chips/wafer/bias/temp are recommended for a large area devices (see Annex B).

Table C.1 Illustration of the stress bias test and minimum recommended distribution across the
VGSstr /Tstr stress bias conditions for the hardware
Tstr
1.5 1.5 1.2 1.4 1.5 1.6 1.7
VGSstr x VDDnom
1/1 X
1/2 X
Lot/wafer 2/1 X X X X X X X
(Tox-Nom) 2/2 X X X X X X X
3/1 X
3/2 X
JEDEC Standard No. 241
Page 22

Annex C (informative) Experiment design to find wide device dc BTI model parameters (contd)

Example 1: One-factorial at the time DOE (contd)

BTI Model parameter estimation

Two step process.

1) Selection of wafers to run DC BTI model parameters estimation


Run BTI stresses with VGSstr = 1.5 V and Tstr = T3 over the 6 wafers (2 wafers/lot) listed in Table
C.1. A minimum of 4 chips/wafer should be used for each stress.
Estimate the mean of the VT(ci)(ttst) distribution (lognormal) at a given ttst.

2) DC BTI model parameters estimation


Run different BTI stresses (VGSstr between 1.2 VDDnom and 1.7 VDDnom at Tstr = T3 and Tstr between
T1and T3 with VGSstr = 1.5 VDDnom) on wafers with VT(ci)(ttst) near the mean shift estimated in step
1. and extract the BTI model parameters on these wafers as follows:
1) Take the logarithm of both sides of eq. 5 to yield the equation:
( ) = ( ) + ( ) ( ) (C.1a)

or
( ) = ( ) + ( ) ( ) (C.1b)

2) Perform a linear regression on the data from the adopted VGSstr/Tstr stress matrix obtaining the
estimate of the parameters C, n, Ea and for the stress times tf tstr tfit over 2 to 3 orders of
magnitude range.
3) Report the best fits values of the BTI model parameters together with the statistics associated
to a linear fit (standard error values, F statistics, degrees of freedom, etc.).
JEDEC Standard No. 241
Page 23

Annex C (informative) Experiment design to find wide device dc BTI model parameters (contd)

Example 2: Cross factorial DOE

For a high accuracy of the model parameters (see eq. 5, and eq. 6) with a given sample size and/or for
testing a possible interaction between temperature and bias a factorial design can be used. An example is
given Table C.2.

Table C.2 Illustration of the stress bias test and minimum recommended distribution across the
VGSstr/Tstr stress bias conditions for each lot and wafer
Tstr
T1 T2 T3
1.2VDDnom X X
VGSstr 1.5VDDnom X
1.7VDDnom X X

A typical combination is VGSstr = 1.2 VDDnom, 1.5 VDDnom, 1.7 VDDnom and Tstr = T1 < Tnom, T2 = Tnom, T3 =
Tmax. In any case the selection of VGSst and Tstr is such that at accelerated stress conditions the same BTI
physics is activated as at use conditions. A minimum of four chips per VGSst and Tstr.

This scheme can be replicated for different lots and wafers.

BTI Model parameters estimation

Run the suggested BTI stresses (VGSst between 1.2 VDDnom and 1.7 VDDnom at Tstr=85 C (T1), 105 C (T2),
125 C (T3) on each wafer and extract the BTI model parameters following this process:

1) Take the logarithm of both sides of eq. 5 to yield the equation:

( ) = ( ) + ( ) ( ) (C.2a)

or
( ) = ( ) + ( ) ( ) (C.2b)

2) Perform a linear regression on the data from the adopted VGSstr / Tstr stress matrix obtaining the
estimate of the parameters C, n, Ea and for the stress times tf tstr tfit over 2 to 3 orders of
magnitude range over all selected wafers.

3) Report the best fits values of the BTI model parameters together the statistics associated to a linear fit
(standard error values, F-statistics, degrees of freedom etc.).
JEDEC Standard No. 241
Page 24
Standard Improvement Form JEDEC

The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry
regarding usage of the subject standard. Individuals or companies are invited to submit comments to
JEDEC. All comments will be collected and dispersed to the appropriate committee(s).

If you can provide input, please complete this form and return to:

JEDEC Fax: 703.907.7583


Attn: Publications Department
3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2107

1. I recommend changes to the following:


Requirement, clause number

Test method number Clause number

The referenced clause number has proven to be:


Unclear Too Rigid In Error

Other

2. Recommendations for correction:

3. Other suggestions for document improvement:

Submitted by
Name: Phone:
Company: E-mail:
Address:
City/State/Zip: Date: