MWE2011, EMC Technology Considering RF Noise, Workshop #4

Sponsored by IEICE APMC Japan National Committee

EMC Analysis for a PCB Mounted Switching

regulator using Electromagnetic simulator

A Simple and Practical Measurement-based Modeling

Method Proposal for Switching Regulator
A Simple PI Simulation Scheme Using the Model
Mitsuharu Umekawa
Dec. 1st , 2011

EDA Application Engineering

Electronic Measurement Group
Agilent Technologies

MWE2011-Workshop-04 Yokohama
1 2011/12/1
Contents

1. Introduction SI/PI/EMC
2. PDN modeling issue VRM Measurement-based modeling
3. Measurement-based DCDC Converter modeling
Evaluation board for VRM
Measurement
De-Embedding connector portion to extract DCDC converter behavior
4. PI analysis using the VRM model
Evaluation board for other than VRM
Estimating SI/EMI by simulation using EM and VRM model
Comparison between simulation and measurement and validity discussion
5. Conclusion

MWE2011-Workshop-04 Yokohama
2 2011/12/1
SI/PI/EMC Signal causing EMI
(Normal Mode)
Choking
Signal Integrity Beads
EMI/EMS

Visualize problems using simulator

Organically
to find/predict root-cause,
PDN Ripple
Inter-related PDNPWR/GND
causing Signal
to estimate effectiveness of the measures
causing EMI
ripple DeCap and Interactive DeCap
optimization optimization
/Layout /Layout
Modification Power Integrity Modification
PDN High-impedance for PDN Impedance
Anti-resonance
at specific frequency
140

IC operation band 120

100
Impedance (ohm)

80

60

40

20

0
Common
Protocol
-20
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Mode Filter
SSN(SSO) freq, GHz

PDN Ripple modification /DeCap

Common Mode EMI for
Receiver wrong operation /Layout Differential line optimization
Modification /Layout
Modification
MWE2011-Workshop-04 Yokohama
3 2011/12/1
PDN modeling and issue

Basic PDN Modeling Idea

PDN
= Power Line + VRM + GND Plane
Input Impedance
=Impedance seen from device
PWR VRM
IC
?
GND

EM or Measurement
Issue
VRM = DCDC Converter, Integrated Module, Non Adjustable
No easy to have VRM equivalent model

Idea
Measure VRM using VNA as a black box to extract AC characteristics
Simple and practical measurement-based modeling with EM

MWE2011-Workshop-04 Yokohama
4 2011/12/1
Contents

1. Introduction SI/PI/EMC
2. PDN modeling issue VRM Measurement-based modeling
3. Measurement-based DCDC Converter modeling
Evaluation board for VRM
Measurement
De-Embedding connector portion to extract DCDC converter behavior
4. PI analysis using the VRM model
Evaluation board for other than VRM
Estimating SI/EMI by simulation using EM and VRM model
Comparison between simulation and measurement and validity discussion
5. Conclusion

MWE2011-Workshop-04 Yokohama
5 2011/12/1
DCDC Converter Evaluation Board
Synchronous Buck type DCDC Converter
Simplified Schematic

Switching Control IC Output Filter

Vin (TI - TPS54310) Vout

DeCap

DeCap

Compensation Circuit

MWE2011-Workshop-04 Yokohama
6 2011/12/1
 DCDC Converter Evaluation Board
Configured to output 3.36V

1:Buck Type DCDC converter

IC [TI, TPS54310]
.1x.1, Connected to DCDC
From DPS converter module
2:Output Filter
30[mm]

Composed of a 1.5uF inductor

and 180uF polymer capacitor
3:Output Decoupling
Capacitor
1000pF ceramic

4:Input Decoupling Capacitor

10uF ceramic
5:Compensation circuits for
feedback system
6:Voltage Detection point to
67[mm] TPS54310 feedback pin
7:Boardmount Socket
.100x.100, 16pins
3.36V output, 3A Maximum
8:Power Terminal
4-6V input

MWE2011-Workshop-04 Yokohama
7 2011/12/1
Connection for measurement
Shunt-Through measurement fixture and PCB
mounting header for DCDC converter module

VNA Port2

DCDC converter Measurement

From DPS module Fixture
30[mm]

67[mm]

VNA Port1 To SMU

From DPS
(5.5[V] const., 2[A] compliance)

MWE2011-Workshop-04 Yokohama
8 2011/12/1
Test setups

1:Vectol Network Analyzer [Agilent

Technologies, E5061B ]
2:Gain/Phase Port
[5Hz-30Mhz]
3:S-para Port
[ -3Ghz]

4:DC Power Supply/ Analyzer

[Agilent Technologies, N6705
Mainframe]
5:CH1 N6762A Precision DPS Module
6:CH4 N6781A SMU Module

7:DUT
DCDC module and shunt-through
impedance measurement fixture

MWE2011-Workshop-04 Yokohama
9 2011/12/1
Measurement Method dp1
DUT Example
ZO=50?
low impedance
Shunt-Through Method at low frequency
C1 L1
Shunt-through method has the advantage of C=3pF L=240mH
measuring low impedance at low frequency.
Zdut = 50 x S21/(2 x (1-S21))
where port impedance = 50Ohm

dp2
ZO=50?

Small Where trace noise adversely

residual affects measurement result

Where dynamic range adversely affects

measurement result

MWE2011-Workshop-04 Yokohama
10 2011/12/1
Calibration
3 Standards are used;

LF impedance measurement
Response Through to improve transmission tracking and isolation
Using this response cal, Inductance factor remains as residual error. For <30Mhz, now this error is thought to be small
enough and ignored.

HF impedance measurement
Electrical Cal Module for 2 port full calibration to cable terminal

DC Blocking Capacitor

2-port Short for Auto Port extension from cable terminal to DUT

MWE2011-Workshop-04 Yokohama
11 2011/12/1
DCDC module measurement results
Measurement and DUT condition:
DCDC module is turned on by DPS and SMU sinks current as electrical load.

Connector intersection
Various
impedance
dependent on
200mA
sunk current
600mA
condition 1400mA
2200mA
HF 30MHz-3GHz

Output filter

Various current condition shows small difference in impedance at very low

frequency where a feed-back loop works.
At higher than 10kHz frequency range, all measurements show identical
response.

MWE2011-Workshop-04 Yokohama
12 2011/12/1
Simplification to model a connector intersection
and EM simulation

EM
(FEM)

Agilent
ADS-FEM

birds-eye view for a connector intersection

MWE2011-Workshop-04 Yokohama
13 2011/12/1
Validity check for EM result
When DCDC control IC is turned off, output filter and DeCap are seen from Vout.

High-side
Switching
SW Control IC Output Filter
Vin HDRV
(TI - TPS54310) Vout

LDRV

Low-side
SW

Turned offHigh Impedance

DeCap

DeCap

Compensation Circuit

MWE2011-Workshop-04 Yokohama
14 2011/12/1
Validity check for EM result

In condition that DCDC control IC is turned off, this shows good

correlation between measurement and simulation.
EM result is valid.
Measurement
(Turned off)
Filter+Concector
Filter/DeCap Only
(Reference)

Impedance [Ohm]
EM result

Filter/Decap

MWE2011-Workshop-04 Yokohama
15 2011/12/1
DeEmbedding connector characteristics from
DCDC evaluation board measurement result
DeEmbedded result is about equal to output filter characteristics with DeCap.
Connector intersection is removed as expected generally.
Measurement-based VRM model
Large reflection by the connector header/socket makes DeEmbedding difficult.

Measurement(1A)
DeEmbed result
Filter/DeCap Only

Impedance [Ohm]
(Turned off/Reference)

DCDC modules
characteristics

DeEmbedding

MWE2011-Workshop-04 Yokohama
16 2011/12/1
Contents

1. Introduction SI/PI/EMC
2. PDN modeling issue VRM Measurement-based modeling
3. Measurement-based DCDC Converter modeling
Evaluation board for VRM
Measurement
De-Embedding connector portion to extract DCDC converter behavior
4. PI analysis using the VRM model
Evaluation board for other than VRM
Estimating SI/EMI by simulation using EM and VRM model
Comparison between simulation and measurement and validity
discussion
5. Conclusion

MWE2011-Workshop-04 Yokohama
17 2011/12/1
Evaluation board conceptual diagram

EMI Impedance
From Inverter IC

74LCX04F
DCDC Decoupling Signal
Inverter IC
Converter Capacitor

50Ohm Waveform
Termination Observation

Reference
DCDC converter External
evaluation board Function
(discussed previously) Generator

Evaluation board

MWE2011-Workshop-04 Yokohama
18 2011/12/1
SI/EMI evaluation board

58[mm]


Connect
DCDC converter
evaluation board
100[mm] here
1:Boardmount Header
2:74 logic 04 inverter [Toshiba,
74LCX04F]
3:50 Ohm single-ended line
with 50Ohm termination
130mm length
4:DeCap mounting pads
5:Power Plane
6:Signal input for the logic
inverter IC
7:Local Pattern Generation
Circuits for the inverter IC

MWE2011-Workshop-04 Yokohama
19 2011/12/1
 Analogy and Ground/Power Plane Modeling
Emission of
PDN(Pwr/Gnd/VRM)
Radiation
= Inductance and Resistance
= Resistance

VRM
Generated VRM model
IC

DeCap
Dissipation of
Parallel Flat Plane
PCB Prepreg/Core
= Capacitor
= Resistance

Note: This analogy is applied to PDN behavior at lower frequency than self-resonance point

MWE2011-Workshop-04 Yokohama
20 2011/12/1
Relationship between anti-resonance and
reflection ratio
Parallel Power Dissipation/
PDN Flat Plane Emission

DeCoupling
Power-to-Ground model for PCB Capacitor

Note: Term impedance is equal to input impedance to calculate S11 correctly.

Z=50Ohm is just an example for the explanation.

MWE2011-Workshop-04 Yokohama
21 2011/12/1
 Relationship between anti-resonance and
reflection ratio

Impedance [Ohm]
PCB Only
With DeCap

This circuit model has anti-resonance

frequency
Putting DeCap moves anti-resonance
frequency

Reflection at Anti Resonance S11 [dB]

frequency is small,
meaning power is consumed as real
power.

MWE2011-Workshop-04 Yokohama
22 2011/12/1
Input Impedance and reflection simulation
linear(AC) analysis with DeCap optimization
Measured data
as a power internal impedance

EM result
(Method of Momentum)
Agilent ADS-Momentum

1:DCDC converter module
Frequency response
Measured impedance
2:Terminated Resistor
3:Current AC source and 200mA case is used
Voltage sense
DeCap 50mA AC current
for VRM measured impedance
for this case.
4:DeCap for inverter IC

MWE2011-Workshop-04 Yokohama
23 2011/12/1
 A Prediction/Estimation of SI/EMI problem from linear
simulation results
Impedance and reflection seen from IC power pin
2e3
1e3
High impedance
- SI problem
Impedance [Ohm]

1e2
20Ohm Small reflection
1e1
- EMI problem
1
DeCap Optimization
1e-1 70Mhz 240Mhz - Low impedance and
1e-2
small reflection
0 - Current flows to low
impedance path
-6

S11 [dB]

-12 Side effect of DeCap

installation
-18

Optimized DeCap
-24 Without Decap
1400pF SMD
With Optimized Decap 580pF SMD
-30 [MHz] in parallel
10 100 1000

MWE2011-Workshop-04 Yokohama
24 2011/12/1
Experimental proof of the estimation
Test Setups Test Item No DeCap Opt. DeCap

Signal Shape at 70MHz Bad Better

EMI at 70MHz Bad Better

EMI at 240 MHz Worse

1:Spectrum Analyzer [Agilent

Technologies, N9010A ]
9kHz to 26.5GHz
2:Function Generator [Agilent
Technologies, 81160A]
3:EMI Scanner Probe Array
[EMSCAN, EMxpert]
5kHz to 4GHz
4:Scanner Adapter [EMSCAN,
EMxpert]
5:EMI Scanner controller
[EMSCAN, EMxpert software
for PC]
EMSCAN 6:Osilloscope [Agilent

EMxpertTM Technologies, MSO7104B]

7:DC Power Supply [Agilent
Technologies, E3631A]

MWE2011-Workshop-04 Yokohama
25 2011/12/1
Experimental proof of the estimation for SI
Inverter output waveform at a termination without DeCap
10MHz CLK 25MHz CLK 50MHz CLK

Getting worse

60MHz CLK 66MHz CLK

70MHz CLK 75MHz CLK

Getting better again

MWE2011-Workshop-04 Yokohama
26 2011/12/1
Time-domain response analysis using IBIS

IC_PWR

IC_OUT1

IC_OUT2
IC_OUT1
Vout_Term

IC_OUT2 IC_GND

EM result
IC_PWR (Method of Momentum)
Agilent ADS-Momentum
IC_GND

1:IBIS for 74LCX04 output

2:Trigger for CLK waveform
DeCap
generation
3:Termination resistor and
probe parasitics
8pF and 1nH

MWE2011-Workshop-04 Yokohama
27 2011/12/1
 Experimental proof of the estimation for SI
Inverter output waveform at a termination with/without DeCap
66MHz CLK
Installing DeCap improves the inverter output SI at a termination.
IBIS simulation result also shows a good correlation to
measurement result with/without DeCap.

Without DeCap With Optimized DeCap

Voltage at termination[V]
Voltage at termination[V]

IBIS Simulation IBIS Simulation

Measurement Measurement

MWE2011-Workshop-04 Yokohama
28 2011/12/1
 Experimental proof of the estimation for EMI
70MHz EMI Scan and Current density
Installing DeCap suppresses the board-wide EMI at 70MHz
Without DeCap With Optimized DeCap
Spectrum
Analyzer
Current Density
Simulation

10[A/m] 10[A/m]
I I
0.3[A/m] 0.3[A/m]

MWE2011-Workshop-04 Yokohama
29 2011/12/1
 Experimental proof of the estimation for EMI
240MHz EMI scan and Current density
Installing DeCap causes anti-resonance around 240Mhz and affect the EMI
without DeCap With optimized DeCap
Spectrum
Analyzer
Current Density
Simulation

10[A/m] 10[A/m]
I I
0.3[A/m] 0.3[A/m]

MWE2011-Workshop-04 Yokohama
30 2011/12/1
Summary and Conclusions

Measurement-based simple and practical VRM modeling

method is proposed.
Reasonable correlation between simulation and SI/EMI
measurement demonstrates validity of the VRM model and
the simple linear PI simulation method.

Considerations for further study

Better connector selection to extract better VRM characteristics
Simpler VRM modeling for DeCap optimization around active devices
Case study for differential devices and evaluation of far field by common
mode change on a differential transmission line

MWE2011-Workshop-04 Yokohama
31 2011/12/1
Acknowledgements

I am deeply grateful to Etoh-san, Toyo Corporation (Toyo

Technica), a representative of EMSCAN, about offering EMxpert
lend-out for my experimental study.

MWE2011-Workshop-04 Yokohama
32 2011/12/1