Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
REFRESH CYCLES
Table 1
There are different cycles you can use to refresh DRAMs,
STANDARD DRAMS AND REFRESH all of which can be used in a distributed or burst method.
SPECIFICATIONS There are three types listed in a standard data sheet:
?R?A/S-ONLY REFRESH
REFRESH NUMBER OF REFRESH
?C?A/S-BEFORE-?R?A/S REFRESH
DRAM TIME CYCLES RATE
HIDDEN REFRESH
4 Meg x 1 16 ms 1,024 15.6s
256K x 16 8 ms 512 15.6s
256K x 16 64 ms 512 125s
(L version) Distributed
Refresh
4 Meg x 4 32 ms 2,046 15.6s
Burst
(2K) Refresh
4 Meg x 4 64 ms 4,096 15.6s Time
(4K) Each pulse represents Required time to
a refresh cycle complete refresh of all rows
TN-04-30 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DT30.pm5 Rev. 2/95 1 1995, Micron Technology, Inc.
TN-04-30
TECHNOLOGY, INC. VARIOUS METHODS OF DRAM REFRESH
?R?A/S-ONLY REFRESH
To perform a ?R?A/S-ONLY REFRESH, a row address is put to supply or keep track of row addresses. A drawing of one
on the address lines and then ?R?A/S is dropped. When ?R?A/S CBR REFRESH cycle is shown in Figure 3. ?C?A/S must be held
falls, that row will be refreshed and, as long as ?C?A/S is held low before and after ?R?A/S falls to meet tCSR and tCHR.
high, the DQs will remain open. (See Figure 2.) Figure 4 shows three CBR REFRESH cycles. In this drawing,
It is the DRAM controllers function to provide the ad- ?C?A/S stays low and only ?R?A/S toggles. Every time ?R?A/S falls
dresses to be refreshed and make sure that all rows are a refresh cycle is performed. ?C?A/S may be toggled each time,
being refreshed in the appropriate amount of time. The row but its not necessary.
order of refreshing does not matter; what is important is
that each row be refreshed in the specified amount of time. CBR POWER SAVINGS
Since CBR REFRESH uses the internal counter and not an
?C?A/S-BEFORE-??R?A/S REFRESH external address, the address buffers are powered-down.
?C?A/S-BEFORE-?R?A/S REFRESH, also known as CBR RE- For power sensitive applications, this can be a benefit,
FRESH, is a frequently used method of refresh because it is because there is no additional current used in switching
easy to use and offers the advantage of a power savings. A address lines on a bus, nor will the DRAMs pull extra power
CBR REFRESH cycle is performed by dropping ?C?A/S and if the address voltage is at an intermediate state.
then dropping ?R?A/S. One refresh cycle will be performed
each time ?R?A/S falls. ?W/E must be held high while ?R?A/S falls. CBR REFRESH IS EASY TO USE
The DQs will remain open during the cycle. Since CBR REFRESH uses its own internal counter, there
Heres how CBR REFRESH works. The die contains an is not a concern about the controller having to supply the
internal counter which is initialized to a random count refresh addresses. Virtually all DRAMs support CBR RE-
when the device is powered up. Each time a CBR REFRESH FRESH and the 15.6s refresh rate, so you can design for
is performed, the device refreshes a row based on the CBR REFRESH at the distributed rate of 15.6s and plug in
counter, and then the counter is incremented. When CBR many different DRAMs without having to worry about
REFRESH is performed again, the next row is refreshed and refresh. For example, the 4 Meg x 4 comes in two versions:
the counter is incremented. The counter will automatically 2,048 cycles in 32ms
wrap and continue when it reaches the end of its count. 4,096 cycles in 64ms
There is no way to reset the counter. The user does not have
tRC
tRAS tRP
V IH
RAS V IL
tCRP tRPC
V IH
CASL V IL
and CASH
tASR tRAH
V IH
ADDR V IL ROW
V
Q V OH OPEN
OL
DONT CARE
UNDEFINED
Figure 2
?R?A/S-ONLY REFRESH
TN-04-30 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DT30.pm5 Rev. 2/95 2 1995, Micron Technology, Inc.
TN-04-30
TECHNOLOGY, INC. VARIOUS METHODS OF DRAM REFRESH
If CBR REFRESH is used, simply maintain the standard minimum of tRP) and then low. Since ?C?A/S was low before
15.6s refresh rate. If ?R?A/S-ONLY REFRESH is used, ad- ?R?A/S went low, the part will execute a CBR REFRESH. In a
dresses must be supplied as follows: READ cycle the output data will remain valid during the
A0-A10 for the 2,048 cycle refresh CBR REFRESH. The refresh is not hidden in the sense that
A0-A11 for the 4,096 cycle refresh. you can hide the time it takes to refresh, instead it is hidden
in the sense that data-out will stay on the lines while
HIDDEN REFRESH performing the function. READ and HIDDEN REFRESH
In HIDDEN REFRESH, the user does a READ or WRITE cycles will take the same amount of time: tRC. The two
cycle and then, leaving ?C?A/S low, brings ?R?A/S high (for cycles together take 2 x tRC. If we were to do a READ and
tRP tRAS
V IH
RAS V IL
tRPC
V IH
CAS V IL
DQ OPEN
tWRP tWRH
V IH
WE V IL
Figure 3
ONE CAS-BEFORE-??R?A/S REFRESH CYCLE
? ? /
V IH
RAS V IL
tRPC
tCPN tCSR
V IH
CAS V IL
DQ OPEN
V IH
WE V IL
DONT CARE
UNDEFINED
Figure 4
THREE ?C?A/S-BEFORE-??R?A/S REFRESH CYCLES
TN-04-30 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DT30.pm5 Rev. 2/95 3 1995, Micron Technology, Inc.
TN-04-30
TECHNOLOGY, INC. VARIOUS METHODS OF DRAM REFRESH
(READ) (REFRESH)
tRAS tRP tRAS tRP
V IH
RAS V IL
tCRP tRCD tRSH
V IH
CAS V IL
V IH
ADDR V IL ROW COLUMN
tAA
tRAC
tCAC
tOFF
tCLZ
V IH
WE V IL
V IOH
DQx V IOL OPEN VALID DATA OPEN
tOE tOD
V IH tORD
OE V IL
FIGURE 5
READ CYCLE FOLLOWED BY HIDDEN REFRESH
(READ) (REFRESH)
tRAS tRP tRAS tRP
V IH
RAS V IL
tCRP t RCD tRSH
tCSR tCHR
V IH
CAS V IL
V IH
ADDR V IL ROW COLUMN
tAA
tRAC
tCAC
tCLZ
V IH
WE V IL tOFF
V IOH
DQx V IOL OPEN OPEN
V IH tORD
OE V IL
DONT CARE
UNDEFINED
FIGURE 6
READ CYCLE FOLLOWED BY CBR REFRESH
TN-04-30 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DT30.pm5 Rev. 2/95 4 1995, Micron Technology, Inc.