EE141-Fall 2009

Digital Integrated
Circuits

Lecture 6
Inverter Delay Optimization

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Announcements
Lab#2 Mon., Tues., Lab #3 Fri.
Homework #3 due Thursday
Homework #4 due next Thursday

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 Class Material
Last lecture
Overview of Semiconductor Memory
Todays lecture
Inverter Delay Optimization
Reading (5.4, 5.5)

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Inverter Chain
In Out

CL

For some given CL:

How many stages are needed to minimize delay?
How to size the inverters?

Anyone want to guess the solution?

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 Careful about Optimization
Problems
Get fastest delay if build one very big
inverter
So big that delay is set only by self-loading

Likely not the problem youre interested in

Someone has to drive this inverter
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Engineering Optimization
Problems in General
Need to have a set of constraints

Constraints key to:

Making the result useful
Making the problem have a clean solution

For sizing problem:

Need to constrain size of first inverter

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 Delay Optimization Problem #1
You are given:
A fixed number of inverters
The size of the first inverter
The size of the load that needs to be driven

Your goal:
Minimize the delay of the inverter chain

Need model for inverter delay vs. size

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Inverter Delay
Minimum length devices, L = 0.09m
Assume that for WP = 2WN = 2W
2W
approximately equal resistances, RN = RP
approx. equal rise and fall delays, tpHL = tpLH

W
Analyze as an RC network:
L L
RP = Rsq , p RN = Rsq ,n = RW
WP WN

Delay: tpHL = (ln 2) RNCL = tpLH = (ln 2) RpCL

Loading on the previous stage: Cin = 3WC g

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 Inverter Delay
CP = 2WCg L
RW = Rsq ,n
2W W

Cint = 3WCd
W Cin = 3WC g
Cint CL

CN = WCg
Replace ln(2) with k (a constant):
Delay = kRWCint + kRWCL

Delay = kRsq,n(L/W)(3WCd) + kRsq,n(L/W)CL

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Inverter with Load

CP = 2WCg Delay

2W

W
Cint CL

Load
CN = WCg

Delay = kRW Cin(Cint/Cin+ CL /Cin)

= 3kLRsq,nCg[Cd/Cg + CL/(3WCg)]
= Delay (Internal) + Delay (Load)
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 Delay Formula
Delay ~ RW ( C int + C L )

t p = kRW C in ( C int C in + C L / C in ) = t inv ( + f )

Cint = Cin ( 1 for inverter)

f = CL/Cin electrical fanout
RW = Rsq(L /W) ; Cin =3WCg
tinv = 3ln(2)LRsqCg

tinv is independent of sizing of the gate!!!

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Apply to Inverter Chain

In Out

1 2 N CL

tp = tp1 + tp2 + + tpN

Cin , j +1
t pj = tinv +
Cin , j

N N Cin , j +1
t p = t p , j = tinv + , Cin , N +1 = CL
j =1

i =1 Cin , j
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 Optimal Tapering for Given N
Delay equation has N-1 unknowns, Cin,2 Cin,N

To minimize the delay, find N-1 partial derivatives:

Cin , j Cin , j +1
t p = ... + tinv + tinv + ...
Cin , j 1 Cin , j
dt p 1 Cin , j +1
= tinv tinv =0
dCin , j Cin , j 1 Cin2 , j

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Optimal Tapering for Given N (contd)

Result: every stage has equal fanout:
Cin , j Cin , j +1
=
Cin , j 1 Cin , j

In other words, size of each stage is geometric

mean of two neighbors:
Cin , j = Cin , j 1Cin , j +1

Equal fanout every stage will have same delay

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Optimum Delay and Number of Stages
When each stage has same fanout f :
f N = F = CL / Cin ,1

Effective fanout of each stage:

f =NF

Minimum path delay:

(
t p = Ntinv + N F )
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Example

In Out

1 f f2 CL= 8 C1
C1

CL/C1 has to be evenly distributed across N = 3 stages:

f =38 =2
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 Delay Optimization Problem #2
You are given:
The size of the first inverter
The size of the load that needs to be driven
Your goal:
Minimize delay by finding optimal number and
sizes of gates
So, need to find N that minimizes:

(
t p = Ntinv + N CL Cin )
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Solving the Optimization

Rewrite N in terms of fanout/stage f:

ln ( CL Cin )
f N = CL Cin N =
ln f

f +
(
t p = Ntinv ( CL Cin )
1/ N
)
+ = tinv ln ( CL Cin )
ln f
t p ln f 1 f
= tinv ln ( CL Cin ) =0
f ln 2 f

f = exp(1 + f ) For = 0, f = e, N = ln (CL/Cin)

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 Optimum Effective Fanout f
Optimum f for given process defined by
f = exp(1 + f )
5

4.5

4
fopt

3.5
fopt = 3.6
for = 1
3

e
2.5
0 0.5 1 1.5 2 2.5 3

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In Practice: Plot of Total Delay

[Hodges, p.281]

Curves very flat for f > 2

Simplest/most common choice: f = 4
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 Normalized Delay As a Function of F

( )
t p = Ntinv + N F , F = CL Cin

( = 1)
Textbook: page 210

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Buffer Design
N f tp

1 1 64 65
64

1 8 64
2 8 18

1 4 64
3 4 15
16

1 64 4 2.8 15.3
2.8 8 22.6
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 What About Energy (and Area)?

Ignoring diffusion capacitance:

Ctot = Cin + fCin + + fNCin
= Cin(1 + f + + fN)
= Cin + CinfN + Cinf(1 + f + + fN-2)

Overhead !!! f(fN-1-1) / (f-1)

Example (=0): CL = 20pF; Ci = 50fF N = 6
Fixed: 20pF
Overhead: 11.66pF !!!
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Example Overhead Numbers

Example: CL = 20pF; Cin = 50fF
25 40
Overhead Capacitance (pF)

20 35
Delay (t inv)

15 30

10 25

5 20

0 15
2 3 4 5 6 7 8 9 10
Number of Stages

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 Next Lecture
Gate Delay
Logical Effort

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