11/09/2016 TheCMOSInverterExplained

TheCMOSInverterExplained
BasilShelley bshelley@calpoly.edu EE307Dr.BraunF02


Overview
ComplementaryMOSFET(CMOS)technologyiswidelyusedtodaytoformcircuitsinnumerous
andvariedapplications.TodayscomputersCPUsandcellphonesmakeuseofCMOSdueto
severalkeyadvantages.CMOSofferslowpowerdissipation,relativelyhighspeed,highnoise
marginsinbothstates,andwilloperateoverawiderangeofsourceandinputvoltages(provided
thesourcevoltageisfixed).NextIwillattempttoexplainjusthowthislogicgateworksnow
thatyouhavesomeideaofhowimportantCMOSisinyourdaytodaylife.



CMOSInverterBasics
AsyoucanseefromFigure1,aCMOScircuitiscomposedoftwoMOSFETs.ThetopFET
(MP)isaPMOStypedevicewhilethebottomFET(MN)isanNMOStype.Thebodyeffectis
notpresentineitherdevicesincethebodyofeachdeviceisdirectlyconnectedtothedevices
source.Bothgatesareconnectedtotheinputline.Theoutputlineconnectstothedrainsofboth
FETs.

TakealookattheVTCinFigure2.Thecurverepresentstheoutputvoltagetakenfromnode
3.YoucaneasilyseethattheCMOScircuitfunctionsasaninverterbynotingthatwhenVINis
fivevolts,VOUTiszero,andviceversa.Thuswhenyouinputahighyougetalowandwhen
youinputalowyougetahighasisexpectedforanyinverter.Youmightbewonderingwhat
happensinthemiddle,transitionareaofthecurve.Youmightalsobecuriousastowhatmodes
ofoperationtheMOSFETsarein.Wewilllookattheseissuesnext.

Figure2:BasicVoltageTransferCharacteristic

Figure1:CMOS
Inverter



DCAnalysis
Figure3showsamoredetailedVTC.Beforewebeginouranalysisitisimportanttomentionthreeitems.

TheMOSFETSmustbeperfectlymatchedforoptimumoperation,thatis,theymusthave
thesamethresholdvoltagemagnitudeandconductionparameter.
Thedraincurrent(ID)throughtheNMOSdeviceequalsthedraincurrentthroughthe
PMOSdeviceatalltimes.MOSFETgateshaveahighinputimpedanceandweassume
thecircuitsoutputseesnosignificantloading.
VDDequalsthevoltageacrossthePMOSplusthevoltageacrosstheNMOSbyKVL.

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Figure3:VTCwithInputSignal

RegionI

FirstwefocusourattentiononregionI.Inthiscasewhenweapplyaninputvoltagebetween0
andVTN.ThePMOSdeviceonsincealowvoltageisbeingappliedtoit.TheNMOSis
alreadynegativeenoughandhasnouseformorefreeelectronssoitrefusestoconductand
turnsintoalargeresistor.SincetheNMOSdeviceisonvacation,thereisnocurrentflow
througheitherdevice.VDDisavailableattheVoterminalsincenocurrentisgoingthroughthe
PMOSdeviceandthusnovoltageisbeingdroppedacrossit.

ThePMOSdeviceisforwardbiased(VSG>VTP)andthereforeon.ThisMOSFETisin
thelinearregion(VSD<=VSG+VTP=VDDVo+VTP).
TheNMOSdeviceiscutoffsincetheinputvoltageisbelowVTN(Vi=VGS<VTN).
Thepowerdissipationiszero.

RegionII

HereweraisetheinputvoltageaboveVTN.WefindthatthePMOSdeviceremainsinthe
linearregionsinceitstillhasadequateforwardbias.TheNMOSturnsonandjumps
immediatelyintosaturationsinceitstillhasarelativelylargeVDSacrossit.

ThePMOSdeviceisinthelinearregion(VSD<=VSG+VTP).
TheNMOSdeviceisinthesaturationregion(Vi=VDS>=VGSVTN=VoVTN).
Currentnowflowsthroughbothdevices.Powerdissipationisnolongerzero.

Themaximumallowableinputvoltageatthelowlogicstate(VIL)occursinthisregion.VILis
thevalueofViatthepointwheretheslopeoftheVTCis1.Putanotherway,VILoccursat
(dVo/dVi)=1.

RegionIII

InthemiddleofthisregionthereexistsapointwhereVi=Vo.WelabelthispointVMand
identifyitasthegatethresholdvoltage.ThevoltagedroppedacrosstheNMOSdeviceequals
thevoltagedroppedacrossthePMOSdevicewhentheinputvoltageisVM.Foraveryshort
time,bothdevicesseeenoughforwardbiasvoltagetodrivethemtosaturation.

ThePMOSdeviceisinthesaturationregion(VSD>=VSG+VTP=VDDVo+VTP).
TheNMOSdeviceisinthesaturationregion(VDS>=VGSVTN=VoVTN).
Powerdissipationreachesapeakinthisregion,namelyatwhereVM=Vi=Vo.

RegionIV

RegionIVoccursbetweenaninputvoltageslightlyhigherthanVMbutlowerthanVDD
VTP.NowtheNMOSdeviceisconductinginthelinearregion,droppingalowvoltageacross
VDS.SinceVDSisrelativelylow,thePMOSdevicemustpickupthetabanddroptherestof
thevoltage(VDDVDS)acrossitsVSDjunction.This,inturn,drivesthePMOSinto
saturation.ThisregioniseffectivelythereverseofregionII.

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ThePMOSdeviceisinthesaturationregion(VSD>=VSG+VTP=VDDVo+VTP).
TheNMOSdeviceisforwardbiased(Vi=VGS>VTN)andthereforeon.ThisMOSFET
isinthelinearregion(Vi=VDS<=VGSVTN=VoVTN).

Theminimumallowableinputvoltageatthelogichighstate(VIH)occursinthisregion.VIH
occursatthepointwheretheslopeoftheVTCis1(dVo/dVi)=1.

RegionV

TheNMOSwantstoconductbutitsdraincurrentisseverelylimitedduetothePMOSdevice
onlylettingthroughatinyleakagecurrent.ThePMOSisouttolunchsinceitisseeinga
positivedrivebutitisalreadypositiveenoughandhasnouseformore.Thisdraincurrentlet
throughbythePMOSistoosmalltomatterinmostpracticalcasessoweletID=0.Withthis
informationwecanconcludethatVDS=Vo=0VfortheNMOSsincenocurrentisgoing
throughthedevice.Wehave,ineffect,sentinVDDandfoundtheinvertersoutputtobezero
volts.ForCMOSinverters,VOH=VDD.VOLisdefinedtobetheoutputvoltageofthe
inverterataninputvoltageofVOH.WehavejustproventhatVOL=0.

ThePMOSdeviceiscutoffwhentheinputisatVDD(VSG=0V).
TheNMOSdeviceisforwardbiased(Vi=VGS>VTN)andthereforeon.ThisMOSFET
isinthelinearregion(Vi=VDS<=VGSVTN).
ThetotalpowerdissipationiszerojustasinregionI.



AFewWordsAboutPowerDissipation
OurCMOSinverterdissipatesanegligibleamountofpowerduringsteadystate
operation.Powerdissipationonlyoccursduringswitchingandisverylow.Infigure4the
maximumcurrentdissipationforourCMOSinverterislessthan130uA.Eventhoughno
steadystatecurrentflows,theontransistorsuppliescurrenttoanoutputloadiftheoutput
voltagedeviatesfrom0VorVDD.ThismakesCMOStechnologyuseableinlowpowerand
highdensityapplications.

Figure4DrainCurrentVersesInputVoltage


PSPICECode
IfyouhavealotoffreetimeonyourhandstrypastingthiscodeintoPSPICE.Trychanging
someofthetransistorparameterssuchasW,L,andKP.

*CMOSINVERTER
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11/09/2016 TheCMOSInverterExplained
VDD105
VIN20
MQ11231PMOD1
MQ23200NMOD1
.DCVIN0.5..01

*NMOSMODELDEFINITION
.MODELNMOD1NMOS(L=3UW=6UKP=69UGAMMA=0.37
+LAMBDA=0.06RD=1RS=1VTO=1.0TOX=0.04U
+CBD=2FCBS=2FCJ=200UCGBO=200PCGSO=40PCGDO=40P)

*PMOSMODELDEFINITION
.MODELPMOD1PMOS(L=3UW=6UKP=34.5UGAMMA=0.37
+LAMBDA=0.06RD=1RS=1VTO=1.0TOX=0.04U
+CBD=2FCBS=2FCJ=200UCGBO=200PCGSO=40PCGDO=40P)

.PRINTDCV(1)V(2)V(3)
.PROBE
.END

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