MOS Transistors as Switches

nMOS transistor:
G Closed (conducting) when
(gate) Gate = 1 (VDD)
Open (non-conducting) when
D S Gate = 0 (ground, 0V)
(drain) (source)

pMOS transistor:
Closed (conducting) when
G Gate = 0 (ground, 0V)

Open (non-conducting) when

S D Gate = 1 (VDD)

For nMOS switch, source is typically tied to ground and is used to pull-down signals:

Out
when Gate = 1, Out = 0, (OV)
G
when Gate = 0, Out = Z (high impedance)
S

For pMOS switch, source is typically tied to VDD, used to pull signals up:

S
when Gate = 0, Out = 1 (VDD)
G
when Gate = 1, Out = Z (high impedance)

Out

Note: The MOS transistor is a symmetric device. This means that the drain and source terminals
are interchangeable. For a conducting nMOS transistor, VDS > 0V; for the pMOS transistor, VDS
< 0V (or VSD > 0V).
The CMOS Inverter

Truth Table
I Out
VDD
0 1
1 0

I Out I Out

Rin
GND

Note: Ideally there is no static power dissipation. When "I" is fully is high or fully low, no

current path between VDD and GND exists (the output is usually tied to the gate of another MOS

transistor which has a very high input impedance).

Power is dissipated as "I" transistions from 01 and 10 and a momentory current path exists
between Vdd and GND. Power is also dissipated in the charging and discharging of gate

capacitances.
Parallel Connection of Switches
Y
Y = 0, if A or B = 1
A B

A+B

Y = 1 if A or B = 0
A B

A+B

Series Connection of Switches

A Y = 0, if A and B = 1

B A B

A
Y = 1, if A and B = 0

B A B

Y
NAND Gate Design
p-type transistor tree will provide "1" values of logic function
n-type transistor tree will provide "0" values of logic function

Truth Table (NAND):

A
B 0 1
AB
0 1 1
00 1

01 1 1 1 0

10 1

11 0

K-map (NAND):
NAND circuit example:

Vdd

Ptree = A + B
Ntree = A B

A
B Y
B

A
NOR Gate Design
p-type transistor tree will provide "1" values of logic function
n-type transistor tree will provide "0" values of logic function

Truth Table:
A
B 0 1
AB
0 1 0
00 1

01 0 1 0 0

10 0

11 0

K-map:
NOR circuit example:

Vdd

A
Ptree = A B
Ntree = A + B
B

Y
A
Y
B
What logic gate is this?

Vdd

A
Y = 1 when A B
Y = 0 when A + B
B

Answer: AND function, but poor design!

Why? nMOS switches cannot pass a logic "1" without a threshold voltage (VT) drop.

where VT = 0.7V to 1.0V (i.e.,

VDD
G threshold voltage will vary)

output voltage = 4.3V to 4.0V,

VDD VDD - VT
D S a weak "1"
The nMOS transistor will stop conducting if VGS < VT. Let VT = 0.7V,

G 5V

S D D ?
0V 5V 0V ?

As source goes from 0V 5V, VGS goes from 5V 0V.

When VS > 4.3V, then VGS < VT, so switch stops conducting.
VD left at 5V VT = 5V 0.7V = 4.3V or VDD VT.

What about nMOS in series?

5V 5V 5V 5V

0V 5V 0V 4.3V 0V 4.3V 0V 4.3V 0V (VDDVT)

5V - 0.7V
4.3V

Only one threshold voltage drop across series of nMOS transistors

For pMOS transistor, VT is negative.
pMOS transistor will conduct if |VGS| > |VTp| (VSG > |VTp|),

or VGS < VTp

0V
G VTp = 0.7V
VGS = 0V 5V = 5V
5V
S D

conducting VGS < VTp or |VGS| > |VTp|

5V < 0.7V 5V > 0.7V

How will pMOS pass a "0"?

When |VGS| < |VTp|, stop conducting

G 0V

5V 0V 5V ?
So when |VGS| < |0.7V|, VD will go from 5V
S D D ?
0.7V,

a weak "0"

How are both a strong "1" and a strong "0" passed?

Transmission gate pass transistor configuration

When I = 1,

A B B = strong 1, if A = 1;

B = strong 0, if A = 0

I When I = 0, non-conducting
About that AND Gate...
Vdd

A No!!!
Poorly designed AND
(circuit designer fired)

Instead use this,

A
Y
B
Vdd

A
More Complex Gates

F = AB + CD Ntree will provide 0's, Ptree will provide 1's

0's of function F is F, F = AB + CD = AB + CD

nMOS transistors need high true inputs, so it is desirable for all input variables to be high true,

just as above.

A C

AB + CD
B D

Likewise, a Ptree will provide 1's.

F = AB + CD, need a form involving A, B, C, D

Apply DeMorgan's Theorem:

A B
F = AB CD = ( A + B) (C + D)

Implementation

C D

Y
Can also use K-maps:
AB

1 1 0 1

F = AB + CD
1 1 0 1
CD
0 0 0 0

1 1 0 1

For Ntree, minimize 0's; for Ptree, minimize 1's

AB

0
CD Ntree = AB + CD
0 0 0 0

AB

1 1 1

1 1 1
Ptree = AC + AD + BC + BD
CD
= A (C + D) + B (C + D)
= (A + B) (C + D)
1 1 1
Introduction to Static Load Inverters

1)
resistor load
R
When I = 1, inverter dissipates static power.
O

I Switching point of inverter depends on ratio of

R to RON (on resistance of nMOS device.

VOH = 5V,
VOL close to 0V, depends on ratio R/RON

Note: output can swing from almost 0V to 5V (VDD)

2) Again, static power dissipation occurs when

I = 1.
D

S
O

Load is enhancement-mode nMOS device.

Note: output swings from nearly 0V to (VDD VTn)

Using a transistor as a load tends to require much less silicon area than a resistor.

VOH = VDD VTn,

VOL can be close to 0V, depending on ratio of RON of two enhancement devices
Depletion-mode nMOS

nMOS device with VTn < 0V (negative threshold voltage). Device is always conducting if VGS >
0V.

3)

D
VGS = 0V always
S
O
Load device is always on, looks like a load
I resistor.

Dissipates static power when I = 1

VOH = 5V; VOL nearly 0V, depending on ratio of RON,dep to RON,enh.

Depletion-mode devices were used before it was economical to put both p-type and n-type
devices on the same die.

4) pMOS device as static load

S Here also the load device is always on

(conducting).

D
O
Dissipates static power when I = 1.
I

VOH = 5V; VOL nearly 0V, depending on ratio of RON,p to RON,n

Basic MOS Device Equations
Drain

Gate Bulk (or substrate for nMOS device in n-well technology)

Source

The nMOS device is a four terminal device: Gate, Drain, Source, Bulk.

Bulk (substrate) terminal is normally ignored at schematic level, usually tied to ground for the
nMOS case. In analog applications, however, the bulk terminal may not be ignored.

Gate controls channel formation for conduction between Drain and Source. Drain at higher
potential than Source Source usually tied to GND to act as pull-down (nMOS).

Three regions of operations first-order (ideal) equations:

Cutoff region

ID = 0A VGS VTn (nMOS threshold voltage)

Linear region

V
2

ID = (VGS VTn )VDS DS 0 < VDS < VGS VTn

2

(
Note: ID is linear with respect to (VGS VTn) only when VDS
2
)
2 is small.

Saturation region

ID = (VGS VTn )2 0 < VGS VTn < VDS
2
Device parameters:

= transistor gain factor, dependent on process parameters and

device geometry (Kn)

process dependent, constant

W
=
tox L

under control of the designer

As W/L increases, effective RON of device decreases

= surface mobility of the carriers in the channel

= permittivity of the gate insulator

tox = thickness of the gate insulator

See Figure 2.5, 2.8 concerning , , and tox

SPICE represents by a factor given by

K' = Cox = t = KP
ox

So,
K' W
ID = (VGS VTn )2 ; saturation region
2 L
VI characteristic

ID

VDS
VGS

boundary between
linear & saturation
regions (dashed line) |VGS - V T| = |V DS |

V GS5

LINEAR

GS
V
V GS4
ID

SATURATION
V GS3

V GS2

V GS1

CUTOFF
V DS

Things to note:
In the "linear" region, ID becomes less and less linear with VGS as VDS becomes large.
(
This is because the VDS
2
)
2 term in the linear region grows large.

Higher VGS values increase channel conductance allowing for higher values of ID for a
given VDS.
*MOSFET Characteristics
Vds 1 0 DC 10
Vgs 2 0 DC -.723
Vdummy 3 0 DC 0
M1 1 2 3 3 Mfet
.MODEL Mfet NMOS(KP=3686U VTO=2.30 LAMBDA=0.137)
.DC Vds 0 10 .2 Vgs 2.5 5 .5
.probe
.end
What do W and L physically look like?

nMOSFET layout:

Gate (polysilicon)
Source Drain
n+ diffusion n+ diffusion

In digital logic, typically will draw all transistors with the minimum gate length and vary the
width.

Larger W larger transconductance (more current flow for given gate voltage), higher gate
capacitance

During fabrication process, the actual width and length of the channel can be reduced by
diffusion from the bulk, source, and drain into the device channel.

SPICE has some MOSFET model parameters to account for this effect, LD and WD, where the
actual the actual length and width is calculated as

Leffective = Ldrawn - 2 LD

Weffective = Wdrawn - 2 WD

If LD, WD parameters not specified in the model, then SPICE assumes they are 0.
Ideal Inverter
Vout

VDD
switching
point

Vin
VDD
2

Actual Inverter Characteristics, some definitions

Vout (V)
VOH

VOL Vin (V)

VIL VIH
Vth

VIL represents the maximum logic 0 (LOW) input voltage that will guarantee a logic 1
(HIGH) at the output

VIH represents the minimum logic 1 (HIGH) input voltage that will guarantee a logic 0
(LOW) at the output
Noise Margin

Illustration of Noise Margin:

Vin Vout

VDD VDD
Output logic 1
VOH
Input logic 1
NMH
VIH

VIL

Input logic 0 NML

VOL
Output logic 0
0V 0V

Calculate noise margin using

NML = VIL - VOL NMH = VOH - VIH

How do we determine VIL, VOL, VOH, and VIH?

We must exam the inverter's transfer characteristic.

CMOS Inverter Regions of Operation

A B D E
5 1.5 10 -4
Vout

4 1.2 10 -4

3 9 10 -5
V out (V)

I DD (A)
C

2 6 10 -5
IDD

1 3 10 -5

0 0 10 0
0 1 2 3 4 5
V in (V)

Region A:
0 Vin < VTn pMOS nonsaturated; nMOS cutoff

nMOS is cutoff because Vin < VTn

Why is the pMOS device in the linear region?

Linear region VSDp < VSGp - |VTp|

(5 5)V < (5 0)V |0.7|V

[for VDD = 5V and VTp = 0.7V]
0V < 4.3V

Note that the pMOS device can be in linear region even if IDp 0A!
Region B:

VTn Vin < Vth pMOS nonsaturated, nMOS saturated

Why is nMOS saturated? Is VDSn > VGSn - VTn?

Because (VDSn = Vout) > Vth and (VGSn = Vin) < Vth ,

then VDSn > VGSn - VTn

Vout > Vin - VTn [B-1]

Why is pMOS in linear region?

It started out in linear and will remain in linear as long as

VSDp < VSGp - |VTp|
(VDD - Vout) < (VDD - Vin) - |VTp|
Vin < Vout - |VTp| [B-2]

Vout in the above expression (Eqn. [B-2]) is decreasing towards Vth and Vin is increasing
towards Vth. When Eqn. [B-2] no longer holds, then the pMOS device will become
saturated.

For the pMOS device, then

regions A B C correspond to
linear linear saturated, respectively.
How can you predict the output voltage for region B?

n
The nMOS is saturated, so IDn = (Vin VTn ) 2 = n (VGSn VTn ) 2
2 2

The pMOS is linear, so

p
IDp = (2(V
SGp
| VTp |)VSDp (VSDp ) 2 )
2
p
IDp = (2(V
DD
Vin | VTp |)(VDD Vout ) (VDD Vout ) 2 )
2

Can solve for Vout since

IDn = IDp

VDD
S

IDp

IDn
S

GND

Equivalent circuit for region B Vout

IDn
Region C:

Vin = Vth pMOS saturated, nMOS saturated

In order for nMOS to be saturated, need

VDSn > VGSn VTn
Vout > Vin VTn

In order for pMOS to be saturated, need

VSDp > VSGp |VTp|
VDD Vout > VDD Vin |VTp|
Vout < Vin + |VTp|

So Vout in region C,

Vin VTn < Vout < Vin + |VTp|

The CMOS inverter has very high gain in region C so small changes in Vin produce large
changes in Vout. No closed form equation for Vout. Somewhere in this region, Vout = Vin,
which is the switching point for this gate.

Equivalent circuit for region C:

VDD

IDp

Vout

IDn
What is Vin in region C?

In region C, both devices in saturation so

p
IDp = (VDD Vin | VTp |) 2
2

n
IDn = (Vin VTn ) 2
2

So, using IDn = IDp, Vin can be solved for (more on this later....)

Region D:

Vth < Vin VDD |VTp| pMOS saturated, nMOS linear

p
Hence, IDp = (VDD Vin | VTp |) 2
2

IDn =
n
2
(
2(Vin VTn )Vout Vout
2
)
Again, since IDp = IDn, we can solve for Vout:

p
Vout2 2(Vin VTn)Vout + (VDD Vin | VTp |) 2 = 0
n

b b 2 4ac
using x=
2a

and, recognizing from above,

p
a = 1, b = 2(Vin VTn), c = (VDD Vin | VTp |) 2
n

we get
 p
Vout = (Vin VTn) (Vin VTn ) 2 (Vin VDD | VTp |) 2 .
n

IDp

Equivalent circuit for region D Vout

Region E:

Vin > VDD |VTp| pMOS is cutoff, nMOS is linear mode

Since VSGp = VDD Vin (< |VTp|),

Vout 0V

due to nMOS acting as pull-down while pMOS in cutoff.

CMOS Inverter Transfer Characteristic
A B D E
5 1.5 10 -4
Vout

4 1.2 10 -4

3 9 10 -5
V out (V)

I DD (A)
C

2 6 10 -5
IDD

1 3 10 -5

0 0 10 0
0 1 2 3 4 5
V in (V)
Analysis:

VOH: Vin < VTn, the nMOS transistor is in cutoff while the pMOS transistor is turned-on
(inversion layer established). The result is

VOH VDD.

VOL: (VDD Vin) < |VTp|, the pMOS is in cutoff while the nMOS is on and providing a
conduction channel to ground. Hence,

VOL 0V.

VIL: Input low voltage, here the nMOS transistor is saturated and the pMOS is nonsaturated.
Equating the currents provides

n
(VIL VTn ) 2 = p (2(VDD VIL | VTp |)(VDD Vout ) (VDD Vout ) 2 ) .
2 2
VIL: (continued) Since two unknowns exist, Vin = VIL and Vout, a second equation is needed.
Use the unity-gain condition to obtain this second equation,

dVout (I Dn /Vin ) (I Dp /Vin )

= = 1,
dVin (I Dp /Vout )

provides

n n
VIL 1 + = 2Vout + VTn VDD |VTp|.
p
p

Now the two equations needed to solve for VIL and Vout exist.

VIH: Input high voltage, here the nMOS is nonsaturated and the pMOS is saturated.
Equating the drain currents yields

n
2
( 2
2(VIH VTn )Vout Vout =
p
2
)
(VDD VIH | VTp |) 2 ,

the first of two equations needed to solve two unknowns, Vin = VIH and Vout. Use the
unity-gain condition to get the second,

dVout (I Dp /Vin ) (I Dn /Vin )

= = 1.
dVin (I Dn /Vout )

This provides

p
VIH 1 + = 2Vout + VTn + p (VDD | VTp |) ,
n n

the second equation needed to solve for the two unknowns.

Vth: At the CMOS inverter's switching point, or inverter threshold, Vth = Vin = Vout and both
the pMOS and nMOS transistors are saturated. Again, equating the drain currents,

n
(Vth VTn ) 2 = p (VDD Vth | VTp |) 2
2 2
is obtained which can be easily solved to provide Vth,

p
VTn + (VDD | VTp |)
n
Vth =
p
1 +
n

VDD n
Note: switching point of gate (Vth) is -if- = 1 and VTn = VTp.
2 p

So, switching point of inverter is function of the ratio of the nMOS/pMOS gains and the
threshold voltages of the nMOS, pMOS transistors.
n/p Ratio
The n (gain of nMOS) / p (gain of pMOS) ratio determines the switching point of the CMOS
inverter.

Vout (V) Equal pull-up/pull-down

"strength"
5
Strong
pull-up
4

3
n = 10 n = 1 n = 0.1
p p p
2

0 Vin (V)
0 1 2 3 4 5
VDD
Strong 2
pull-down

Switching point = VDD/2

if n/p = 1 and VTn = |VTp|
Recall that
W
=t L .
ox

If we assume that the nMOS and pMOS transistors have equal W/L ratios, then
n Wn
n tox Ln n electron mobility
= = p = hole mobility .
p p Wp
tox Lp

In silicon, the ratio n/p is usually between 2 to 3.

This means, that if Ln = Lp,

then Wp must be 2 to 3 times Wn

in order for n = p .

Wp Wn
Vout if = because n > 1
Lp Ln p
5

0 Vin
0 1 2 3 4 5
VDD
2
Calculate the switching point of a static load inverter as function of n/p:

In region C, already know nMOS device is saturated from previous analysis.

VDD

Vout

Vin

For pMOS to be saturated need:

VSDp > VSGp |VTp|

VDD Vout > VDD 0V |VTp|
Vout < |VTp|
Not true!!!
VDD VDD
(If Vout in region C is about and >
2 2
|VTp|
(typically this is true))

pMOS must be in linear region


Then I Dn = n (VGSn VTn ) 2 = n (Vin VTn ) 2
2 2

and I Dp =
p
2
(2(V
SGp | VTp |)VSDp VSDp
2
)
I Dp =
p
2
(2(VDD | VTp |)(VDD Vout ) (VDD Vout ) 2 )

Equate IDn = IDp and solve for Vout.

Vout = | VTp | + (VDD | VTp |) 2 n (Vin VTn ) 2
p

Can also solve for n/p,

2 2
n (VDD | VTp |) (Vout | VTp |)
=
p (Vin VTn ) 2
Consider again

2 2
n (VDD | VTp |) (Vout | VTp |)
=
p (Vin VTn ) 2

for the pseudo-nMOS inverter.

VDD
Let |VTp| = VTn = 0.2VDD and Vin = Vout = . Then, for VDD = 5V,
2

n
6.1 !!!
p

Note that this is very different result from the CMOS inverter case!

If VDD = 3.3V, but the value of VTn = |VTp| is unchanged (i.e., 1V in the above example),
then
n
11.5
p
VDD
for a switching point equal to .
2

The n/p ratio depends on the absolute value of VDD! This means that the operation of
the pseudo-nMOS inverter will NOT scale with VDD (for a given CMOS technology).

For the CMOS inverter, the n/p ratio for a switching point of VDD/2 is independent of
VDD so its operation will scale with supply voltage. This is a another big advantage of
CMOS technology.

Not unusual for static CMOS circuits to operate over a very large range of power supply
voltages, i.e., 2.0V to 6.0V is common.