library IEEE;

use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity practica3 is
port
(
-- Input ports
a,b : in std_logic_vector (3 downto 0);
-- Output ports
c : out std_logic_vector (4 downto 0)
);
end practica3;
architecture practica3 of practica3 is
signal z,z1: std_logic_vector (4 downto 0);
begin
z <= '0' & a;
z1 <='0' & b;
c <= z+z1;
end practica3;