ITU - Digital Circuits Course Slide No. 09

Lecture Notes are licensed to Feza BUZLUCA under license
Digital Circuits
http://creativecommons.org/licenses/by-nc-nd/3.0/
INTERNAL STRUCTURES OF ELECTRONIC DIGITAL CIRCUTS
Until now we have seen abstract logic gates such as AND, OR, NAND, NOT , so
on.
There are many different ways to implement a logic gate as an electronic
circuit.
In this course we will discuss how different types of transistors are used to
design an electronic logic circuit.
In digital circuits transistors act as a current-controlled switch (ON or OFF).
First we introduce the bipolar junction transistor.
Then we will introduce the MOSFET (metal-oxide semiconductor field effect
transistor) or simply MOS transistor, which is used almost by all new
integrated circuits.
http://www.faculty.itu.edu.tr/buzluca
http://www.buzluca.info 2011 Dr. Feza BUZLUCA 9.1
Digital Circuits
Bipolar Junction Transistor:

Base is the control terminal.
If no current is flowing into the base then no current can flow from the collector
to the emitter (OFF).
However, if current is flowing from the base to the emitter, then current is also
enabled to flow from the collector to the emitter (ON).
npn Bipolar Transistor Transistor is cut off (OFF) Transistor is saturated (ON)
VBE < 0.6V VBE 0.6V
C Collector
C C
Base
Ic Ic>0
Ic=0
B
B B RCE(sa t )
Ib + Ib=0 + Ib>0
VCE(SAT)
=0.2V
Ie =Ib +Ic VBE<0.6V Ie=0 VBE =0.6V

Ie =Ib +Ic
E E
E
Emitter
Digital Circuits
Implementation of a NOT gate using a bipolar npn transistor and resistors

VCC = 5V VOUT
IN OUT
5.0V VCC
R2 3.6V
VOUT
R1
V Q1
IN 0.2V VCE(sat)
VIN
Switch model of the circuit: LOW HIGH
VCC =+5 V VCC = +5 V 0.8V 2.0V
a) b)
IO
Rc R
VOUT VOUT
VIN VIN
VOUT =VCC - RC*IO VOUT=LOW
VIN=HIGH R IO
VIN=LOW VOUT=HIGH CEsat
Switch ON
Switch OFF <50
VCEsat
0.2V
Digital Circuits
TTL (Transistor- Transistor) Logic Family

Bipolar transistors and resistors are used.
Although TTL was largely replaced by CMOS (we will discuss later), you may
encounter TTL components in your labs; therefore, basic TTL concept are covered
in this course.
VCC=+5 V
Example:
Two-input NAND gate R1 R2 R4
A Q3
Q2
Inputs
Q1
B Z Output
Q4
R3
Digital Circuits
Operation of the Output Stage of a TTL Gate

Output is "0" (LOW): Q4 is ON, Q3 is OFF.
VCC=+5 V
In this case the current IOL flows from the output into
the circuit (sinking current).
R
VOL = VCE(Q4) + IOL* RQ4
IOH Output is "1" (HIGH): Q3 is ON, Q4 is OFF.
(sourcing)
Q3 In this case the current IOH flows from the output to
the outside of the circuit (sourcing current).
VO (Output) VOH = VCC (VCE(Q3) + IOH* (R+RQ3))
Q4
If both Q3 and Q4 are OFF output is in high-impedance
(Hi-Z) state.
IOL It is also called third state (High, Low, Hi-Z).
(sinking)
In this state the output behaves as it isn't even
connected to the circuit.
The output is isolated from the line it was connected.
For TTL components VOL(MAX) = 0.4V VOH(MIN) = 2.4V
In the TTL family there different types of elements (such as LS,ALS,L, F). They
have different current and voltage values which can be found in data catalogs.
Digital Circuits
TTL Logic Levels

Abstract logic elements process binary digits, 0 and 1.
However, real logic circuits process electrical signals such as voltage levels.
In any logic circuit family, there is a range of voltages that is interpreted as
logic 0 and another, nonoverlapping range that is interpreted as logic 1.
TTL circuits are connected to 5-volt power supply (Vcc=5V).
Logic levels of a standard TTL unit:
5.0V VCC
VOHmin: The minimum output voltage produced in

the HIGH state.
HIGH
VIHmin: The minimum input voltage guaranteed to be
recognized as a HIGH.
2.4V VOHmin
VILmax: The maximum input voltage guaranteed to
2.0V VIHmin be recognized as a LOW.
ABNORMAL
VOLmax: The maximum output voltage produced in
0.8V VILmax the LOW state.
0.4V LOW VOLmax
0.0V GND
Digital Circuits
TTL Fanout
Remember, the output of a logic gate is connected to inputs of other gates.
The fanout of a logic gate is the number of inputs that the gate can drive
without exceeding its worst-case loading specifications.
Because of current issues this number is limited.
When Output is LOW:
VCC=+5 V VCC=+5 V VCC=+5 V VCC=+5 V
From the inputs(LOW) of
the components flows the
R R1 R1 R1 current IIL into the
output of the gate.
IIL IIL IIL The sum of these
currents is sunken by the
Q3
gate.
VOL IOL < IIL
Q4 With the increase in IOL according to the equation

VOL = VCE(Q4) + IOL* RQ4 , the value VOL also increases and
IOL it can exceed the limit value that can be accepted as 0.
The condition must be satisfied: VOL < VILmax
Digital Circuits
When Output is HIGH:

Into the inputs in
VCC=+5 V VCC=+5 V VCC=+5 V VCC=+5 V HIGH state flows the
leakage current IIH.
R R1 R1 R1 The sum of these
currents is sourced by
IOH the output of the gate.
IIH IIH IIH
IOH < IIH
Q3
VOH
Q4
With the increase in IOH according to the equation
VOH = VCC (VCE(Q3) + IOH* (R+RQ3))
VOH decreases and it can go down the limit value that can be
accepted as logic 1.
The condition must be satisfied: VOH > VIHmin
The fanout of a unit is the minimum of the numbers calculated for LOW and
HIGH states.
Digital Circuits
CMOS (Complementary MOS) Logic Family

MOS FET (Metal-Oxide Semiconductor Field-Effect Transistor) is used.
A MOS transistor can be modeled as a 3-terminal device that acts like voltage
controlled resistance.
Drain (D)
According to the voltage from Gate to Source (VGS) the
resistance from Drain to Source (RDS) changes.
Gate If transistor is OFF RDS 1M (106)
(G) If transistor is ON RDS 10
Source
(S) There are two types of MOS transistors.
a) n channel MOS: NMOS. b) p channel MOS: PMOS.
V
GS
dra in
gate + source
gate
+ sou rce dra in
V
GS
-
Increase VGS decrease RDS Decrease VGS decrease RDS
Normally: VGS 0V Normally: VGS 0V
Digital Circuits
CMOS NOT Gate
VDD = +5.0 V IN OUT
Q2
(p-channel )
V IN Q1 Q2 VOUT
VOUT
Q1 0.0 (L) off on 5.0 (H)
V IN (n-channel ) 5.0 (H) on off 0.0 (L)
Digital Circuits
CMOS NOT Gate Switch Model

VD D = +5.0 V
Q2 If V IN Low: ON
(p-cha nne l)
If V IN High: OFF
VOUT
Q1 1 = 0 State:
0 = 1 State: VIN (n-cha nne l)
VIN High: ON
VDD = +5.0 V V IN Low: OFF VDD = +5.0 V
IOH
V IN = L VOUT = H V IN = H VOUT = L
IOL
Digital Circuits
CMOS NAND Gate
VDD A
Z
B
Q2 Q4
A B Q1 Q2 Q3 Q4 Z
Z
L L off on off on H
A Q1 L H off on on off H
H L on off off on H
H H on off on off L
B Q3
Digital Circuits
CMOS NAND Gate Switch Model
VDD VDD VDD
Z =H Z =H Z =L
A =L A=H A=H
B =L B =L B =H
0 TVE 0 = 1 0 TVE 1 = 1 1 TVE 1 = 0
Digital Circuits
CMOS NOR Gate

VDD
A
Z
B
A Q2
B Q4 A B Q1 Q2 Q3 Q4 Z
Z L L off on off on H
L H off on on off L
H L on off off on L
Q1 Q3 H H on off on off L
Digital Circuits
CMOS Three-state Buffer

Remember, if an output is in high-impedance (Hi-Z) state (also called third state)
the output behaves as it isn't even connected to the circuit.
VD D = +5.0 V
EN
EN A OUT
Q2
OUT IF EN=HIGH THEN OUT=A

A IF EN=LOW THEN OUT= Hi-Z
Q1
EN A Q1 Q2 OUT
L L off off Hi-Z
To simplify the diagram, the internal NAND, L H off off Hi-Z
NOR and NOT functions are shown as H L on on L
functional abstract gates rather than in H H off on H
transistor form.
They actually consist of 10 transistors.
Digital Circuits
Three-state Common Bus

Several three-state outputs can be wired together to form a three-state common
bus.
Only one, unit which is enabled can drive the bus.
Example:
Common bus
X EN 1 EN
2
If X=0 buffer #2 drives the bus. B is on bus.
If X=1 buffer #1 drives the bus. A is on bus.
A B
Example: Common bus
EN 1 EN EN EN Y X Bus
0 2 3 4
X S0 1 0 0 A
2 0 1 B
Y S1 1 0 C
3
2:4 1 1 D
Decoder
A B C D
Digital Circuits
CMOS Logic Levels

CMOS circuits can use power supplies withe voltage less than 5 Volts.
Logic levels change according to the voltage of the power supply.
VCC
VOH 5-V CMOS families: 5.0V VCC
HIGH 4.44V VOH
0.7VCC VIH 3.5V VIH
ABNORMAL
0.3VCC VIL 1.5V VIL
LOW VOL
VOL 0.5V
GND 0.0V GND
2.5-V 2.5V VCC 1.5-V

CMOS families: 2.0V VOH CMOS families:
1.7V VIH 1.5V VCC
1.15V VOH
0.975V VIH
0.7V VIL 0.525V VIL

VOL 0.35V VOL
0.4V
0.0V GND 0.0V GND

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Lecture Notes are licensed to Feza BUZLUCA under license

INTERNAL STRUCTURES OF ELECTRONIC DIGITAL CIRCUTS

Bipolar Junction Transistor:

Implementation of a NOT gate using a bipolar npn transistor and resistors

TTL (Transistor- Transistor) Logic Family

Operation of the Output Stage of a TTL Gate

TTL Logic Levels

VOHmin: The minimum output voltage produced in

Q4 With the increase in IOL according to the equation

When Output is HIGH:

CMOS (Complementary MOS) Logic Family

CMOS NOT Gate

VDD = +5.0 V IN OUT

CMOS NOT Gate Switch Model

CMOS NAND Gate

CMOS NAND Gate Switch Model

VDD VDD VDD

0 TVE 0 = 1 0 TVE 1 = 1 1 TVE 1 = 0

CMOS NOR Gate

CMOS Three-state Buffer

OUT IF EN=HIGH THEN OUT=A

Three-state Common Bus

Example: Common bus

CMOS Logic Levels

0.7VCC VIH 3.5V VIH

2.5-V 2.5V VCC 1.5-V

0.7V VIL 0.525V VIL

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