ITU - Digital Circuits Course Slide No. 06

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Timing Diagrams
They describe the temporal behavior (input/output relation) of digital circuits.
Time is drawn on the horizontal axis (x-axis), output of the digital circuit (0/1 or
L/H) is drawn on the vertical axis.
In more detailed timing diagrams, values of the output are written in terms of
electrical voltage or current.
Some of the physical phenomena cannot be shown on the truth table. In these
cases timing diagrams should be used describe the behavior of the circuit.
Example:
A
B 0 0
A
F 0 0
C B
0 1
In this diagram only logical
C
behavior of the circuit is shown and 0 0
AB
time delays (described in the next
slides) are ignored. 0 1
F
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Translated by Dr. Mustafa KAMAAK 2011 Dr. Feza BUZLUCA 6.1
Digital Circuits
Propagation Delay
Because of the electronic structure of the logic gates, there is time difference
between the input (of the logic gate) and the response of the gate (to this input).
The time required for the input signal to propagate inside the logic gate until its
effect can be seen at the output is called propagation delay.
Propagation delay determines the speed of the logic circuit.
Example: Input Output
tPHL: transition from H to L

tPLH: transition from L to H
input
output
tPHL
tPLH
Digital Circuits
Hazards caused by propagation delays

If an input propagates through multiple paths to the output, unexpected output
values (hazards) may happen at the output.
For example, input B has two different paths (shown with red and yellow lines) to
the output Z.
A When the inputs A, B, and C are
B all zero (A=0, B=0,C=0), the
1 output will also be zero (Z=0).
Z
B' 2 While in this state, if the value
C Z= (A+B)(B'+C) of input B is changed to 1, the
output should not change its
value (Z=0).
0 0
A
However due to the different
0 0
C propagation delay in the paths
of input B, a short change
B 0 Delay in the (hazard) appears at the output.
1
inverter
B' 1 gate
Z 0 Static 0 hazard
Digital Circuits
There are three types of hazards:

a) Static 0: The output becomes 1 for a short time and get back to 0.
Static 0 hazard happens when a function is implemented with product
of sums.
b) Static 1: The output becomes 0 (from 1) and gets back to 1 after a
short time.
Static 1 hazard happens when a function is implemented with sum of
products.
c) Dynamic: The output oscillates when it changes its value.
Static 0 Static 1 Dynamic
Digital Circuits
Avoiding hazards: Circuit at the left (implemented as

SoP) has output Z=1 when A=1, B=1
A
and C=1.
B
While in this state if B becomes 0
Z (10), the output should stay as Z=1.
B' However, static 1 hazard occurs at
C the output.
The potential for a hazard can be foreseen from the Karnaugh diagram.
Z BC B Change in B (10) causes a transition from a prime implicant
00 01 11 10
A to another. These type of transitions cause hazards because
0 1 of delays.
To avoid all possible hazards, consensus of the transitions
A 1 1 1 1 are added to the design which increase the cost.
C Z BC B
Z= AB + B'C A 00 01 11 10
0 1 Z= AB + B'C + AC
A 1 1 1 1
C
Digital Circuits
SEQUENTIAL CIRCUITS
In the first part of the course, combinational circuits are covered.
The output of the combinational circuits depends only to the input.
In sequential circuits, the output depends both on the input and the state of
the circuit.
Memory units are required to remember (store) the state of the circuit.
For example, vending machines keep track of (remember) the coins that were
thrown into the machine. With each coin, the state of the machine (total amount
of thrown coins) is updated.
There two types of sequential circuits:
Synchronous sequential circuits: Their state can change at a discrete instance
of time.
All memory elements are synchronized by a common clock signal. Therefore
these circuits are also called "clocked synchronous sequential" circuit.
Asynchronous sequential circuit: Their state can change at any instant of time
depending upon the input signals.
In this course we will deal only with clocked synchronous sequential circuits,
because nearly all sequential logic today is clocked synchronous.
For example microprocessors are clocked synchronous sequential circuits.
Digital Circuits
Finite State Machine (FSM) Model

Sequential circuits are designed using finite state machine FSM model.
This model is also used in the design of many other systems.
When the machine is started, it is in a certain state (initial state: s0).
An output is produced depending on the inputs and the current state.
Transition into a new state happens depending on the input and the current state.
A FSM has two parts:
a) Combinational circuit for logical operations
b) Memory unit to remember the current state.
Block diagram of a clocked synchronous sequential circuit:
Inputs (I0-In-1) Outputs (O0-Om-1)
Combinational
circuit
Current state
(s0-sk-1) Next state
(s0+- sk-1+)
Memory
Clock signal
CLK
We will get back to FSM and clocked synchronous sequential circuits (in chapters
7 and 8) after we cover memory units.
Digital Circuits
Memory Units
'Flip-flop': One-bit memory unit. They are designed as multiple inputs, single
output logical circuit.
I0
I1 Output
Inputs Q Q(t+)= f( Q(t), I0, I1, ., In-1 )
FF
In-1 Q(t): Current value
Q(t+): Next value
CLK
Q output shows the current value of the flip-flop (0,1). This value is the state
of the flip-flop.
The next value of the output Q (denoted by Q(t+) or Q+) is a function of the
current state (denoted by Q(t) or Q) and the current inputs.
Clock signal (denoted as CLK) determines the time when the next state
function is evaluated and the output of the flip-flop changes its value.
The output of the flip-flop can only change when the clock signal is active (the
definition of being active will be described in the next slides).
If the clock signal is not active, flip-flop output will not change even if the
input values change.
Digital Circuits
Clock Signal: tH tL
Clock signal is a periodic square wave that synchronizes

the gates in the circuit.
tPER
Logic units with clock signal input (such as flip-flops) are enabled only when the
clock signal is active. If clock signal is not active, they preserve their state.
There are two types of units in terms of clock signal activation
a) Level-triggered units b) Edge-triggered units
Level-triggered units: Use a level of the clock signal (1 in positive logic) as active.
These units activate and change their outputs when the clock signal is at level 1.
They preserve their state when the clock signal is at level 0.
When the clock signal is at level 1, the inputs should not change as they are
processed. Otherwise the output of the sequential circuit is undetermined
(random).
This time is called register time.
The inputs can change when the clock signal is 0. This time is called settling time.
Settling Register
time Time
Digital Circuits
Edge-triggered units:
These units use an edge (rising edge in positive logic) of the clock signal as active.
Positive edge-triggered units use 01 transition of the clock signal (rising edge)
to change their state and output. At other times, they preserve their state.
In negative logic, all transactions happen at 10 transition (falling edge).
As the inputs are used (processed) during 01 transition, inputs should be kept
constant for certain time before and after the transition. Otherwise, the output
of the sequential unit is undetermined (random).
T he register time is the
addition of the setup and hold
Inputs times.
should be Setup time is the minimum
kept amount of time the data signal
constant Inputs can should be held steady before
change the clock transition.
Setup Hold
Time Time Hold time is the minimum
amount of time the data signal
Register Settling
Time Time
should be held steady after the
clock transition.
The inputs should be kept constant during the register time so that the sequential
circuit works correctly.
Digital Circuits
Example: Edge-triggered Toggle (T) Flip-Flop

Before detailed explanation of flip-flops, a T flip-flop is used as an example.
T T Q Q(t+)= T Q(t)
FF
Edge
Clock Triggered
The next output (state) of the T flip-flop Q(t+) is equal to its current output XOR
its input (T).
According to this, the output of the flip-flop does not change when T=0 as:
0 x = x
The output of the flip-flop is complemented when T=1 as:
1 x = x'
CLK
Q
Digital Circuits
Bistable (Two stable states) Circuit

Bistable units are formed by two inverters whose inputs
come from the output (feedback) of each other.
They have no inputs.
This circuit will always be in one of the two possible
stable states.
1.If the output of the inverter at the top is Vout1 (Q) = 0, the input of the inverter
at the bottom becomes Vin2 = 0, and its output becomes Vout2 (Q_L) = 1. This is a
stable state as this state requires Q = 0 and Vin1 = 1.
Vin1 = 1, Vout1 = Vin2 = 0, Vout2 = 1
2. If the output of the inverter at the top is Vout1 (Q) = 1, the input of the inverter
at the bottom becomes Vin2 = 1, and its output becomes (Q_L) = 0. This is also a
stable state as it requires Vin1 = 0 and Q = 1.
Vin1 = 0, Vout1 = Vin2 = 1, Vout2 = 0
This circuit has two stable states: Q=0 and Q=1
It is impossible to control (change) the state of the circuit as it has no inputs.
When this circuit is turned on, it takes a random state.
Examples for unstable circuits: or

Digital Circuits
S-R (Set-Reset) Latch

S-R Latch is a one bit memory built with two NAND or two NOR gates.
All other flip-flops can be built upon this fundamental memory with certain
extensions.
S-R latch with NOR gates:

1000
S 00 11 S: Set
QN R: Reset
Q: Output (State)
QN: Complemented output (Q')
Q Recall: When an input of a NOR gate is 1,

R 11 0 0 the output will be 0 regardless of the other
0010
input.
S R Q QN S input is used to write (store) 1 to the
1 0 1 0 latch, R input is used to write 0.
0 0 1 0 After S=1, R=0
0 1 0 1 If both inputs are "0, SR latch
0 0 0 1 After S=0, R=1 preserves its state.
1 1 0 0 Forbidden input Both inputs should not be 1 at the
same time.
Digital Circuits
Next value of the output (state) Q(t+1) depends on the inputs and current output
Q(t).
The truth table and the logical expression of the SR latch can be expressed as
follows:
Q(t) S R Q(t+1) Q(t+1) S
0 0 0 0 SR
Q(t) 00 01 11 10
0 0 1 0
0 1 0 1
0 1
0 1 1 forbidden() Q 1 1 1
1 0 0 1
1 0 1 0 R
1 1 0 1 Q(t+1)= S + Q(t)R', SR=0
1 1 1 forbidden()
S Q S Q
R QN R Q
Latches are not triggered by clock

signal.
Flip-flops are clock triggered memory
units.
Digital Circuits
Because of the propagation delay, the changes in the S and R inputs will not
affect the output simultaneously.
During the delay, the inputs should be kept constant. Otherwise, the value of
the output is undetermined (random).
Undetermined output
R
tpLH(SQ) tpHL(RQ) tpw(min)
tpLH(SQ): Delay in the 0-1 transition of the output when S changes.

tpHL(RQ): Delay in the 1-0 transition of the output when R changes.
tpW(min): Minimum duration when the inputs should be kept constant.
Digital Circuits
S-R Latch with Enable Input

AND gates are connected to S and R inputs so that the latch is active only when
it is enabled.
S: Set
S
QN R: Reset
Q: Output (State)
C QN: Complemented output (Q')
C: Enable input
Q The value of the latch can
R only be changed when C=1.
When C=0, the value of the
latch is preserved
Effective when regardless of the inputs.
Not enabled C=1
S SR=11
R
Output
C undetermined
QN
Digital Circuits
S-R Latch with Enable Input (with only NAND Gates)

S S-R Latch implemented with NOR
Q and AND gates (slide 6.16) can
also be implemented using only
C NAND gates.
If the forbidden input (SR=11)

QN
R is applied to the latch, both Q
C S R Q(t+1) and Q' outputs will be 1.
0 X X Q(t) If the latch is disabled in this
S Q
1 1 0 1 C state, the value in the latch is
1 0 1 0 R Q undetermined.
1 0 0 Q(t) Effective when
1 1 1 forbidden Not enabled C=1 SR=11
S
QN
Digital Circuits
Difference between Latch and Flip-flop:

Latches are not triggered by clock signal. The value of the latch can be changed
whenever it is enabled.
Memory units that are triggered by clock signal are called flip-flop.
S-R Latch with NAND Gates (S'-R' Latch)
S-R latches can be implemented using NAND gates instead of NOR. These units
are called S-R latch.
This latch is
0 111 S': Complement of Set different
S' 1 1 00
Q R': Complement of Reset than the one
in slide 6.17.
Q: Output (State)
QN: Complemented output (Q')
QN S' R' Q QN
R' 1 1 0 1 00 1 1
0 1 1 0
1 1 1 0 After S'=0, R'=1
Recall: If an input of a NAND 1 0 0 1
gate is 0, the output will be 1 1 1 0 1 After S'=1, R'=0
regardless of the other input. 0 0 1 1 Forbidden inputs
Digital Circuits
Delay (D) Latch

Other types of latches can be build upon S-R latch with some additions.
If the S and R inputs of the SR latch are connected with an inverter, D-latch is
obtained. C=1 D S R Q(t+)
Refer to slide 6.17.
0 0 1 0 (Reset)
S 1 1 0 1 (Set)
D
Q If C=1, the value of D input is
written to the latch.
C
C If C=0, latch preservers its
previous value.
QN C D Q(t+) QN(t+)
R SR Latch D Q
1 0 0 1
1 1 1 0
C Q 0 X Q(t) QN(t)
Q(t+1)=D
Q
Digital Circuits
Rising Edge Triggered D Flip-flop

Latches change their value (depending on their input) when they are enabled.
Flip-flops on the other hand, change their value when the clock signal is active.
QM D CLK Q QN
D D Q D Q Q
D Q
C C Q
0 0 1
QN
CLK Q 1 1 0
x 0 prev Q prev QN
CLK
x 1 prev Q prev QN
Edge
D Latch triggered
CLK
QM
QN
Digital Circuits
Timing properties of the rising edge triggered D flip-flop

Output is undetermined as the Output gets a valid value
inputs are not kept constant (1 in this example).
during the setup time.
CLK
thold
tpLH(CQ) tpHL(CQ) tsetup
tpLH(CQ): Delay between the active edge of clock and 0-1 transition of output.
tpHL(CQ): Delay between the active edge of clock and 1-0 transition of output.
tsetup : Time before active edge where inputs should be kept constant.
thold : Time after active edge where inputs should be kept constant.
Digital Circuits
Falling Edge Triggered D Flip-flop

Data is written to D flip-flop during the falling edge of the clock signal.
D D Q D Q Q D Q
C C Q QN CLK Q
CLK_L
D latch Falling edge
Triggered
In flip-flops (especially to write an initial value), there
D CLK_L Q QN may be asynchronous (independent of clock signal) inputs.
0 0 1 To write 1 to the flip-flop PR (Preset), to write 0 CLR
1 1 0
(Clear) inputs can be used.
Asynchronous inputs change the value of flip-flop even if
x 0 prev Q prev QN
the clock signal is not active.
x 1 prev Q prev QN
PR
D Q
CLK Q
CLR
Digital Circuits
Edge Triggered D Flip-flop with Enable Input

Flip-flops may also have an enable input. If the enable input is active, the value of
the flip-flop can be changed. Otherwise, it preserves its value regardless of its
inputs.
D
EN 0 2:1
D
CLK
Q Q = D 1 MUX D Q Q
Q QN CLK Q QN
EN s
CLK CLK
D E N CL K Q QN
0 1 0 1 D Q
EN
1 1 1 0
CLK Q
x 0 prev Q prev Q N
x x 0 prev Q prev Q N
x x 1 prev Q prev Q N
Digital Circuits
Master/Slave SR Flip-flop
Master/slave flip-flops are pulse triggered units. The value (output) of this type
of flip-flops changes only at the falling edge of the clock signal.
However, next value of the flip-flop can be determined while the clock signal is 1.
S R C Q QN
S S QM S
Q Q Q x x 0 prev Q prev QN S Q
C C
Q M_ L prev Q prev QN
Q Q QN 0 0 C
R R R
Q
0 1 0 1 R
C 1 0 1 0
1 1 undefined undefined
Master Slave
Ignored C=0 Effective when C=1 Effective when C=1
S
QM
Q M_ L
QN
Translated by Dr. Mustafa KAMAAK 2011 Dr. Feza BUZLUCA 5.24 6.24
Digital Circuits
JK Latch
The problem of forbidden inputs of the SR latches (S=1,R=1) is solved in JK latches.
These units function similar to SR latches. Input J sets and input K resets the
output.
When both inputs are "1" (J=1, K=1), the value (output) of the latch is complemented.
C=1 J K Q(t) S R Q(t+1) Operation

J S Q 0 0 0 0 0 0
Q Don't change
C QN 0 0 1 0 0 1
K R Q
0 1 0 0 0 0
Reset
0 1 1 0 1 0
C
1 0 0 1 0 1
Set
1 0 1 0 0 1
1 1 0 1 0 1 Complement
1 1 1 0 1 0
J K C Q QN
x x 0 prev Q prev QN
0 0 1 prev Q prev QN J Q
0 1 1 0 1 C
Q(t+1)=JQ(t)' + K'Q(t) Q
1 0 1 1 0 K
1 1 1 prev QN prev Q
Digital Circuits
Edge Triggered JK Flip-flop

An edge-triggered JK flip-flop can be implemented using an edge triggered D flip-
flop and logical gates.
In this unit, the J and K inputs are processed only at the active edge of the clock
signal.
J K CLK Q QN
x x 0 prev Q prev QN J Q
J
D Q Q x x 1 prev Q prev QN CLK
K Q
K 0 0 prev Q prev QN
CLK Q QN
0 1 0 1
CL K
1 0 1 0
1 1 prev QN prev Q
Q(t+1)=JQ(t)' + K'Q(t)
Digital Circuits
Edge Triggered Toggle (T) Flip-flop
T T Q Q(t+1)= T Q(t)
FF
Clock
The output (value) of a T flip-flop is determined by XOR operation of the input

(T) and the current value.
Therefore, if the input is 0 (T=0), the value of the flip-flop is preserved as:
0 x = x
If the input is 1 (T=1), the value of the flip-flop is complemented (toggled) as:
1 x = x'
Clock
Q

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Digital Circuits License: http://creativecommons.org/licenses/by-nc-nd/3.

Example: Input Output

tPHL: transition from H to L

Hazards caused by propagation delays

There are three types of hazards:

Static 0 Static 1 Dynamic

Avoiding hazards: Circuit at the left (implemented as

Finite State Machine (FSM) Model

Clock signal is a periodic square wave that synchronizes

Example: Edge-triggered Toggle (T) Flip-Flop

Bistable (Two stable states) Circuit

Examples for unstable circuits: or

S-R (Set-Reset) Latch

S-R latch with NOR gates:

Q Recall: When an input of a NOR gate is 1,

Latches are not triggered by clock

tpLH(SQ) tpHL(RQ) tpw(min)

tpLH(SQ): Delay in the 0-1 transition of the output when S changes.

S-R Latch with Enable Input

S-R Latch with Enable Input (with only NAND Gates)

If the forbidden input (SR=11)

Difference between Latch and Flip-flop:

Delay (D) Latch

Rising Edge Triggered D Flip-flop

Timing properties of the rising edge triggered D flip-flop

Falling Edge Triggered D Flip-flop

Edge Triggered D Flip-flop with Enable Input

C=1 J K Q(t) S R Q(t+1) Operation

Edge Triggered JK Flip-flop

Edge Triggered Toggle (T) Flip-flop

The output (value) of a T flip-flop is determined by XOR operation of the input

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