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Contents
No Experiment Name
1 Verification of Gates
2 Half Adder and Full Adder using Logic gates
3 Half Subtractor and Full Subtractor Logic gates
4 Parallel Adder and Subtractor
4 Excess 3 to BCD and Vce Versa
5 Binary Grey & Grey Binary Converter
6 MUX and DEMUX
7 MUX and DEMUX using NAND Gates
8 Comparators
9 Encoder and Decoder
10 Flip Flops
11 Counters
12 Shift Registers
13 Johnson and Ring Counters
14 Multivibrators
Shahjalal University of Science and [DEGITAL ELECTRONICS LAB MANUAL]
Technology Dept. of Electrical and Electronic Engineering (EEE)
Experiment No: 01
Aparatus :
Procedure:
2 Input NOR
Shahjalal University of Science and [DEGITAL ELECTRONICS LAB MANUAL]
Technology Dept. of Electrical and Electronic Engineering (EEE)
Experiment No: 02
Experiment Name: Half Adder and Full Adder using Basic Gates
Objective:
Procedure: