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Abstract At a factory which produces a wide variety of 1) there are few new machines, and the process technology
products such as ASICs or microcomputers, it is necessary is matured;
to detect any machine causing a bottleneck and return it to 2) as a result of capital depreciation, utilization of the
a high level of performance for fast and effective production.
This paper introduces a workflow control system called JUS- current equipment is cost effective;
TICE/MORAL (just time process control system/method of 3) most machines are reliable.
optimum-buffer restriction and adjustment logic) which dynam- Accordingly, the machines are kept in a state of high
ically detects a machine causing a bottleneck and feeds work to
that machine at an appropriate time.
throughput to the greatest extent possible. On the other hand,
The advantages of this system are as follows: 1) manufacturing this type of factory often has to meet the challenges described
cycle time can be reduced by an average of 13% and a maximum below:
of 50% and 2) throughput can be increased up to approximately 4) many different types of products are fabricated in small
10%. Part of this system has been installed in our factory. We
have seen that factory cycle time improved approximately 20% lot sizes;
in the two month period from July to September 1998. Also, the 5) the product-mix changes radically both in terms of type
machine causing the bottleneck was found quickly; as a result, and quantity;
the utilization of this machine increased by 3%. 6) the location of new machines is restricted by the current
Index TermsJob release control, production planning, sched- facility layout; as a result, a complete job-shop form is
uling, semiconductor manufacturing, system modeling and sim- hard to maintain;
ulation. 7) work is transported from shop to shop by both an
automated interbay transfer system and operators.
I. INTRODUCTION This degree of variability makes the control of the traditional
semiconductor production even more difficult. Thus, there
S EMICONDUCTOR manufacturing is one of the most
complex manufacturing processes found today. This com-
plexity is, in part, the result of the constant miniaturization
is a strong need for a system that can respond to diverse
changes in customers demands more quickly than ever. In
of various devices, the intricacy of the process, product di- such circumstances, the demand to reduce manufacturing cycle
versity, uncertainty due to external factors, and changing time (cycle time is defined as the time a particular lot spends in
technologies. In addition, semiconductor wafer fabrication the factory) is steadily increasing. It is therefore necessary to
requires the repetitive use of several similar processes. The detect any machines causing a bottleneck in order to obtain a
machines performing these operations are costly; thus, the high level of performance for fast and effective production. In
economic necessity of reducing capital outlays dictates that cases in which a sufficient amount of work-in-process (WIP)
such expensive machines be shared by all lots requiring the is not supplied to the bottlenecks, their throughput decreases
particular processing operation provided by the machine, even due to the machines being idle. On the other hand, too
though those lots may be of different processing stages in much WIP causes a lengthening of manufacturing cycle time
their manufacturing life. This makes production planning and [1], [9]. Our previous review of pertinent literature clarified
control in semiconductor wafer fabrication complicated. that a bottleneck machine was defined by its process speed,
In this paper, we focus on the problem of production line efficiency, and downtime variability [14]. However, the factory
control in a factory which produces a wide variety of products. is not designed for the current product-mix. As a result, the
This factory, which is a microcomputer and ASIC factory, is change of product-mix creates imbalances in the production
not a leading-edge factory as it was established 12 years ago. line. In addition, the possibility exists that the demand may
This type of factory has the following features: decrease after wafer input. This change causes an imbalance in
the WIP level and the machine load. It is difficult to detect the
bottleneck machine in this situation because the quota given to
Manuscript received December 7, 1998; revised April 5, 1999. each machine changes to such a large degree that the machine
T. Nakata is with Mitsubishi Electric Corporation, Manufacturing Engineer-
ing Center, Hyogo 661-8661, Japan (e-mail: nakata@mfe.mdl.melco.co.jp). causing the bottleneck (i.e., its quota is more than its own
K. Matsui, Y. Miyake, and K. Nishioka are with Mitsubishi capacity) frequently changes as shown in Fig. 1. With Photo
Electric Corporation, Kochi Factory, Kochi 781-5332, Japan (e- Type 3, for example, bottlenecks have appeared frequently
mail: matsuiko@mpl.koch.melco.co.jp; nishioka@mpl.koch.melco.co.jp;
miyake@isd.koch.melco.co.jp). over a two month period of due to changes in the product
Publisher Item Identifier S 0894-6507(99)06368-X. mix.
08946507/99$10.00 1999 IEEE
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274 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 3, AUGUST 1999
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NAKATA et al.: DYNAMIC BOTTLENECK CONTROL IN WIDE VARIETY PRODUCTION FACTORY 275
3) lot dispatching to determine which lot to process when next scheduling, which specifies the order of lots processed
a machine becomes available [3]. at each machine group. Similar articles are numerous in
The primary goal of wafer input is to control the level of the existing literature. Lu and Kumar [6] analyzed several
WIP and cycle times. It is calculated using a day or a week dispatching rules for a large semiconductor production line.
as a time unit over a long time span of two to four months. It would be difficult, however, to challenge bottlenecks issues
As a results, daily or weekly wafer outputs (i.e., production in diverse situations only through lot dispatching control.
targets) can also be determined. Many previous approaches Daily scheduling provides a bridge between these two
have attempted to resolve bottleneck issues. Glassey and aforementioned functions, and breaks daily production targets
Resende [1] presented a starvation avoidance (SA) rule and into a production schedule in a time span of 13 h over a day.
Wein [5] demonstrated a workload regulation (WR) rule. The This, in turn, serves as a guideline for dispatching. The need
difference between SA and WR is that Glassey and Resende for effective coordination of daily operations in a production
only consider work that will arrive at the bottleneck within line is significant [3]. There are some approaches which
the time required to feed new work to the machine where address this issue of controlling daily operations in multiple
the bottleneck has occurred, whereas Wein considers the total layers. Bechte [10] describes the principles of load-oriented
work content (of any lots on the line) which will be supplied manufacturing control which is useful in identifying bottle-
with the bottleneck machine. These two studies, however, do necks. This control rule has three planning levels: order entry
not address the cases that involve dynamic changes in the and mid-term capacity planning; order release and short-term
conditions that produce bottlenecks. Lu, Ramaswamy, and capacity planning and operation sequencing. Fargher et al.
Kumar [2] have shown that smoothing the flow of work within [11] describe two closely related CIM (computer-integrated-
the line can lead to substantial improvements in both the mean manufacturing) subsystems used to manage production con-
as well as the standard deviation of the cycle time. However, trol: MMST planner and scheduler. Akella et al. [12] report
the effectiveness of this method is questionable when it is on the performance of hierarchical production scheduling
applied at a variety production factory. In yet a different policy. These studies are concerned with the implementation
study, Glassey et al. [7] present linear control rules. Here, of workflow control in multiple layers. However, little atten-
they deal with the issue of reducing the cycle time for the tion has been given to the investigation of how to control
mass production of a single product. It is not clear, however, bottlenecks while paying attention to the factors underlying
that the given rules could sufficiently respond to changes in their occurrence and the cycle in which they occur. Nishimura
the product mix dynamically. [14] states that it is possible to divide all machines into four
Lot dispatching prioritizes processes on the shop floor in different classifications based on the type of bottleneck. In
order to respond appropriately to line status changes in real turn, bottlenecks are classified according to their downtime
time [4]. Connors et al. [8] focused on the issue of whats variability and the speed of processing wafers. However, this
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276 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 3, AUGUST 1999
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NAKATA et al.: DYNAMIC BOTTLENECK CONTROL IN WIDE VARIETY PRODUCTION FACTORY 277
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NAKATA et al.: DYNAMIC BOTTLENECK CONTROL IN WIDE VARIETY PRODUCTION FACTORY 279
Fig. 12. Our cycle time improvement from July to September 1998. VII. CONCLUSION
We have proposed a new workflow control system called
monitor screen by the line. Operators can readily receive JUSTICE/MORAL. This system can detect the exact ma-
information about their next task. chine causing a bottleneck through three phases. All work
movements are controlled by keeping an appropriate level of
WIP in the bottleneck machine. A standard level of WIP is
VI. EFFECT OF JUSTICE/MORAL INTRODUCTION
dynamically calculated for the machine currently experiencing
The following effects are expected based on simulations a bottleneck. The WIP level in that machine is then managed in
in which the whole system was utilized. The simulation was order to maintain a standard amount of WIP. This establishes
modeled using actual data about the line. Two different control maximum throughput with minimum manufacturing cycle
methods, the FIFO rule and the MORAL rule, were compared. time. The advantages of the system are as follows:
The results of the simulation appear in the queue length of each 1) manufacturing cycle time can be reduced by an average
machine. Fig. 9 shows a comparison between MORAL and of 13% and a maximum of 50%;
FIFO (WIP/throughput of the machine causing the bottleneck). 2) throughput can be increased up to approximately 10%.
MORAL tended to retain WIP near bottleneck machines in
Part of this system has been installed in our factory. We have
order to avoid idle time. The conventional workflow control
had the following results:
system, which uses only one policy, could not respond to
the various changes in the bottlenecks. Therefore, WIP is 3) cycle time improved approximately by 20% in the two
unleveled everywhere in the line. The JUSTICE/MORAL month period from July to September 1998;
system decides workflow policy in all phases from the plan- 4) the machine causing the bottleneck was found quickly;
ning values of the weekly standard which are based on the as a result, the utilization of this machine increased by
long range forecast. The system then extracts candidates for a 3%.
bottleneck, focuses the bottleneck strategy after considering
the WIP level, and dispatches the work to the bottleneck. REFERENCES
MORAL feeds only the necessary amount of WIP to each [1] C. R. Glassey and G. C. M. Resende, Closed-loop job release control
machine, with dynamically considering the quota, the capacity for VLSI circuit manufacturing, IEEE Trans. Semiconduct. Manufact.,
vol. 1, pp. 3646, Feb. 1988.
and the queue length. As a result, manufacturing cycle time [2] S. C. H. Lu, D. Ramaswamy, and P. R. Kumar, Efficient scheduling
was reduced by 13% as shown in Fig. 10 (50% for a certain policies to reduce mean and variance of cycle-time in semiconductor
product), and throughput became 10% higher than in the manufacturing plants, IEEE Trans. Semiconduct. Manufact., vol. 7, pp.
374388, Feb. 1994.
conventional workflow control method (see Fig. 11). [3] D. Y. Liao, S. C. Chang, K. W. Pei, and C. M. Chang, Daily sched-
As a result, cycle time of the entire line will be improved be- uling for R&D semiconductor fabrication, IEEE Trans. Semiconduct.
cause work will be supplied to each machine when necessary. Manufact., vol. 9, pp. 550561, Feb. 1996.
[4] J. E. Dayhoff and R. W. Atherton, Signature analysis of dispatch
JUSTICE/MORAL manages the line to keep the required schemes in wafer fabrication, IEEE Trans. Comp., Hybrids, Manufact.
standard WIP level without decreasing throughput. Technol., vol. CHMT-9, pp. 518525, Dec. 1986.
Authorized licensed use limited to: SUNY Buffalo. Downloaded on February 1, 2009 at 02:47 from IEEE Xplore. Restrictions apply.
280 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 3, AUGUST 1999
[5] L. M. Wein, Scheduling semiconductor wafer fabrication, IEEE Trans. Koichi Matsui received the B. E. degree from the
Semiconduct. Manufact., vol. 1, pp. 115130, Aug. 1988. Science University of Tokyo, Japan, in 1986.
[6] S. H. Lu and P. R. Kumar, Distributed scheduling based on due He joined the Production System Engineering
dates and buffer priorities, IEEE Trans. Automat. Contr., vol. 36, pp. Section, Kochi Factory, Mitsubishi Electric Corpo-
14061416, Dec. 1991. ration, Kochi, Japan, where he has been engaged
[7] C. R. Glassey, J. G. Shanthikumar, and S. Seshadri, Linear con- in research and development of production control
trol rules for production control of semiconductor fabs, IEEE Trans. system.
Semiconduct. Manufact., vol. 9, pp. 536549, Feb. 1996.
[8] D. Connors, G. Feigin, and D. Yao, Scheduling semiconductor lines
using a fluid network model, IEEE Trans. Robot. Automat., vol. 10,
pp. 88, Apr. 1994.
[9] L. M. Wein, On the relationship between yield and cycle time in
semiconductor wafer fabrication, IEEE Trans. Semiconduct. Manufact.,
vol. 5, pp. 156158, May 1992.
[10] W. Bechte, Theory and practice of load-oriented manufacturing con-
trol, Int. J. Prod. Res., vol. 26, no. 3, pp. 375395, 1988.
[11] H. E. Fargher, M. A. Kilgore, P. J. Kline, and R. A. Smith, A Yasuhisa Miyake received the B.S. degree from
planner and scheduler for semiconductor manufacturing, IEEE Trans. Kochi University, Kochi, Japan, in 1986.
Semiconduct. Manufact., vol. 7, pp. 117126, May 1994. He is an Assistant Manager in the Kochi System
[12] R. Akella, Y. Choong, and S. B. Gershwin, Performance of hierarchical Section, Ryoden Semiconductor System Engineer-
production scheduling policy, IEEE Trans. Comp., Hybrids, Manufact. ing Corporation, Kochi, Japan.
Technol., vol. CHMT-7, pp. 225240, Sept. 1984.
[13] B. Ehteshami, R. G. Petrakian, and P. M. Shabe, Trade-offs in cycle
time management: Hot lots, IEEE Trans. Semiconduct. Manufact., vol.
5, pp. 101106, May 1992.
[14] M. Nishimura, Strategic inventory control for stable production, in
Proc. ISSM97, pp. A-1A-4.
Tomohito Nakata received the B.E. degree in in- Kyusaku Nishioka received the B.S. degree in
dustrial engineering from Osaka Prefecture Univer- physical chemistry and the Ph.D. degree from Osaka
sity, Osaka, Japan, in 1991. University, Osaka, Japan, in 1970 and 1977.
In 1991, he joined the Manufacturing Engineer- From 1977 to 1980, he was with VLSI Labora-
ing Center, Mitsubishi Electric Corporation, Hyogo, tory, Kanagawa, Japan. Currently, he is with Kochi
Japan, where he has been engaged in research and Factory, Mitsubishi Electric Corporation, Kochi,
development of production control and scheduling Japan. His research interests have been in the ar-
system. His recent interests are in the areas of manu- eas of microelectronics, process engineering, and
facturing system flow control, job-shop scheduling, production control.
and communication network analysis using queuing
models.
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