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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO.

3, AUGUST 1999 273

Dynamic Bottleneck Control in


Wide Variety Production Factory
Tomohito Nakata, Koichi Matsui, Yasuhisa Miyake, and Kyusaku Nishioka

Abstract At a factory which produces a wide variety of 1) there are few new machines, and the process technology
products such as ASICs or microcomputers, it is necessary is matured;
to detect any machine causing a bottleneck and return it to 2) as a result of capital depreciation, utilization of the
a high level of performance for fast and effective production.
This paper introduces a workflow control system called JUS- current equipment is cost effective;
TICE/MORAL (just time process control system/method of 3) most machines are reliable.
optimum-buffer restriction and adjustment logic) which dynam- Accordingly, the machines are kept in a state of high
ically detects a machine causing a bottleneck and feeds work to
that machine at an appropriate time.
throughput to the greatest extent possible. On the other hand,
The advantages of this system are as follows: 1) manufacturing this type of factory often has to meet the challenges described
cycle time can be reduced by an average of 13% and a maximum below:
of 50% and 2) throughput can be increased up to approximately 4) many different types of products are fabricated in small
10%. Part of this system has been installed in our factory. We
have seen that factory cycle time improved approximately 20% lot sizes;
in the two month period from July to September 1998. Also, the 5) the product-mix changes radically both in terms of type
machine causing the bottleneck was found quickly; as a result, and quantity;
the utilization of this machine increased by 3%. 6) the location of new machines is restricted by the current
Index TermsJob release control, production planning, sched- facility layout; as a result, a complete job-shop form is
uling, semiconductor manufacturing, system modeling and sim- hard to maintain;
ulation. 7) work is transported from shop to shop by both an
automated interbay transfer system and operators.
I. INTRODUCTION This degree of variability makes the control of the traditional
semiconductor production even more difficult. Thus, there
S EMICONDUCTOR manufacturing is one of the most
complex manufacturing processes found today. This com-
plexity is, in part, the result of the constant miniaturization
is a strong need for a system that can respond to diverse
changes in customers demands more quickly than ever. In
of various devices, the intricacy of the process, product di- such circumstances, the demand to reduce manufacturing cycle
versity, uncertainty due to external factors, and changing time (cycle time is defined as the time a particular lot spends in
technologies. In addition, semiconductor wafer fabrication the factory) is steadily increasing. It is therefore necessary to
requires the repetitive use of several similar processes. The detect any machines causing a bottleneck in order to obtain a
machines performing these operations are costly; thus, the high level of performance for fast and effective production. In
economic necessity of reducing capital outlays dictates that cases in which a sufficient amount of work-in-process (WIP)
such expensive machines be shared by all lots requiring the is not supplied to the bottlenecks, their throughput decreases
particular processing operation provided by the machine, even due to the machines being idle. On the other hand, too
though those lots may be of different processing stages in much WIP causes a lengthening of manufacturing cycle time
their manufacturing life. This makes production planning and [1], [9]. Our previous review of pertinent literature clarified
control in semiconductor wafer fabrication complicated. that a bottleneck machine was defined by its process speed,
In this paper, we focus on the problem of production line efficiency, and downtime variability [14]. However, the factory
control in a factory which produces a wide variety of products. is not designed for the current product-mix. As a result, the
This factory, which is a microcomputer and ASIC factory, is change of product-mix creates imbalances in the production
not a leading-edge factory as it was established 12 years ago. line. In addition, the possibility exists that the demand may
This type of factory has the following features: decrease after wafer input. This change causes an imbalance in
the WIP level and the machine load. It is difficult to detect the
bottleneck machine in this situation because the quota given to
Manuscript received December 7, 1998; revised April 5, 1999. each machine changes to such a large degree that the machine
T. Nakata is with Mitsubishi Electric Corporation, Manufacturing Engineer-
ing Center, Hyogo 661-8661, Japan (e-mail: nakata@mfe.mdl.melco.co.jp). causing the bottleneck (i.e., its quota is more than its own
K. Matsui, Y. Miyake, and K. Nishioka are with Mitsubishi capacity) frequently changes as shown in Fig. 1. With Photo
Electric Corporation, Kochi Factory, Kochi 781-5332, Japan (e- Type 3, for example, bottlenecks have appeared frequently
mail: matsuiko@mpl.koch.melco.co.jp; nishioka@mpl.koch.melco.co.jp;
miyake@isd.koch.melco.co.jp). over a two month period of due to changes in the product
Publisher Item Identifier S 0894-6507(99)06368-X. mix.
08946507/99$10.00 1999 IEEE

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274 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 3, AUGUST 1999

Fig. 1. Product mix effects on the bottleneck.

Fig. 2. Framework of dynamic bottleneck control.

The first purpose of this research is to propose a new method


for effective production control which can deal with changes
in the bottlenecks. Fig. 3. Outline of the dynamic bottleneck control system JUSTICE/
In order to deal with the real production problem of which MORAL.
lot to assign next, it is necessary to take the human factor
into account. If the factory is fully automated, a computer
system generates job scheduling and gives orders directly to a a system that helps eliminate such bottlenecks correspond to
manufacturing system through network. However, if operators different situations. Section IV introduces a simple method for
in a specific area decide which lot to process next, it is providing instructions to operators using the concept of Hot
very important for operators the order is simple and easily to Lots. Section V introduces JUSTICE/MORAL a system
understand. The second purpose of this research is to propose which implements the ideas discussed in previous sections.
a manufacturing direction and execution system which can Finally, Section VI reports on the improvements achieved
solve the problem of bottlenecks. through the use of JUSTICE/MORAL.
At a factory which produces a wide variety of products,
we are introducing the workflow control system called JUS-
II. PREVIOUS STUDY
TICE/MORAL (just timing process control system/method
of optimum-buffer restriction and adjustment logic) which Production planning and control of semiconductor wafer
dynamically detects a machine causing a bottleneck and feeds manufacturing is extremely complicated and particularly dif-
work to the machine at the appropriate time. ficult. The development of production planning and control
Section II provides a review of past studies conducted on in a semiconductor wafer factory is still a very challenging
production planning and the control of semiconductor wafer research topic. Major production control issues include:
manufacturing at variety production factories. Section III ana- 1) input of raw wafers into the line;
lyzes bottlenecks at variety production factories and introduces 2) daily scheduling;

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NAKATA et al.: DYNAMIC BOTTLENECK CONTROL IN WIDE VARIETY PRODUCTION FACTORY 275

Fig. 4. GUI of extracting candidates for the bottleneck.

3) lot dispatching to determine which lot to process when next scheduling, which specifies the order of lots processed
a machine becomes available [3]. at each machine group. Similar articles are numerous in
The primary goal of wafer input is to control the level of the existing literature. Lu and Kumar [6] analyzed several
WIP and cycle times. It is calculated using a day or a week dispatching rules for a large semiconductor production line.
as a time unit over a long time span of two to four months. It would be difficult, however, to challenge bottlenecks issues
As a results, daily or weekly wafer outputs (i.e., production in diverse situations only through lot dispatching control.
targets) can also be determined. Many previous approaches Daily scheduling provides a bridge between these two
have attempted to resolve bottleneck issues. Glassey and aforementioned functions, and breaks daily production targets
Resende [1] presented a starvation avoidance (SA) rule and into a production schedule in a time span of 13 h over a day.
Wein [5] demonstrated a workload regulation (WR) rule. The This, in turn, serves as a guideline for dispatching. The need
difference between SA and WR is that Glassey and Resende for effective coordination of daily operations in a production
only consider work that will arrive at the bottleneck within line is significant [3]. There are some approaches which
the time required to feed new work to the machine where address this issue of controlling daily operations in multiple
the bottleneck has occurred, whereas Wein considers the total layers. Bechte [10] describes the principles of load-oriented
work content (of any lots on the line) which will be supplied manufacturing control which is useful in identifying bottle-
with the bottleneck machine. These two studies, however, do necks. This control rule has three planning levels: order entry
not address the cases that involve dynamic changes in the and mid-term capacity planning; order release and short-term
conditions that produce bottlenecks. Lu, Ramaswamy, and capacity planning and operation sequencing. Fargher et al.
Kumar [2] have shown that smoothing the flow of work within [11] describe two closely related CIM (computer-integrated-
the line can lead to substantial improvements in both the mean manufacturing) subsystems used to manage production con-
as well as the standard deviation of the cycle time. However, trol: MMST planner and scheduler. Akella et al. [12] report
the effectiveness of this method is questionable when it is on the performance of hierarchical production scheduling
applied at a variety production factory. In yet a different policy. These studies are concerned with the implementation
study, Glassey et al. [7] present linear control rules. Here, of workflow control in multiple layers. However, little atten-
they deal with the issue of reducing the cycle time for the tion has been given to the investigation of how to control
mass production of a single product. It is not clear, however, bottlenecks while paying attention to the factors underlying
that the given rules could sufficiently respond to changes in their occurrence and the cycle in which they occur. Nishimura
the product mix dynamically. [14] states that it is possible to divide all machines into four
Lot dispatching prioritizes processes on the shop floor in different classifications based on the type of bottleneck. In
order to respond appropriately to line status changes in real turn, bottlenecks are classified according to their downtime
time [4]. Connors et al. [8] focused on the issue of whats variability and the speed of processing wafers. However, this

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276 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 3, AUGUST 1999

research seems to have not considered the effect of the change


of product-mix on the bottleneck.

III. BOTTLENECK ANALISIS


Bottlenecks are caused by various situational changes such
as sudden machine breakdowns, delay in work progress,
nonscheduled machine maintenance, and the change of product
mix. We classify these factors in terms of their frequency or
action cycle and investigate the best way to respond to the
bottleneck problem. An example of a bottleneck and a way to
resolve it are shown in Fig. 2.
Fig. 5. Example of standard time table.
We thought that bottlenecks can not be completely fixed at
anytime; because they occur as the result of a wide variety
of different situations. In order to avoid bottlenecks, dynamic
control, such as the real time dispatching rule, the WIP
restriction, and wafer input control, is required.
The cause of bottlenecks is classified into the following
three cases according to their appearance cycles.
Case 1The Appearance of Long-Cycled Bottlenecks: In
this case, the maximum capacity during stable operation is
less than the norm (i.e., the quota which must be processed)
at each machine. In this phase, the bottleneck appears because
of reasons such as product-mix variability, change of process Fig. 6. Example of daily policy (leveling WIP strategy).
design, and setting up a new machine. Thus, the candidate
for a bottleneck must be kept operating at a high level, and
therefore, it is necessary that wafer input timing be controlled, operators is Hot Lots handling. Hot Lots are defined as work
the machines be well maintained, and machine capacity be which has been designated as having the highest priority in a
improved. factory in terms of reducing their cycle time [13]. All other
Case 2The Appearance of Midcycled Bottlenecks: In this work is known as regular lots. First, operators check to see
case, the maximum capacity is more than the norm, but the which jobs have Hot Lots, and then they begin to process these
WIP queue will often occur over the course of several days. lots. Therefore, operators must be able to easily determine
In this phase, bottlenecks occur because, for example, there is whether any work has been designated as Hot Lots. Hot
a decrease in demand from customers or a request for early Lots indicator is usually attached on each carrying case,
delivery after wafers have already been input. It is necessary or is displayed on the monitor in manufacturing line. We
to avoid making long queue, to clear it. propose a method utilizing this principle of Hot Lots to
Case 3The Appearance of Short-Cycled Bottlenecks: In realize a manufacturing system can control bottlenecks. All
this final case, work can not proceed on schedule due to sudden work are classified into three types: a) quick-turnaround-
machine breakdowns. Thus, it is necessary that replanning of time (QTAT) lots designated as RAPID, b) normal lots
the workflow policy be accomplished in real-time. designated as NORMAL, and c) low priority lots designated
We propose a system that uses three different processes as SUSPENDED. Lots are reassigned to these classes in real-
in order to address different types of changes described in time according to bottleneck status change. The lot processing
the above three cases. The first process concerns forecasting order for each machine is not calculated in the first step; rather,
situational changes and then planning accordingly. The second instructions to hurry up or not is provided for every lot.
process involves scheduling daily work and planning daily
policy when the bottleneck changes. The third is the process V. OUTLINE OF JUSTICE/MORAL
that reflects daily policy in production efficiently and in a
JUSTICE/MORAL has three major parts. The first is
timely manner. The utilization of these three processes allows
a phased adjustment process function which estimates or
different responses to bottlenecks which appear under different
predicts changes in bottleneck situations and plans corrective
conditions.
actions. This is combined with a function which gives pro-
duction orders for individual lot after considering the effect of
IV. SIMPLE DIRECTION the corrective actions. The second is a function which controls
The method of ordering direction to carry out manufacturing individual lot speed dynamically and offers a framework for;
is extremely important. In a fully automated factory, an order the third part, which is the execution of manufacturing orders.
of a schedule can be easily directed to automation system. The phased adjustment process function uses three control
However, in a case of which operators decide which lot is processes. The first is a monthly/weekly control process which
to be processed next, it is important to simplify the order to addresses long-term changes such as changes in the product
be easily understood. One of the most simple directions for mix. The second is a daily control process which addresses

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NAKATA et al.: DYNAMIC BOTTLENECK CONTROL IN WIDE VARIETY PRODUCTION FACTORY 277

Fig. 7. Dispatching logic in MORAL rule.

midterm changes such as day-to-day production delays caused


by, e.g., machine maintenance. Finally, a real time control
is utilized in order to respond to short-term changes such as
delays caused by sudden machine failure. The combination
of these three different control processes allows to effec-
tively buffer the changes in bottleneck conditions arising from
different causes.
An outline of JUSTICE/MORAL is shown in Fig. 3.

A. Phased Adjustment Process to Changes In Bottlenecks


1) Monthly/Weekly Control Process: Two different mod-
ules achieve this process. The first module predicts changes
in the product mix, simulates future changes in bottleneck
conditions, and detects possible locations of bottlenecks.
Fig. 8 Architecture of dynamic speed control.
In consideration of changes in the timings of deliveries
requested by customers and after accounting for the need
TABLE I
to give adequate instructions regarding machines that can LOT SPEED MATRIX
potentially produce a bottleneck, the second module optimizes
the standard weekly production volume.
a) The module for extracting candidates for the bottleneck:
JUSTICE/MORAL simulates the influence of the machine
load caused by changes in customer demand, and then extracts
a group of machines which are candidates for a bottleneck. The
result of this forecast is displayed on the monitor as shown in norm in order to determine what would be suitable load for
Fig. 4 to support the implementation of an improvement plan. a bottleneck candidate. Moreover, it calculates the standard
The upper display portion of this GUI (graphical user progress. Fig. 5 shows an example of the progress timetable.
interface) allows to specify of simulation parameters, while The total process flow is divided into sequential steps in which
the lower portion displays the outcome of the simulation the processes have the same standard day.
performed using the specified parameters. 2) Daily Control Process:
b) The module for planning the values of the weekly stan- The module for focusing on the bottleneck: Based on the
dard: JUSTICE/MORAL plans the values of a weekly weekly standard and the production conditions up to the
standard (e.g., the progress timetable and the quota for each previous day, JUSTICE/MORAL focuses on the bottleneck
machine) and decides the input time into the line in order machine. The bottleneck machine may change every day.
to prevent the occurrence of a bottleneck. And, it plans the An unexpected machine failure or a decrease of process

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278 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 12, NO. 3, AUGUST 1999

Fig. 9. Comparison between MORAL and FIFO (WIP/throughput of the bottleneck).

throughput causes a long queue at a machine. Moving this WIP


to the standard step is the purpose of this procedure. Therefore,
it is necessary to plan a daily policy against bottlenecks
based on the followings; skilled operators bottleneck strategy
in which the WIP does not pile up in front of a certain
machine, the supply of work to a machine causing a bottleneck
is reduced in consideration of regular maintenance of the
machine, or the progress of a specific lot is hastened. Fig. 6
shows an example of the daily policy. The factors are
automatically calculated. Fig. 10. Simulation results (cycle time).
3) Real Time Control Process:
The module for controlling work at the bottleneck:
JUSTICE/MORAL calculates the appropriate amount of 2) Bottleneck Status Standard: Each machine is classified
WIP should be kept in front of each machine in real time, into one of three categories based on information about the
feeds the appropriate work into the machine, and controls machines capacity, the quota, and the current amount of
the workflow based on the daily policy. A simple example WIP. The categories are CROWDED, PROPER, and
is shown in Fig. 7. Machine , which currently has no HUNGRY. For example, a machine will be classified as
work, is the bottleneck. JUSTICE/MORAL synchronizes CROWDED if the amount of WIP readily available is
the bottleneck condition with all the machines in the lines, equal to or larger than the machines daily quota. A machine
and controls the progress speed of all lots. This permits more is classified as HUNGRY if the amount of WIP readily
intelligent control throughout the entire line than what can available is equal to or less than the machines correspond
be achieved utilizing a conventional dispatching rule (i.e., to four-hour process time capacity. The rest are classified as
FIFO: first in first out). PROPER. Each machine is classified independently.
3) Final Decision of Individual Lot Speed: Finally, each
lot is assigned one of three speed classifications using the lot
B. Dynamic Speed Control System of Individual Lots speed matrix (Table I). The three classifications are RAPID,
A MORAL rule directs the progress speed of each lot NORMAL, and SUSPENDED. The speed is decided by
in real time. The architecture is shown in Fig. 8. This is a the progress status of each lot and the bottleneck status of
classification method based on the progress status of the lot and the machine that is scheduled on the process route of each
the bottleneck status of the machine for a certain time interval lot. Furthermore, the speed classification is updated at certain
before dispatching work to each machine. The machines and intervals (e.g., every 4 h) according to status changes in the
operators in the line execute the manufacturing orders which line. Work is fed to each machine based on the dispatching
are sorted by speed. These directions are visibly indicated on rule of each speed classification. RAPID is higher priority than
their carrying case. NORMAL, and lots which are classified as SUSPENDED are
1) Progress Status Standard: Each lot is classified into one not allocated to a machine. The work can be effectively fed
of three categories based on information from the progress to the bottleneck utilizing this method.
timetable about the processing target and the customer delivery
date. The categories are ADVANCED, JUST IN TIME,
and BEHIND. For example, the lot which is more than C. The Execution of the Manufacturing Order
two days behind the standard time table is categorized into Orders are transmitted to various manufacturing resources
the BEHIND class, and the lot that is more than three including the automatic processing equipment, the interbay
days in advance into the ADVANCED class. The lot which transfer system, AGVs (automated guided vehicles), and
does not fit in those two categories is classified as JUST the storage rack. These machines automatically process the
IN TIME. Each lot is classified into one of these categories. most appropriate work according to the order. Operators for
This classification is independent of the status of a machine; the manual-processing machines are informed of the orders
whether it is in operation or not. through operation instructions, which are displayed on the

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NAKATA et al.: DYNAMIC BOTTLENECK CONTROL IN WIDE VARIETY PRODUCTION FACTORY 279

Fig. 11. Simulation results (throughput).

Part of this system has been introduced to our factory.


At the same time, other improvements such as increased
machine operating time, better process design, and increases
in operators skills are continuing; therefore, it is difficult to
distinguish the effect of the introduction of this system from
other activities. However, the system enabled the machine
causing a bottleneck to be found rapidly, so utilization of this
machine improved by 3%. Moreover, cycle time was improved
approximately by 20% for two months from July to September
1998 (see Fig. 12).

Fig. 12. Our cycle time improvement from July to September 1998. VII. CONCLUSION
We have proposed a new workflow control system called
monitor screen by the line. Operators can readily receive JUSTICE/MORAL. This system can detect the exact ma-
information about their next task. chine causing a bottleneck through three phases. All work
movements are controlled by keeping an appropriate level of
WIP in the bottleneck machine. A standard level of WIP is
VI. EFFECT OF JUSTICE/MORAL INTRODUCTION
dynamically calculated for the machine currently experiencing
The following effects are expected based on simulations a bottleneck. The WIP level in that machine is then managed in
in which the whole system was utilized. The simulation was order to maintain a standard amount of WIP. This establishes
modeled using actual data about the line. Two different control maximum throughput with minimum manufacturing cycle
methods, the FIFO rule and the MORAL rule, were compared. time. The advantages of the system are as follows:
The results of the simulation appear in the queue length of each 1) manufacturing cycle time can be reduced by an average
machine. Fig. 9 shows a comparison between MORAL and of 13% and a maximum of 50%;
FIFO (WIP/throughput of the machine causing the bottleneck). 2) throughput can be increased up to approximately 10%.
MORAL tended to retain WIP near bottleneck machines in
Part of this system has been installed in our factory. We have
order to avoid idle time. The conventional workflow control
had the following results:
system, which uses only one policy, could not respond to
the various changes in the bottlenecks. Therefore, WIP is 3) cycle time improved approximately by 20% in the two
unleveled everywhere in the line. The JUSTICE/MORAL month period from July to September 1998;
system decides workflow policy in all phases from the plan- 4) the machine causing the bottleneck was found quickly;
ning values of the weekly standard which are based on the as a result, the utilization of this machine increased by
long range forecast. The system then extracts candidates for a 3%.
bottleneck, focuses the bottleneck strategy after considering
the WIP level, and dispatches the work to the bottleneck. REFERENCES
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Tomohito Nakata received the B.E. degree in in- Kyusaku Nishioka received the B.S. degree in
dustrial engineering from Osaka Prefecture Univer- physical chemistry and the Ph.D. degree from Osaka
sity, Osaka, Japan, in 1991. University, Osaka, Japan, in 1970 and 1977.
In 1991, he joined the Manufacturing Engineer- From 1977 to 1980, he was with VLSI Labora-
ing Center, Mitsubishi Electric Corporation, Hyogo, tory, Kanagawa, Japan. Currently, he is with Kochi
Japan, where he has been engaged in research and Factory, Mitsubishi Electric Corporation, Kochi,
development of production control and scheduling Japan. His research interests have been in the ar-
system. His recent interests are in the areas of manu- eas of microelectronics, process engineering, and
facturing system flow control, job-shop scheduling, production control.
and communication network analysis using queuing
models.

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