SR FLIP FLOP

module sr(q,qbar,s,r,clk);

output q,qbar;

input s,r,clk;

reg q,qbar;

initial

begin

q=1'b0;

qbar=1'b1;

end

always@ (posedge clk)

begin

case ({s,r})

{1'b0,1'b0}:begin q=q; qbar=qbar;end

{1'b0,1'b1}:begin q=1'b0; qbar=1'b1;end

{1'b1,1'b0}:begin q=1'b1; qbar=1'b0;end

{1'b1,1'b1}:begin q=1'bx; qbar=1'bx;end

endcase

end

endmodule

TEST BENCH
module sr1_tb;
// Inputs

reg s;

reg r;

reg clk;

// Outputs

wire q;

wire qbar;

// Instantiate the Unit Under Test (UUT)

sr1 uut (

.q(q),

.qbar(qbar),

.s(s),

.r(r),

.clk(clk)

);

initial begin

// Initialize Inputs

s = 0;r = 0;clk = 0;#100;

s = 0;r = 0;clk = 1;#100;

s = 0;r = 1;clk = 0;#100;

s = 0;r = 1;clk = 1;#100;

 s = 1;r = 0;clk = 0;#100;

s = 1;r = 0;clk = 1;#100;

s = 1;r = 1;clk = 0;#100;

s = 1;r = 1;clk = 1;#100;

// Add stimulus here

end

endmodule