UNIT-V

SINGLE STAGE AMPLIFIERS

5.1. TWO PORT NETWORK:

A transistor can be treated as a 2-port network as shown below.

Fig1: Two port network

Actually a 2 port network requires 4 terminals, 2 for input port and 2 for
output port; but transistor has only 3 terminals. So by taking a terminal common to
input and output ports we can consider a transistor as a 2 port network.

In 2 port network shown in Fig1,

v1=input port voltage

i1=input port current

v2=output port voltage

i2=output port current

Out of these 4 variables 2 are considered as independent variables and the

remaining two are considered as dependent variables.

5.1.1. Case1: Open circuit impedance or z-parameters: -

v1 and v2 as dependent parameters

& i1 and i2 as independent parameters.

v1=z11i1+z12i2

v2=z21i1+z22i2
 v
1
z11= i i =0 open circuit input impedance (
2
1

v
1
z12= i i =0 open circuit reverse transfer impedance (
1
2

v2
z21= i i =0 open circuit forward transfer impedance( )
2
1

v2
z22= i i =0 open circuit output impedance()
1
2

These are called open circuit impedance parameters or z-parameters as they

are calculated under open circuit condition and all are representing voltage to
current ratios.

5.1.2. Case2: Short circuit admittance or y-parameters:

i1, i2 as dependent parameters

& v1, v2 as independent parameters.

i1=y11v1+y12v2

i2=y21v1+y22v2
i1
y11= v v =0 short circuit input admittance ( )
2
1

i1
y12= v v =0 short circuit transfer reverse admittance ( )
1
2

i2
y21= v v =0 short circuit transfer forward admittance ()
2
1

i2
y22= v v =0 short circuit output admittance ( )
1
2

These are called short circuit admittance parameters or y-parameters

as they are calculated under short circuit condition and all are representing current
to voltage ratios.
5.1.3. Case3: hybrid or h-parameters: -

v1, i2 as dependent parameters

& i1, v2 as independent parameters

v1=h11i1+h12v2

i2=h21i1+h22v2
v
1
h11= i v =0 short circuit input impedance ( = hi
2
1

v1
h12= v i =0 open circuit reverse voltage gain=hr (no units)
1
2

i2
h21= i V =0 short circuit forward current gain=hf (no units)
2
1

i2
h22= V i =0 open circuit output admittance=h0 ( )
1
2

These are not having same units, so called as hybrid or h-parameters.

Like wise

Case 4, Case 5etc.

In transistor characteristics (studied in unit-3), we learn that input current

and output voltage are independent parameters. So we can use h-parameters model
to represent transistor.

5.2. How to represent a transistor using h-parameter model? :

h-parameter equations are

v1=hii1+hrv2 --------------> (1)

i2=hfi1+hov2 ----------------> (2)

Each term in equation (1) represents a voltage so we have to form a

mesh such that whose Kirchhoffs voltage law (KVL) should be equation (1). Each
term in equation (2) represents a current so we have to form a node such that
whose Kirchhoffs current law (KCL) should be equation (2).

Step: -1

Consider a two port network as shown in Fig 2(a)

Fig2(a) : Initiation to represent transistor in h-parameter model

Step:-2 ho v 2
+ hi
hr v 2 hf i 1 ho
hi i1

Fig 2(b): h- parameter model of transistor

hrv2 and hfi1 cannot be directly related to input port and output ports respectively.
So, indicated as dependent sources in Fig 2(b).

5.3. How the h-parameter model help in analysis? :

BJT (Bipolar junction transistor) is a non-linear device. h-parameter
model is nothing but linear ( linear equations), so by considering a transistors
characteristics piece wise linearly, we can find voltage gain, current gain, power
gain, input impedance, output impedance, ..etc.

5.4. Analysis of single stage transistor amplifier using h-parameters:

Consider h-parameter equivalent circuit of general amplifier.

i1 hi i2
<
RS + +
v
v1 ho v2
v S~ hr v 2
hf i 1 _ ZL
-
 Fig 3: transistor amplifier h-parameter representation

(a) Current gain( A I : It is defined as the ratio of load current (iL) to input
current (i1). So
iL i 2
AI = i = i (from Fig3, iL=-i2)
1 1

From equation (2)

i2=hfi1+hov2


=hfi1+hoiL.zL ( from Fig3, v2=iLzL)
= hfi1- hoi2.zL ( iL=-i2 from Fig3)
i2 (1+hozL)=hfi1
i2 hf
=> i = 1+ h z
1 o L

i 2 hf
Ai = i1
= 1+ h z
o L

(b) Input impedance (zi): It is defined as the ratio of input voltage (v1)to
input current(i1).
v1
zi =
i1
From equation (1)
v1=hii1+hrv2
=hii1+hr (-i2zL) ( v2= iL z L =-i2zL)
= hii1+hr.i1.AI.zL ( AI =
i 2
i1 )
=i1 (hi + hr A I z L )

V1
zi = = hi + hr A I z L
i1

(c) Voltage gain (AV): It is defined as the ratio of output voltage (v0) to input
voltage(vi).
vo v2 i 2 . z L
AV= v = v = i 1 . zi
i 1
 zL
AV = AI.
zi

(d) Output admittance (yo): It is defined as the ratio of output current (i2) to
output voltage (v2)with input supply voltage v s = 0.
i2
yo =
v 2 v =0
S

From equation (2)

i2=hfi1+hov2

Dividing the equation with v2

i2 hf i 1 h0 v 2
v2
= v2
+ v2

i2 hf i 1
=> v = v2
+ ho ---------------> (3)
2

i1
Now let us find v when vS=0
2

Applying KVL to the input loop with vS=0 of Fig 3

(RS + hi) i1 + hrv2=0

i1 hr
=> v = R +h ------------------> (4)
2 S i

Substitute (4) in (3)

i2 h f hr
= R +h + ho
v 2 v =0S
S i

h f hr
y o = ho -
R S +hi
 (e) Output impedance (zo):

It is defined as the ratio of output voltage (v2)to output

current (i2) with input supply voltage v s = 0.

v2
z0 =
i 2 v =0
S

1
z0 =
yo

v
(f) Overall voltage gain (AvS): - It is defined as the ratio of output voltage )


v
to supply voltage ).

o 2 v v
A vs = v = v
s s

v2 v1
= v . v
1 s

v1
=AV. v -------------------> (5)
s

Considering input circuit of Fig 3

Rs + R1 RS +
v ~s = v 1 Ri
~
v1
- -
Ri
 i R
v1= v s . R + R
i S

v1 Ri
=> v = R + R ----------------------> (6)
s i S

Substituting equation (6) in equation (5)

i R
A v s =AV. R + R
i S

If RS=0, A v s =Av as v s =v1

(g) Overall current gain (AIS): - It is defined as the ratio of output current(iL) to
supply current (is).
Consider input circuit of Fig3 and applying source transformation

i1

iS RS Ri

iL i 2
AIS = i = iS
S

i 2 i1
= . ---------------------> (7)
i1 iS

From the above circuit,

RS
i1=iS. -------------------> (8)
R S + Ri

Substituting (8) in (7)

RS
AIS=AI. R + R
S i
 (h) Power gain (AP): -It is defined as the ratio of output power (P0) to input
power (Pi).
Po i L . vL i 2 v2
AP = Pi
= i1 . v 1
= i1
. v
1

AP=AI.AV

5.5 What is an amplifier?:

An amplifier is a device which strengthens the amplitude of the input

signal and there should not be any change in its shape and frequency.

5.6 Transistor configurations:

1. Common base: Base is common for input and output ports.

Emitter as input & collector as output.

2. Common emitter: Emitter is common for input and output ports.

Base as input & collector as output.

3. Common collector: Collector is common for input and output ports.

Base as input & emitter as output.

5.7 Common emitter amplifier:

v cc
R1 Rc
CC
vo
A CC
RL
RS
R2
RE CE
vS ~
B

Fig 4: Common Emitter amplifier

Description:

For a.c analysis, capacitors are treated as short circuit as they offer
very small resistance i.e.emitter will be connected to ground, so acts common to
input and output.
v cc , R1, R2 and RE forms the self biasing to fix the operating point in
the active region.
CCs are coupling capacitors to block d.c signals from one stage to
next stage so as not to change the operating point of next stages.
CE is a bypass capacitor to provide low reactance path to a.c signals
and hence avoids negative feedback for a.c signals.
 For proper operation of the circuit, polarities of the capacitors must be
connected correctly. The curve bar, which indicates negative terminal
must always be connected to a d,c voltage less than or equal to the d.c
level of positive terminal, straight bar.

Operation:

During the positive half cycle of input, A is positive with respect to B.

Due to this two voltages a.c and d.c will be added, increasing the forward bias of
the emitter-base junction. This increases base current. As collector current is
times base current, ic also increases.

From figure4,
v o = v cc c - i c Rc

So v o decreases.

Therefore, we get a negative half-cycle of output for positive half-cycle

of input.

During the negative half-cycle of input B is positive with respect to A.

So a.c will be subtracted from d.c and net forward bias of emitter-base junction
will be decreased. This decreases the base current and hence collector current.
From figure, we can write
v o = v cc c - i c Rc

So v o increases. Therefore, we get a positive half-cycle of output for negative

half-cycle of input.

The phase difference between

input and output is 180 .
Fig 5: Input and output waveforms of Common Emitter amplifier

5.8. common base amplifier:

C1 C2

RS
RE RC RL vo
vS ~ v EE
v cc

Fig 6: Common Base Amplifier

Description :

Base is grounded so common for both input and output. V cc , v EE , RC and

RE are used to bias the transistor in active region. C1 and C2 are coupling capacitors
used to pass only a.c signals and block d.c signals from one stage to the next stage
to maintain stable operating point.

Operation: During the positive half-cycle of input, a.c is subtracted from

d.c and net forward bias on emitter-base junction will be reduced, so base current
will be reduced and hence collector current will be reduced.

From fig6, v o = v cc c - i c Rc So v o will be increased.

During the negative half-cycle of input a.c is added to d.c as they are in the
same polarity and net forward bias on emitter-base junction will be increased, so
base current will be increased and hence collector current will be increased.

As v o = v cc c - ic Rc , v o will be decreased. Therefore output is in

phase with the input.
 Fig7: Input and output waveforms of Common Base amplifier

5.9 common collector amplifier:

During the a.c analysis d.c supplies must be made 0. i.e. v cc

becomes zero i.e. ground i.e. collector is common.

v cc

R1

C1
C2

R2
v S~ RE RL

Fig 8: Common Collector Amplifier

Description : Vcc, R1, R2, and RE form the biasing for transistor to operate in the
active region. C1 and C2 are coupling capacitors used to couple only a.c signals
from one stage to the next stage.

Operation: During the positive half-cycle of input, net forward bias on emitter-
bias junction will be increased, so base current and hence collector current will be
increased.

From figure8, v o = i e R E i c R E So output will be increased.

During the negative half cycle of input, net forward bias on emitter-base
junction will be decreased, so base current and hence collector current will be
decreased and output also will be decreased. So output is in phase with the input.
 Fig9: Input and output waveforms of Common Base amplifier

5.10 Analysis of transistor using h-parameter model:

Guidelines to draw the equivalent circuit:

1. Replace the BJT by its h-parameter equivalent.

2. Make d.c sources to zero.
3. Replace the capacitors by short circuit.

Analysis problems:

1. Find Ai, Ri , Av, A v s , AIS and Ro for the following circuit. Given h je
=1.1k, hoe=25 A/v, hfe =50 and h =2.510-7

v CC =12 v
RC
1K 1K
0.1f v0
0.1f cc
50=
cc 1.2K

1K
0.1f RL
2K
v ~ 470 Ce

Based on the guidelines draw the equivalent circuit.

B ib C
Equivalent of BJT hie
h v cc +- hoe
hfe i b

E
This is a.c analysis, so v cc =0 =>ground.
So RC should be connected from collector to ground. All capacitors are
short circuited so RL should be connected from collector to ground. Emitter
is directly connected to ground. At the input R1 is connected from base to
ground ( v cc =0=ground) and R2 is connected from base to ground and
v ss in series with RS is also connected from base to ground.

i bB hie C
+ +
1K 1.2K +
RS +_ h v ce
R2 R1 v 1 hfe i b hoev 2 RC RL vo
_
vS ~ _ E _
'
Ri Ri
From the above figure,
Effective load R'L =RC||RL
=1K||1.2K
=545.45
IL h fe
Current gain (AI) = =
I1 1+ hoe R'L
50
=
1+25 106 545.45
= -49.32
Vi '
Input resistance ( Ri ) = Ii
= hie + A I h R L
= 1.1K + (-49.32)(2.510-4)545.45
= 1.093K
V0 R 'L
Voltage gain (AV) = V1
= A I. RS
Ri
545.45
= -49.32 1093 [ ] '
Ri
v s~
=-24.6
'
R = R1||R2||Ri = 1K||2K||1.093K
i

=0.414K
 '
Vo Ri
Overall voltage gain A v S = = AV . '
VS R i+ R S
0.414 K
= -24.6 0.414 K +1 K
= -7.2

Negative sign in AV and A v S indicates 180 phase difference between input

and output.
hfe h
Output admittance y o = hoe -
hie + R's

Where R's =RS||R1||R2 = 1K||1K||2K = 0.4K

50 2.5 104
yo= 25 10-6 -
1100+0.4 K

= 16.67 10-6 A/V

1 1
Output resistance Ro= y0 = = 59.98K
16.67 106

iL iL iC ib
Overall current gain AIS= i = i
ib

iS
S C

RC R S R1 R 2
= R +R (-AI)
RS R1 R2 + Ri
C L

=0.45 (49.32) 0.2679 = 5.946

2. For the common collector configuration, the transistor parameters are

hic=1.2K, hfc =-101, hrc =1 and hoc=25A/V. calculate Ri, Ai, AV, A v s
, Ro for the circuit.
v cc =12 v
R1
10K

CC

RS 1K 10f
R2 o vo
100K 5K
v S~ 20K
The h- parameters equivalent circuit is
i1B hic ie E iL
+
RS
R2 R1
1K
100K
hrc v ec +_ hoc 5K 20K
10K hfc i b
v S~ vo
C _
Ri
'
Ri Ro R'0

iL h fc
Current gain AI= i =
1 1+ hoc R'L

Where R'L = effective load=5K||20K

= 4K
(101)
AI =
1+25 106 4 103

=91.8
Vi
Input resistance Ri = Ii

=hic +AI.hrc. R'L

=1.2K+91.8 1 4K =368.4K
'
V0 R
Voltage gain (AV) = V1
=AI. L
Ri
 4K
= 91.8 368.4 K

=0.996

o o 1 V V V
Overall voltage gain A v s = V = V . V
S 1 S

V1
=AV. V
S

RS
'
+ Ri
v1 A v s =AV. '
v s~ R'i R i+ R S
_
8.87 K
= 0.996 8.87 K +1 K

=0.895

R'i =R1||R2||Ri

=10K||100K||368.4K

=8.87K
h fc hrc
Output admittance (yo) = hoc - R S +hic

(101 ) (1)
=25 10-6 1 k+ 1.2 K

=25 106 - 45909 10-6

A
=-45884 10-6 v

iL ie ib
Overall Current gain (AIS) = i .
ib
. i
e S

5 K RS R1 R2
= 5 K +20 K (-AI). R R R + R
S 1 2 i

= (-0.2) (91.8) (2.439 10-3)

 =0.04478
1
Output resistance (Ro)= y =21.79
o

R'o =Ro||RE = 21.79||5k = 21.69

3. For the common base circuit, the transistor parameters are hib=22, hfb=-
0.98, hob=0.49A/V, hrb =2.9 10-4. Calculate the values of Ri , Ro, AI,
AV, A v s , Ro and R'o .

CC CC

RS RE RC RL
5K 10K 12K
vS ~ vE
v CC

The h-parameters equivalent circuit is

i1 E hie C iL

RS
5K hrb v cb+_ ho bRC RL
1K hfb i e 10K 12K
v S~
B

R
Effective load ) = RC||RL


=10K||12K
=5.45K
iL h fc
(1.) Current gain (AI) = i = '
1 1+ hob R L
(0.98 )
= 6 3
1+0.49 10 5.45 10
=0.977
 R Vi
(2.) Input resistance )= = hib +AI.hrb. R'L
Ii

= 22+0.977 2.9 10-4 5.45 103
=23.544
'
V0 R
(3.) Voltage gain (AV) = V1
=AI. L
Ri

5.45 K
= 0.977 23.544

=226

o o 1 V V V
Overall voltage gain (A v s ) = A v s = V = V . V
S 1 S

RS V1
=AV. V
+ S
v1 '
vs Ri
~ R'i
_
A vs =AV. '
R i+ R S

Ri = R1||RE = 23.54||5K
'

= 23.42
23.42
A v s =226 23.42+1 K

=5.17

fb rb h h
Output admittance ( y o ) = hob - R +h
S ib

0.98 2.9 104

=0.4910 -6 -
1 K + 22

=0.768 ( )
1 1
Output resistance Ro= y = 0.768 = 1.3M
o

'
R0 =Ro||RC = 1.3M||10k= 9.923k
 iL iL iC ie
Overall current gain (AIS) = i = i . i . i
S C e S

iL RC 10 K
= = 10 K +12 K = -0.45
iC R C+ R L

iC
ie
=-AI=-0.977

ie RS R E 1 K 5 K
= = 1 K5 K +23.54
iS R S R E + Ri

0.833 K
= 0.833 K +23.54

=0.9725
A IS = (-0.45) (-0.977) (0.9725)

= 0.4725

5.11 Comparison of CB, CE, and CC amplifiers:

S.No Parameter Common base Common emitter Common collector

1. Input Resistance Low High Very high
2. Output Resistance Very high Moderate Low
3. Voltage gain High High Low
4. Current gain Low High High
5. Power gain Moderate Very High Moderate
5.12 Frequency response of an amplifier:

The performance of an amplifier can be judged by its frequency response

curve. This curve describes the amount of gain offered by the amplifier for various
frequencies. Frequency is taken on x-axis and gain is taken on y-axis. Logarithmic
scale is taken for frequencies to cover maximum range, so gain should be
converted to decibels as follows.

AV = 20 log 10 A V , AI = log 10 A I

and AP = log 10 A P

Typical frequency response curve is

A V ( db )
 A Vmax
A Vmax
2

0 f
fL B.W fH
Fig 10: Frequency response
of an amplifier
AV is maximum voltage gain of the amplifier fL and fH are lower and upper
max

cutoff frequencies respectively.

1
Cutoff frequency is defined as the frequency at which gain is times the
2
maximum gain.

Bandwidth is defined as the range of frequencies over which gain is greater than
1
or equal to times the maximum gain.
2
Bandwidth= f H - f L

5.13 Frequency response of common emitter amplifier:

v CC
3.3K R1 RC
1.2K CC
vo
CC
10f
1K 10f RL
RS 100f 1K
R2
vs 6.8K Ce
~ 1K
1mv

Fig 11: A typical Common Emitter Amplifier

 If we connect the circuit as shown above and take the output for various
Vo
input frequencies and then compute gain in dB as 20 log( V ) . S
10

S.NO f VO Vo
20 log( V )
S
10

1
2
.
.
.
.

Now if we plot frequencies Vs gain, it will be like this.

gain

0 f

Fig 12: Typical frequency of an amplifier

From the plot, we can say that gain at low frequencies is increasing, gain at high
frequencies is decreasing and gain at mid frequencies is constant as frequency is
increasing. The reasons for gain fall at low and high frequencies is as follows.

Reasons to get low gain at low frequencies:

1
1. Coupling capacitors: We know that XC = 2 f . At low frequencies,
C

coupling capacitors offer very large reactance, which results in maximum

drop across coupling capacitor and in turn reduces the amount of coupling
from one stage to the next stage. So final output decreases and hence gain
 decreases. As frequency is increasing, capacitive reactance decreases, drop
decreases, coupling increases, v o increases and hence gain increases.
2. Bypass capacitors: At low frequencies, bypass capacitors also offer high
reactance and cannot stop negative feedback offered by Re.
As frequency is increasing, XC decreases, and bypasses the feedback signals
and hence gain increases.

Practically the value of bypass capacitors is very high so the effect of bypass
capacitor is low compared to coupling capacitor.

Reasons to get low gain at high frequencies:

1. : As frequency is increasing, decreases so output voltage and hence gain

decreases.
2. Shunt capacitors:

Emitter, Base and collector are conducting materials separated by

forbidden gap, which acts like dielectric and hence behave like capacitors called
shunt capacitors.

E B C C

B
E

3. Stray capacitors: When two conducting wires separated by air then it

results in capacitance, called stray capacitance.

RS
~ vS
Ri
C Stray

At high frequencies, capacitive reactance ( X C ) will be small and most of

stray

the signal will be passed through c stray compared to input of the amplifier and
hence gain decreases.
Corollary: For common base and common collector amplifiers coupling
capacitors cause diminished gain at low frequencies and , shunt capacitances &
stray capacitances cause diminished gain at high frequencies.

5.14. FET amplifiers: From the operation of FETs studied in second unit, we
know 2 d.c supplies v gs and Vds are required. So current is due to both v gs and
v ds . From the super position theorem,

a) id due to voltage source v gs is

i d =g m V gs
1

Where gm is transconductance.
b) id due to voltage source v ds is
V ds
id =
2
rd
V ds
id = i d +i d = gm V gs + --------------> (9)
1 2
rd
Constructing the equation (9) as a 2 port network results in small signal
model of FET as shown below.

g d
+ v ds r +
v gs gm v gs d v ds
rd
- _
s

Fig 13: Small signal model of FET

5.15. Analysis of common source FET amplifier using small signal model:

(a) Fixed bias: -

v DD

cc
)| R D cc

RG v0
vi
v gs
 Fig 14: FET amplifier with fixed bias

To draw the a.c equivalent circuit

(i.) FET should be replaced by small signal model

(ii.) Capacitors should be short circuited.
(iii.) d.c sources should be made zeros.

So a.c equivalent circuit is

I1 G id D
+
vi ~ RG gm v gs rd RD
v gs v0
_ S

zi Z0 Z0
'

Fig 15: AC equivalent of FET amplifier with fixed bias

Vi
(i) Input impedance ( z i ) = Ii
= RG

(ii)Output impedance ( z o ) = r d

and z 'o = rd||RD

(iii) Voltage gain

v o = - id R D

Applying KVL to output loop

id R D + r d (id - gm v gs ) = 0

g m V gs r d gm V gs r d
=>id = rd + R D
= vo = rd + R D
RD
 Vo gm R D r d
AV= V = rd+ R D
gs

Self-bias:
v DD

RD
c2
c1 v0
vi

RG
RS cS

Fig 16: FET amplifier with self bias

a.c equivalent circuit is

v0
+
vi RG v gs gm v gs rd RD

Zi z0 z '0

Fig 17: AC equivalent of FET amplifier with self bias

Input impedance ( z i ) = RG
 Output impedance ( z o ) =rd

and z 'o =RD||rd

gm R D r d
Voltage gain= rd+ R D
= g m rd||RD)

(b) Self bias with un bypassed RS:

v DD

RD
v0
vi
c1
RG
RS

Fig 18: FET amplifier with self bias and un bypassed Rs

a.c equivalent circuit is

S
o
i dD
G +
v gs gm v gs rd RD

vi RG - v0

RS
 Zi z0 '
z0

Fig 19: AC equivalent of FET amplifier with self bias and un bypassed Rs

Input impedance ( z i ) = RG
V o
Output impedance ( z o ) = i V =0 i
0

Applying KVLs at output and input

v o = (id- gm v gs rd + i d R S ----------------> (10)
v i = v gs + i d R S => 0= v gs + i d R S
=> v gs = - i d R S ----------------> (11)
Substituting (11) in (10)
v o = [ i d g m ( i d R S ) ] rd + i d R S
=id [ r d + g m R S r d + R S ]
Vo
zo = id
= rd + RS+ gm R S r d
'
z o =zo||RD.
Vo
Voltage gain (AV) = Vi
Applying KVL vo = id.RD -------------> (12)
idRD+(id- gm Vgs)rd+idRS=0
idRD+ [ i d g m ( V ii d RS ) ] rd+idRS=0
g m vi rd
id= R +r + g R r + R
D d m S d S
g m vi rd
id= R +r + R + R

D d S S
gm vi r d R D
vo=-idRD= ( = gm r d
R D +r d + R S ( 1+ )
vo g m r d R D
AV = vi
=
R D +r d + R S ( 1+ )

Note: - With un bypassed RS gain will be reduced due to negative feedback

provided by RS.
5.16. Common drain amplifier: -

v DD

vi

RG v0
c2
RS

Fig 20: FET Common drain amplifier

a.c equivalent circuit is

vi G D
+

v gs gm v gs rd

_ S
RG
o v0
RS

R0
Ri
Fig 21: AC equivalent of FET Common drain amplifier

Input Resistance (Ri)= RG

Vo
Output resistance Ro=
i o V =0
i

a.c equivalent circuit is

G S v0
+ id
RG gm v gs rd RS
vi
i dg m v S
_ D
id
Ri R0 '
R0

Fig 22: Modified AC equivalent of FET Common drain amplifier

Applying KVL to outer loop

-Vi +Vgs +Vo=0

Condition for Ro is vi=0 so

-O+Vgs+vo=0 => Vgs=-vo---------------> (13)

From the circuit,

vo=idRS=-(id-gmVgs)rd

=-(id+gmvo)rd ( from (13))

vo(1+gmrd) = - idrd
vo r d
id
= 1+ g r
m d
 r d
=
1+

V o r d
As 1 Ro= i V =0 =
d
i

r d 1
= 1+ g r = - g
m d m

' 1
Ro =Ro || RS =
g m ||RS

vo
Voltage gain (AV) = vi

vo=idRS -------------------> (14)

Applying KVL to output loop

idRS+(id-gmVgs)rd=0 -----------------> (15)

Applying KVL for outer loop

-vi+Vgs+ idRS=0

=>Vgs= vi- idRS---------------> (16)

Substituting (16) in (15)

idRS+(id-gm(vi- idRS))rd=0

id(RS+rd+gmrdRS)=gmvird
vi
=>id= R +r + R ----------------> (17)
S d S

Substituting (17) in (14)

vi
vo= R +r + R .RS
S d S

vo RS
AV= vi
= R +r + R
S d S
As rdRS(1+)
RS
AV= R (1+ ) = 1+
S

Note 1: CD amplifiers voltage gain is slightly less than unity.

Note 2: Positive sign of AV indicates 0 phase shift between input and output.

5.17. Common gate amplifier: -

c1 S D c2

RS RD
vi v0

v DD

Fig 23: Common gate amplifier

Equivalent circuit

i+
r
gm v dgs
S i id D
+ +

vi RS gm v gs
v0
RD

G _
-

Z 'i Zi

Fig 24: AC equivalent of FET Common gate amplifier

 vi
Input impedance (zi) =
i

From figure 24,

Current flowing through rd(Ird)=i+gmVgs

=> i = ird- gmVgs

v iiR D
= rd
- gmVgs

=
v iiR D
- gm(-vi)
( Vgs=-vi)
rd

R vi
i= 1+ r(D

d
) = r + gmvi = vi
d
( r1 +g )
d
m

RD
1+
vi rd rd + R D
=> zi= = =
i 1 1+ gm r d
+g
rd m

z 'i =zi||RS

Vo
Output impedance (zo) =
i o V =0 i

i.e impedance seen from output port when input port is short circuited.

zo=rd||RD
Vo
Voltage gain (AV) = Vi

vo= -iDRD

vi=-Vgs

Applying KVL to outer loop

-vi+(i+gmVgs)rd+iRD=0

As Vgs=-vi, we get
-vi+(i-gmvi)rd+iRD=0

=> i(rD+RD)=vi(1+gmrd)
v i (1+ gm r d )
=> i= rd + R D

v i R D (1+ g m r d )
=> vo= iRD= r d + RD

vo R D ( 1+ g m r d )
=> AV= v = rd + R D
i

5.18. Gain bandwidth product (GBWP):

This quantity allows circuit designers to determine the maximum gain that can be
extracted from the device for a given frequency and vice-versa.

IF GBWP of an amplifier is 10KHz, it means that the gain of the device falls
to unity at 10KHz.

GBWP is constant for a given amplifier. That is even we add some more
circuitry to increase (or decrease) gain then bandwidth will be decreased (or
increased) and GBWP is constant.

For transistors, the current gain bandwidth product is known as fT or transition

frequency. It is calculated from the low frequency current gain under specified test
conditions.