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LM2757
SNVS536F OCTOBER 2007 REVISED JULY 2015
Typical Application
VOUT = 4.1 V (100 mA), 4.5 V (110 mA)
VIN = 3 V - 5.5 V
5 V (180 mA)
VIN VOUT
B2,B3 A2
C1+
CIN 1 F A3 1 F COUT
C1
0.47 F
B1
C1- LM2757
C2+
A1
M0
C2 D3
0.47 F M1
C3 D2
C2- GND
C1,C2
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM2757
SNVS536F OCTOBER 2007 REVISED JULY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 11
2 Applications ........................................................... 1 9 Application and Implementation ........................ 13
3 Description ............................................................. 1 9.1 Application Information............................................ 13
4 Revision History..................................................... 2 9.2 Typical Application ................................................. 13
5 Device Options....................................................... 3 10 Power Supply Recommendations ..................... 18
6 Pin Configuration and Functions ......................... 3 11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
7 Specifications......................................................... 4
11.2 Layout Example .................................................... 19
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4 12 Device and Documentation Support ................. 20
7.3 Recommended Operating Conditions....................... 4 12.1 Device Support .................................................... 20
7.4 Thermal Information .................................................. 4 12.2 Documentation Support ........................................ 20
7.5 Electrical Characteristics........................................... 5 12.3 Community Resources.......................................... 20
7.6 Typical Characteristics .............................................. 6 12.4 Trademarks ........................................................... 20
12.5 Electrostatic Discharge Caution ............................ 20
8 Detailed Description ............................................ 10
12.6 Glossary ................................................................ 20
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10 13 Mechanical, Packaging, and Orderable
8.3 Feature Description................................................. 10
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Added Device Information and Pin Configuration and Functions sections, ESD Rating table, Feature Description,
Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and
Documentation Support , and Mechanical, Packaging, and Orderable Information sections. ............................................... 1
5 Device Options
YFQ Package
12-Pin DSBGA
Top View (left); Bottom View (right)
A1 A2 A3 A3 A2 A1
B1 B2 B3 B3 B2 B1
C1 C2 C3 C3 C2 C1
D1 D2 D3 D3 D2 D1
Pin Functions
PIN
TYPE DESCRIPTION
NUMBER NAME
A1 C2+ Power Flying Capacitor C2 Connection
A2 VOUT Power Regulated Output Voltage
A3 C1+ Power Flying Capacitor C1 Connection
B1 C1 Power Flying Capacitor C1 Connection
B2 VIN Power Input Voltage Connection
B3 VIN Power Input Voltage Connection
C1 GND Ground Ground Connection
C2 GND Ground Ground Connection
C3 C2 Ground Flying Capacitor C2 Connection
D1 NC NC No Connect Do not connect this pin to any node, voltage or GND. Must be left floating.
D2 M1 Logic input Mode select pin 1
D3 M0 Logic input Mode select pin 0
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN MAX UNIT
VIN pin: voltage to GND 0.3 6 V
M0, M1 pins: voltage to GND 0.3 6 V
Continuous power dissipation (4) Internally Limited
Junction temperature, TJ-MAX 150 C
Maximum lead temperature (soldering, 10 sec.) 265 C
Storage temperature, Tstg 65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) All voltages are with respect to the potential at the GND pins.
(4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 145C (typical) and
disengages at TJ = 135C (typical).
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pins.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJMAX-OP =
125C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (RJA), as given by the following equation: TA-MAX = TJ-MAX-OP (RJA PD-MAX).
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) All voltages are with respect to the potential at the GND pins.
(2) Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm.
(3) CIN, COUT, C1, C2: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(4) There is a 450-k (typical) pulldown resistor connected internally to each logic input.
(5) Turnon time is measured from when the M0 or M1 signal is pulled high until the output voltage crosses 90% of its final value.
Copyright 20072015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM2757
LM2757
SNVS536F OCTOBER 2007 REVISED JULY 2015 www.ti.com
Figure 1. Efficiency vs. Input Voltage Figure 2. Efficiency vs. Input Voltage
Figure 3. Efficiency vs. Input Voltage Figure 4. Output Voltage vs. Output Current
Figure 5. Output Voltage vs. Output Current Figure 6. Output Voltage vs. Output Current
Figure 7. Output Voltage Ripple vs. Output Current Figure 8. Output Voltage vs. Input Voltage
Figure 9. Output Voltage vs. Input Voltage Figure 10. Output Voltage vs. Input Voltage
Figure 11. Output Leakage Current, Device Shutdown Figure 12. Output Leakage Current, Device Shutdown
Figure 13. Current Limit vs. Input Voltage Figure 14. Oscillator Frequency vs. Input Voltage
Figure 15. Operating Current vs. Input Voltage Figure 16. Shutdown Supply Current vs. Input Voltage
VIN = 3.6 V Load = 200 mA Time scale: 100 s/Div VOUT = 5-V Mode Load = 200 mA Time scale: 100 s/Div
CH2: VOUT; Scale: 1V/Div, DC Coupled CH1: VIN; Scale: 1V/Div, DC Coupled
CH4: IIN; Scale: 200 mA/Div, DC Coupled CH2: VOUT; Scale: 100mV/Div, AC Coupled
Figure 17. Start-up Behavior, 5-V Mode Figure 18. Line Step, 3.5 V to 4 V
VOUT = 5-V Mode VBATT = 4 V Time scale: 10 s/Div VOUT = 5-V Mode VBATT = 4 V Time scale: 10 s/Div
CH1: VOUT; Scale: 50mV/Div, AC Coupled CH1: VOUT; Scale: 50mV/Div, AC Coupled
CH4: IOUT; Scale: 100mA/Div, DC Coupled CH4: IOUT; Scale: 100mA/Div, DC Coupled
Figure 19. Load Step With Li-Ion Battery, 10 mA to 200 mA Figure 20. Load Step With Li-Ion Battery 200 mA to 10 mA
8 Detailed Description
8.1 Overview
The LM2757 is a switched capacitor converter that produces a regulated output voltage of either 5 V, 4.5 V or
4.1 V, depending on the mode selected. The core of the part is a highly efficient charge pump that utilizes fixed
frequency pre-regulation to minimize ripple and power losses over wide input voltage and output current ranges.
A description of the principal operational characteristics of the LM2757 is shown in the Functional Block Diagram
and detailed in Feature Description.
VIN
C1+
G= 2, 2
3 C2+
C2-
VOUT
OSCILLATOR
SHORT-
CIRCUIT
EN
PROTECTION
THERMAL
SHUTDOWN
M0
VOLTAGE MODE
SELECT AND 1.24 V Soft-Start
M1 ENABLE CONTROL Ref. Ramp GND
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Capacitors with a Y5V or Z5U temperature characteristic are generally not recommended for use with the
LM2757. These types of capacitors typically have wide capacitance tolerance (80%, 20%) and vary significantly
over temperature (Y5V: +22%, 82% over 30C to +85C range; Z5U: 22%, 56% over a 10C to 85C range).
Under some conditions, a 1-F-rated Y5V or Z5U capacitor could have a capacitance as low as 0.1 F. Such
detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum capacitance
requirements of the LM2757.
Net capacitance of a ceramic capacitor decreases with increased DC bias. This degradation can result in lower
capacitance than expected on the input and/or output, resulting in higher ripple voltages and currents. Using
capacitors at DC bias voltages significantly below the capacitor voltage rating usually minimizes DC bias effects.
Consult capacitor manufacturers for information on capacitor DC bias characteristics.
Capacitance characteristics can vary quite dramatically with different application conditions, capacitor types, and
capacitor manufacturers. It is strongly recommended that the LM2757 circuit be thoroughly evaluated early in the
design-in process with the mass-production capacitors of choice. This helps ensure that any such variability in
capacitance does not negatively impact circuit performance.
The voltage rating of the output capacitor should be 10 V or more. For example, a 10-V 0603 1-F capacitor is
acceptable for use with the LM2757, as long as the capacitance does not fall below a minimum of 0.5 F in the
intended application. All other capacitors should have a voltage rating at or above the maximum input voltage of
the application. The capacitors should be selected such that the capacitance on the input does not fall below 0.7
F, and the capacitance of the flying capacitors does not fall below 0.2 F.
Table 3 lists some leading ceramic capacitor manufacturers.
Much like the relationship between the output capacitance and output voltage ripple, input capacitance has a
dominant and first-order effect on input ripple magnitude. Increasing (decreasing) the input capacitance results in
a proportional decrease (increase) in input voltage ripple. Input voltage, output current, and flying capacitance
also affects input ripple levels to some degree.
In typical high-current applications, a 1-F low-ESR ceramic capacitor is recommended on the input. Different
input capacitance values can be used to reduce ripple, shrink the solution size, and/or cut the cost of the
solution. But changing the input capacitor may also require changing the flying capacitor and/or output capacitor
to maintain good overall circuit performance. Performance of the LM2757 with different capacitor setups is
discussed in Recommended Capacitance.
(1) Refer to the text in Recommended Capacitance for detailed information on the data in this table.
Figure 22. Efficiency vs. Input Voltage Figure 23. Efficiency vs. Input Voltage
4.1-V Mode
LM2757 (Host
Mode VBUS
EN (VM1)
Power)
USB Connector
VM0
VOUT / VBUS (5V)
VBUS
Dual Role
ID
Application
Processor D+
D-
USB OTG
GND
Transceiver
VBAT VOUT = 5V
Flash
LM2757 LED(s)
Supercapacitor 2.7 k:
Charge (M1) Flash Charger
R R
M0
2.7 k:
LM2757
LED(s) D1 DX
M0 LED
M1
Driver
R R
11 Layout
VOUT 1 PF
C1+
M1 M0
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 5-Jul-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM2757TM/NOPB ACTIVE DSBGA YFQ 12 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -30 to 85 DL
& no Sb/Br)
LM2757TMX/NOPB ACTIVE DSBGA YFQ 12 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -30 to 85 DL
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 5-Jul-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Jul-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Jul-2015
Pack Materials-Page 2
MECHANICAL DATA
YFQ0012xxx
D
0.600
0.075
TMD12XXX (Rev B)
4215079/A 12/12
NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
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