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PCB
Fixture
ICT TESTER
ICT FT
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ICT5
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Agilent ICT Tester
Agilent 307x Series 3 Architecture
Testhead Layout
BRC:Bank,Row,Column :20378,203178
Configuring a Four-Module System
Cards
HybridPlus Pin Card ASRU - Rev A,B or C
Double Density Hybrid Control
ChannelPlus Pin Card ControlPlus
AccessPlus Pin card ControlXT
Analog Pin Card
Double Density Analog Pin Card
Serial Test Pin Card
System config file
PATH:/hp3070/diagnostic/th1/config
testhead name "testhead1"
line frequency 50
relay 1 controls vacuum 2,3
relay 2 controls vacuum 0,1
bank 1
module 0
cards 1 asru
cards 2 hybrid advanced ! double density
cards 3 hybrid advanced ! double density
cards 4 hybrid advanced ! double density
cards 5 hybrid advanced ! double density
cards 6 control plus
cards 7 hybrid advanced ! double density
cards 8 hybrid advanced ! double density
cards 9 hybrid advanced ! double density
cards 10 hybrid advanced ! double density
cards 11 hybrid advanced ! double density
supplies hp6624 13 to 16 ! asru channels 1 to 4
ports ext7, ext8
end module
module 1
.
End module
end bank
bank 2
end bank
Board level config file
module 2
cards 1 asru c revision
cards 2 hybrid standard double density
cards 3 hybrid standard double density
cards 4 hybrid standard double density
cards 5 hybrid standard double density
cards 6 control plus
cards 7 hybrid standard double density
!@ cards 8 hybrid standard double density
!@ cards 9 hybrid standard double density
!@ cards 10 hybrid standard double density
!@ cards 11 hybrid standard double density
supplies 5 to 8
end module
module 3
cards 1 asru c revision
!@ cards 2 hybrid standard double density
!@ cards 3 hybrid standard double density
!@ cards 4 hybrid standard double density
!@ cards 5 hybrid standard double density
cards 6 control plus
cards 7 hybrid standard double density
cards 8 hybrid standard double density
cards 9 hybrid standard double density
cards 10 hybrid standard double density
cards 11 hybrid standard double density
supplies 1 to 4
end module
Short Wire Fixture Architecture
Command control testhead
Testhead power on
fix lock, fix unlock-----compressed air
faon,faoff ------Vacuum
vacuum well is
faon fbon
Windows NT Fixture
GenRad RECEIVER
MXI Bus
DSM BOARD
AFTM CARD
IEE-488
REFERENCE
PIN CARD
PIN CARD
PIN CARD
PIN CARD
RST
C/S/T
MTG
ICA
0 1 3 3 4 5 6 31 32 33 34
UUT PS
PIN BAY
MXI to GenRad board
MTG Functional blocks are MXI to GR businterface
Clock/synchronus/trigger board
CST Privides event timing and event detection
Driver/Sensor reference
Reference Supplies programmed dc reference voltages for the D/S pin
boards
Solectron Confidential
TESTPLAN
Sub Pre_Shorts
call Pre_shorts
Subend
call Shorts Sub Shorts
. Test shorts
Call Analog_tests Subend
Sub Analog_Tests
Call testjet Test analog/c4
Test analog/r56
Call digital
subend
Sub Characterize Sub Digital_Tests
learn capacitance on Test digital/u1
learn capacitance off Test digital/u2
subend
subend
Typical Example of Analog Test
disconnect all
connect s to N1
Resistor typical test program: connect I to N2
connect g to N100
resistor 10k, 5.5,5,re5,ar0.1
1. S bus 4. A bus
2. I bus 5. B bus
3. G bus 6. L bus
enhancement
Capacitor Test
! Declaration Section
! Device Type
! assignment section
! Timing Section
Details are covered
in Advanced Digital
Class
! Vector Definition Section
Vector Initial_State
set Reset to 0
set CS_bar to 0
...
! Vector Execution section
unit Test Reset
execute Initial_State
execute Assert_reset
.
1 Input 1 Input2 Output
3
2
E1 0 0 1
4
6 E1 0 1 1
5
E1 1 0 1
9
8 E1 1 1 0
10
12
13
11 Truth Table
NAND GATE
Digital library (Declaration Section)
! 7400
! NAND, 2-Input, Quad
! revision A.01.00
combinatorial
vector cycle 500n
receive delay 400n
assign VCC to pins 14
assign GND to pins 7
family TTL
inputs E1_Inputs,E2_Inputs,E3_Inputs,E4_Inputs
outputs E1_Output,E2_Output,E3_Output,E4_Output
Digital library test (Vector Definition Section)
vector E1_Input_00 vector E4_Input_00
set E1_Inputs to "00" set E4_Inputs to "00"
set E1_Output to "1" set E4_Output to "1"
end vector end vector
Vector E1_Input_11
A set A to 1
C
set B to 1
B
set C to 0
end vector
VCC
PATH:/hp3070/standard/safeguard/standard_cmos
include "standard_cmos"
S A F E G U A R D S U M M A R Y
--------------------------------
safeguard status :Not Inhibited
Estimated test time:3.60e-05
Safe Test time(device):5.99e-01(u16)
cs
Upsteam UUT1
device U1
U21
Input
UUT2 output
U2
Disable description in library
! QMV288 U21 Library
! setup only
! revision A.01.00
family TTL
power VCC,GND
inputs CS
bidirectional IO
disable IO with CS to "0"
Disable in execute test
!U2 executable test
assign Disablegroup to nodes "TREE__1343 default "0"
inputs Disablegroup
The node TREE__1343(U21 Pin CS) keep at low level during U2 Test
Analog Functional Resource
s :Source
a:auxiliary source
i: detector high
l: detector low
rcva,rcvb,rcvc:frequency detector
Resource specification
Source range unit
------------------------------------------------------------
DCV -10 - +10 Vdc
SINE 0 - 7.0 Vrms
SQUARE 0 - 10 Vpk
TRIANGLE 0 - 10 Vpk
subtest "TRANSLATOR1_2"
......
end subtest
Frequency Test
end test
subtest"OUTPUT"
end subtest
How Testjet do?
Remark:The S (source) bus to the pin being tested,the I (input) bus to the HP TestJet probe,and the
G(guard) bus to all other pins on the device.
The "testjet" File
The "testjet" file is the test file for all devices to be tested with HP TestJet; this
one test file includes the tests for all HP TestJet devices.
default threshold low 200 high 10000
default throughput adjustment 1!throughput adjustment 0
device "u101;threshold low100 high 10000
test pins 1
test pins 2,3
test pins 4,5,6
! test pins 7 ! Ground pins commented by HP IPG.
test pins 8
test pins 11;threshold low 20 high 10000
test pins 12
test pins 13
! test pins 14 ! Fixed pins commented by HP IPG.
inaccessible pins 9,10
end device
The "default threshold" statement sets the test thresholds for all the devices in the file.
The "default throughput adjustment" statement enables or disables throughput
adjustment for all the devices in the file.
There is a "device/end device" block for each device to be tested. The "device" statement
specifies the device designator. If the device is mounted on the bottom side of the board,
the "device statement includes the "bottom" keyword.
The "test pins" statement specifies the pin or pins to be tested. Pins that are tied together in
the circuit are specified and are tested together.
The "inaccessible pins" statement declares pins that are not tested because they are not
accessible.This statement always appears at the end of the device block.
Testjet Probe Assemble
Testjet Probe Assemble
HP TestJet Probe and Mux Card Connections.
Pin Numbers for the Right-Angle Connector.
A Shorts Test is testing for unexpected shorts on the board; it requires the
impedance between nodes to be greater than the threshold (open) to give a
PASS indication.
short A to D
source
S
A
B
C
detector
D
D
Shorts test
3.isolation
1.Check node A
find short
Phantom shorts
report netlist
report netlist, common devices
report common devices
report common devices, netlist
report phantoms
report limit <# of nodes>
ICT Fixture Software Develop Process
HP3070
SOFTWARE
Fixture File &
Test program
FABMASTER GENRAD
CAD File SOFTWARE
TAKAYA
Test program
GC-PLACE
Gerber File
TEST DEVELOPMENT PROCESS
First : Gather the materials
(Schem.,BOM,CAD,Datasheet,loaded board)
Second: Describe the board to the HP 3070.(Fabmaster,board
consultant)
Third : Let the HP 3070 generate tests and fixture files(IPG).
Third: Evaluate the files the HP 3070 generated.Is the test
sufficient? Are there details omitted? Should changes
be made and the Test Generation process be re-run?
Fourth: Build a fixture
Fifth : Turn on each test.Are there tests that require debug? If
so,debug those tests.
Sixth : Release test to production.
Seventh: Perform an ECO(Engineering Change Order)as needed.
Gathering
Materials
The Materials
Schematic Diagram
CAD Data(contain x-y information,netlist)
BOM
Part Datasheet
Blank PC board
Loaded PC board(known good)
knowledge of Board Test Consideration
Describing the PC board to the System
What does the HP 3070 software need and what
tools are available?
The software needs a description of the testhead hardware.
For the HP 3070 software to accomplish this,it needs a clear,concise
clear,concise
picture of the PC board.This includes the physical characteristics
characteristics of
the board,the locations of the components on the board,the locations
locations of
vias and testpads.It
testpads.It also needs the value of the analog parts on the
board and the tolerance of each device.The generic part number of
of the
digital devices on the board is also needed.Given this information,the
information,the
HP 3070 will create tests for the analog devices and use libraries
libraries of
tests for the digital devices.
For the testhead configuration,you will use BT-
BT-BASIC editor to create
the config
configfile.This describes the testhead hardware to be used when
creating the fixture and test files for this board.
HP Board Consultant
mandatory
This forces the system software to locate the probe at the specified location.
preferred
This marks the specified location as the one you would like to see probed if there
are no other considerations that would prevent this location from being used.
unreliable
This marks the location as one to use but only if no others are available.
no_access
This flags the given location as being one that cannot be probed.
no_probe
This tells the software that the associated location is prohibited from being a valid
probe location.
Inputs Running IPG Outputs
board.o pins file
analog directory
board_xy
board_xy.o
.o
digital directory
Config.o
Config.o testorder file
ipg/summary
ipg/summary file
ipg/details
ipg/details file
ipg/dependencies.o
ipg/dependencies.o
Final Compile/Verify & Generate Testability Report
Save Files
Compile Files
Generate a testability.rpt
wirestop.p drillsup
drilltop
wires.p
fixture.o
wires Fixture
inserts
trace
probes.p
testjet_mux
summary probesyop.p
Explanation of all fixtures files
details file
The Details Report contains all the information provided by the Summary
Report with detailed explanations. When the Fixture Generation Software is
run in incremental mode (for ECOs) the Details Reports also contains
information about wiring that needs to be added or deleted from the existing
fixture.
drill file
The drill files contain drill tool and X-Y coordinate information for the probe
plate . The information is in a common format for numerically controlled
machines.
drillsup file
Drilling information for the support plate.
drilltop file
Drilling information for the top probe plate.
fixture.o file
The placement is specified in the fixture.o file, and includes the board outline
coordinates, tooling pin hole and locations, board placement specifications,
fixture part number, and fixture options.
insert file
The Fixture Inserts Report contains information for inserting pins, receptacles,
and probes.
Revolutionizing PCB
Testing
WHY
Boundary Scan
PCB Testing is Challenging
High Density
Device
Complexity
SMD
BGA
MCM
Multi-Layer
A Boundary Scan
Device
IEEE 1149.1
Architecture
Engineers turn to technologies like boundary scan
which dont need physical access to perform design
debug, manufacturing and field test, as well as in-
system configuration for programmable devices.
15
10
0
1999 2000 2001 2002 2003
The total U.S. demand for printed circuit boards,
estimated at $9.194 billion in 1998, is projected to
increase at an annual average growth rate of 7.2% to
reach $13 billion in 2003.
Source: BUSINESS COMMUNICATIONS CO., INC.,
The Market -Continue
300
250
200
150
100
50
0
2001 2002 2003 2004
HOW
Boundary Scan
Introduction to Boundary-
IEEE StandardScan
1149.1-1990
Background
Current in-circuit and functional testing techniques are becoming less effective because of node access
problems and the inability of testers to cover all nodes. Conventional techniques are becoming less
efficient because test development requires longer time investments; time-to-market lengthens and test
costs increase.
These problems were viewed with such a concern that, in 1985, several European companies formed a
group called JETAG (Joint European Test Action Group). Later several American companies joined this
group, which was renamed JTAG (Joint Test Action Group). JTAG conceived the boundary-scan technique
to address these problems; it was finally documented in the JTAG Rev 2.0 proposal in 1988.
A proposal to develop this technique was handed off to the Institute of Electrical and Electronics
Engineers (IEEE) and was refined by the IEEE working group. During 1989, IEEE P1149.1 went out to
ballot, and in early 1990 it became IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and
Boundary-Scan Architecture. The standard defines how to design testability features into digital devices,
which will simplify testing. These features can be used in device testing, incoming inspection, board test,
system test, and field maintenance and repair.
What is Boundary-Scan?
Boundary-Scan is a test technique that involves devices designed with shift registers placed between
each device pin and the internal logic as shown in Figure 1. Each shift register is called a cell. These cells
allow you to control and observe what happens at each input and output pin. When these cells are
connected together, they form a data register chain, called the Boundary Register.
Boundary-Scan devices have a dedicated port, called the Test Access Port (TAP), that routes input
signals to a controller, called the TAP Controller.
Test Data In (TDI) the serial input for test data and instruction bits
Test Data Out (TDO) the serial output for test data
Test Clock (TCK) an independent clock used to drive the device
Test Mode Select (TMS) provides the logic levels needed to
change the TAP Controller from state to state
Test Reset (TRST*) an optional input signal used to reset the
device (the * indicates that this is an active-low input signal)
The Manufacturing Fault Spectrum and Boundary-
Scan Boundary-Scan addresses the fault spectrum by providing a variety of test options that focus on
each of the failures mentioned. For example, the mandatory EXTEST provides excellent fault coverage,
which addresses opens, shorts, missing or wrong components, and dead ICs. The optional RUNBIST
instruction checks the internal logic of a device and provides fault coverage for missing or wrong
components, dead ICs, and fixture problems. IDCODE checks for wrong devices mounted on the board.
Boundary-Scan In the Circuit (1)
Boundary-Scan In the Circuit
(2)
Boundary-Scan In the Circuit (3)
Boundary-Scan In the Circuit (3)
Moving Through the TAP Controller State
Diagram
IEEE BSDL
Boundary-Scan Description Language (BSDL) is the standard description language for boundary scan
devices complying with IEEE Standard 1149.1-1990. It is intended to be used by test developers, device
manufacturers, ASIC designers and foundries, and ATE manufacturers to promote consistency
throughout the industry. It is also intended to specify those characteristics necessarily unique to a given
boundary-scan device.
In September of 1994 IEEE Standard 1149.1b-1994 was released and with it the potential for there
being devices compliant with IEEE 1149.1 and 1149.1b existing on the same board.