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CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2011-01-24
SCHEM,RIO,D2
PIB2B, 03/16/2012
D 820-3071-10.brd D
m
Page
TABLE_TABLEOFCONTENTS_HEAD
(.csa)
1
Contents Sync Date
MASTER
1
o
Table of Contents MASTER
TABLE_TABLEOFCONTENTS_ITEM
2 MASTER
2 System Block Diagram MASTER
TABLE_TABLEOFCONTENTS_ITEM
5 MASTER
3 BOM Configuration MASTER
TABLE_TABLEOFCONTENTS_ITEM
7 MASTER
.c
4 Functional / ICT Test MASTER
TABLE_TABLEOFCONTENTS_ITEM
8 MASTER
5 Power Aliases MASTER
9 MASTER
TABLE_TABLEOFCONTENTS_ITEM
8
39
ETHERNET PHY (CAESAR IV) K91_ERIC
10/11/2010 C
x
TABLE_TABLEOFCONTENTS_ITEM
44 MASTER
9 RIO CONNECTORS MASTER
TABLE_TABLEOFCONTENTS_ITEM
46 07/01/2011
10 External USB Connectors RIO_BEN
TABLE_TABLEOFCONTENTS_ITEM
79 MASTER
11 Power Control 1/ENABLE
fi
MASTER
TABLE_TABLEOFCONTENTS_ITEM
97 07/07/2011
12 HDMI SHIFTER MASTER
TABLE_TABLEOFCONTENTS_ITEM
98 07/07/2011
13 HDMI CONNECTOR MASTER
TABLE_TABLEOFCONTENTS_ITEM
102 06/25/2010
14 PCH Constraints 1 K92_YUN
a
TABLE_TABLEOFCONTENTS_ITEM
109 05/14/2010
TABLE_TABLEOFCONTENTS_ITEM
15 PCB Rule Definitions K17_MLB
in
h
B B
.c
w
w
w
A ALIASES RESOLVED
Schematic / PCB #s
DRAWING TITLE
SCHEM,RIO,D2
DRAWING NUMBER SIZE
D
A
D D
m
o
J4400 J4410
.c
32 Pin Flex Connector 30 Pin Coax Connector
PG 9 PG 8
C C
x
fi
U3520 U3510 J4600 J4600
a
PG 6 PG 6 PG 13 PG 10
U3900
in
Caesar-IV
BCM57765
PG 7
h
J3500
SD
Connector
B B
.c
PG 6
w
w
w
A SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
Apple Inc. D
REVISION
R
D D
BOM GROUP BOM OPTIONS PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_BOMGROUP_ITEM
PART NUMBER
J5_RIO_COMMON COMMON,ENETLOWPWR:NO,J5_RIO_PROGPARTS,HDMI_3V3_S0:YES,ALTERNATE TABLE_ALT_ITEM
m
TABLE_BOMGROUP_ITEM
J5_RIO_PROGPARTS TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
197S0450 197S0177 ALL Alt EPSON Xtal
J5_RIO_DEVEL:ENG ENET_ROM TABLE_ALT_ITEM
o
.c
Bar Code Labels / EEEE #s
C PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
C
x
825-7753 1 TEXT,LABEL,RIO,D2 [EEEE:DL62] CRITICAL EEEE:DL62
825-7697 1 LBL,SERIAL NO,BOARDS,D2 TEXT_lABEL CRITICAL EEEE:DL62
fi
a
in
Module Parts
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
h
B B
.c
w
w
A SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
BOM Configuration
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R
TRUE USB3_EXTB_RX_P 9 10 14
TRUE USB3_EXTB_RX_N 9 10 14
TRUE USB3_EXTC_TX_P
TRUE USB3_EXTC_TX_N
TRUE USB3_EXTC_RX_P
TRUE USB3_EXTC_RX_N
I1042 TRUE PP5V_S3_RTUSB_B_F 10
D I1043
I1044
TRUE
TRUE
USB_EXTB_F_N
USB_EXTB_F_P
10 14
10 14
TRUE
TRUE
USB3_EXTB_TX_F_P
USB3_EXTB_TX_F_N
14
14
D
TRUE GND TRUE USB3_EXTB_RX_F_P 14
TRUE USB3_EXTB_RX_F_N 14
TRUE HDMI_DATA_CONN_P<2..0> 13 14
TRUE HDMI_DATA_CONN_N<2..0> 13 14
POWER RAILS
PP3V3_S3 TRUE HDMI_DATA_P<2..0> 12 13 14
TRUE 5 7 9 11 12
I615
TRUE HDMI_DATA_N<2..0> 12 13 14
m
I639 TRUE PP3V3_S4 5 7 9 12 13
TRUE HDMI_DATA_C_P<2..0> 9 12 14
TRUE PP5V_S4 5 9 10 13
I1054
TRUE HDMI_DATA_C_N<2..0> 9 12 14
o
.c
C C
x
fi
a
in
h
B B
.c
w
w
w
A SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
Apple Inc. D
REVISION
R
13 10 9 5 4 PP5V_S4 PP5V_S4 4 5 9 10 13
ENET Rails
D MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
11 8 7 5 PP3V3_ENET PP3V3_ENET
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
5 7 8 11
D
PP5V_S4 4 5 9 10 13 VOLTAGE=3.3V
MAKE_BASE=TRUE
PP5V_S4 4 5 9 10 13 PP3V3_ENET 5 7 8 11
11 8 7 5 PP1V2_ENET PP1V2_ENET 5 7 8 11
12 9 7 5 4 PP3V3_S4 PP3V3_S4 4 5 7 9 12 13 MIN_LINE_WIDTH=0.6 MM
13 MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE VOLTAGE=1.2V
MAKE_BASE=TRUE
PP3V3_S4 4 5 7 9 12 13
PP1V2_ENET 5 7 8 11
PP3V3_S4 4 5 7 9 12 13
m
11 9 7 5 4 PP3V3_S3 PP3V3_S3 4 5 7 9 11 12
o
12 MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
PP3V3_S3 4 5 7 9 11 12
PP3V3_S3 4 5 7 9 11 12
.c
PP3V3_S3 4 5 7 9 11 12
PP3V3_S3 4 5 7 9 11 12
PP3V3_S3 4 5 7 9 11 12
C C
x
12 5 PP3V3_HDMI PP3V3_HDMI 5 12
MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
PP3V3_HDMI 5 12
PP3V3_HDMI
fi
5 12
a
in
1.5V Rail
12 9 5 PP1V5_S0 PP1V5_S0 5 9 12
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
h
PP1V5_S0 5 9 12
PP1V5_S0 5 9 12
B B
GND
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
.c
w
VOLTAGE=0V
w
w
A SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
Power Aliases
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R
D D
APN870-2451
m
Pogo pins Unused ethernet signals
SH900
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
ENET_MDI_P<3..0> NC_ENET_MDI_P<3..0> 8
o
1 MAKE_BASE=TRUE NO_TEST=TRUE
ENET_MDI_N<3..0> NC_ENET_MDI_N<3..0> 8
MAKE_BASE=TRUE NO_TEST=TRUE
8 6 NC_ENET_WAKE_L NC_ENET_WAKE_L 6 8
MAKE_BASE=TRUE NO_TEST=TRUE
SH901 8 6 NC_ENET_MEDIA_SENSE NC_ENET_MEDIA_SENSE 6 8
.c
POGO-2.3OD-5.5H-SM-LOW-FORCE MAKE_BASE=TRUE NO_TEST=TRUE
SM
1
8 6 SYSCLK_CLK25M_ENET SYSCLK_CLK25M_ENET 6 8
C SH902
POGO-2.3OD-5.5H-SM-LOW-FORCE
MAKE_BASE=TRUE
C
x
SM
1
SH903
fi
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
1
a
in
APN:998-3975
TH900
TH-NSP
1
SL-1.1X0.45-1.4x0.75
TH901
APN806-2500
h
TH-NSP
1
can shield SL-1.1X0.45-1.4x0.75
1
TH902
B B
.c
S904 1
TH-NSP
SM
SL-1.1X0.45-1.4x0.75
TH900/1 for USB can gnd slot
SHLD-J5-USB-RIO TH902/3 for HDMI can gnd slot
TH903
TH-NSP
1
APN806-2865 SL-1.1X0.45-1.4x0.75
w
can shield
1
S905
SM
w
SHLD-J5-HDMI
w
APN998-1457
SMT GND connuity test pin
T900
A 1
A
TP-1P0-TOP
SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
Signal Aliases
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R
D 2 IN0
3 IN1
DGN OUT0 6 MF-LF
2 402
PP3V3_S4
13 12 9 7 5 4
MF-LF
402 2 D
12 11 9 7 5 4 PP3V3_S3 OUT1 7 PP3V3_S0_SW_SD_PWR 7
OUT2 8 MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mm SDCONN_DETECT 8
4
353S3004 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
Q3510
8 ENET_CR_PWREN EN CRITICAL NOSTUFF SSM3K15FV D 3 CRITICAL
OC* 5 SDCONN_OC_L 1 C3502 1 C3503 1
R3500 SOD-VESM-HF
CRITICAL THRM 10UF 0.1UF 47K
GND PAD 20% 10% 5%
1 C3500 1 C3501 2 6.3V
X5R 2 16V
X7R-CERM 1/16W
R35341
9
10UF 0.1UF 603 402 MF-LF
20% 10% 2 402 PLACE_NEAR=U3530.7:5mm
0 1 G S 2
2 6.3V
X5R 2 16V
X7R-CERM 5% ENETLOWPWR:YES
603 402 1/16W 7 SDCONN_DETECT_L
MF-LF FROM SD CONN ->
-> TO ENET CHIP 402 2
m
SD_PWR_EN_SAK_R 7
R3532
0
11 8 5 PP1V2_ENET 1 2 P1V2_ENET_PHY_R 7
5%
DETECT-CHANGED PCH GPIO LATCH CIRCUIT
o
1/16W
MF-LF
402
12 11 9 7 5 4 PP3V3_S3
DLY block is 20ms nominal
.c
ENETLOWPWR:YES
When ENET_LOW_PWR deasserts, RST_OUT# Supervisor & CLKREQ# Isolation
deasserts for >80ms, then asserts for
C3510 1
10ms regardless of RST_IN# state. SDCONN DETECT DEBOUNCE, INVERSION, AND
1UF
10% Otherwise RST_OUT# follows RST_IN#
10V 2
X5R
402-1
DETECT-CHANGED PCH GPIO LATCH CIRCUIT
C Must STUFF R3512 and NOSTUFF R3514
ENETLOWPWR:YES
when not using K9x back up RESET.
C
x
CRITICAL PP3V3_S4 ENETLOWPWR:NO -->power cutoff C-IV
1
13 12 9 7 5 4
VDD R3514 and R3512 mutually exclusive ENETLOWPWR:YES--> C-IV in low power mode
U3511 to bypass reset logic C3530 1
10
fi
0.1UF CRITICAL
SLG4AP014V ENETLOWPWR:YES 10%
25V 2
TDFN X5R VDD
R3514 402 U3530
11 8 ENET_LOW_PWR 2 LOW_PWR
RST RST_OUT* 4 SLG_ENET_RESET_OUT_L 1
0 2 ENET_RESET_L 8
Platform (PCIe) Reset SLG4AP029V
OUT TDFN
LOGIC
5% 11 8 7 5 PP3V3_ENET 9 SD_RESET_L 2 MR*
1/16W
ENET_RESET_L_R 3 RST_IN* MF-LF R3531 1
a
7 SENSE RESET*
402 P1V2_ENET_PHY_R
7
1
6 DET_IN ENETLOWPWR:NO 100K 3 ENET_RESET_L_R 7
NC DLY (OD) 8 1 5% R3533 ENETLOWPWR:NO
XOR
(IPU)
NC R3512 1/16W
MF-LF 0 7 2 SD_PWR_EN_SAK_R
DET_CHNGD* 0 402 2 11 9 SD_PWR_EN 1 7 EN
(OD) 7 5% OUT 9 SD_CLKREQ_L 9
1/16W 5%
NC ENET_CLKREQ_ISOL_L 8
in
MF-LF 8 7 1/16W IN Pull-up provided by SB page.
DET_OUT MF-LF
2 402 402
THRM
GND PAD 7 SDCONN_DETECT_L 4 DET_IN
(IPU) 6 SDCONN_STATE_CHANGE 9
5
11
h
B *Note logic inversion of K16 connector.* B
.c
Input to C-IV should remain active low New part SLGAP029V (APN 343s0563)
8 7 ENET_CLKREQ_ISOL_L ENET_CLKREQ_ISOL_L 7 8
w
MAKE_BASE=TRUE
SD CARD CONNECTOR
CRITICAL
516-0248
J3500
w
SD-CARD-J5
CRITICAL F-RT-TH
L3500 3
VSS
47NH-1.3OHM 0402 6
VSS J5 connector different from K9X connector which was CARD INSERTED = OPEN
14 8 IN SDCONN_CLK R3579 33 1 2 5% 1/20W MF 201 14 SDCONN_CLK_R 1 2 SDCONN_CLK_R_L 5
CLK
R3561
w
1 2
L3920
PP3V3_S3_ENET_PHY_XTALVDDH FERR-600-OHM-0.5A
D SM MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V C3900 1 PP1V2_ENET_PHY_AVDDL 1 2 D
MIN_LINE_WIDTH=0.4 mm SM
0.1UF MIN_NECK_WIDTH=0.2 mm
10% VOLTAGE=1.2V
16V
X5R-CERM 2
0201
C3921 1 1 C3920
CRITICAL 0.1UF 4.7UF From Broadcom:
10% 20%
L3905 16V
X5R-CERM 2 2 6.3V
X5R-CERM1 CRITICAL For SD-Only, can remove C3931, C3930,
FERR-600-OHM-0.5A
1 2
0201 402 L3925 C3921,C3920, C3910, C3911, R3910 TBD, R3965 TBD
PP3V3_S3_ENET_PHY_BIASVDDH FERR-600-OHM-0.5A
SM MIN_LINE_WIDTH=0.4 mm For SD-Only, RIO removed C3930 as space limited
MIN_NECK_WIDTH=0.2 mm PP1V2_ENET_PHY_PCIEPLL 1 2
VOLTAGE=3.3V 1 C3905 MIN_LINE_WIDTH=0.4 mm SM
0.1UF MIN_NECK_WIDTH=0.2 mm
10% VOLTAGE=1.2V
2 16V
X5R-CERM C3926 1 1 C3925
m
CRITICAL 0201 0.1UF 4.7UF
10% 20%
L3910 16V
X5R-CERM 2 2 6.3V
X5R-CERM1 CRITICAL
FERR-600-OHM-0.5A
1 2
0201 402 L3930
PP3V3_S3_ENET_PHY_AVDDH FERR-600-OHM-0.5A
SM MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm PP1V2_ENET_PHY_GPHYPLL 1 2
VOLTAGE=3.3V R39101 1 C3910 1 C3911 MIN_LINE_WIDTH=0.4 mm SM
0.1UF 0.1UF
o
4.7K MIN_NECK_WIDTH=0.2 mm
5% 10% 10% VOLTAGE=1.2V
1/20W 2 16V
X5R-CERM 2 16V
X5R-CERM C3931 1
MF 0201 0201
201 2 0.1UF
10%
16V
X5R-CERM 2
0201
.c
R39401 1
R3941 C3915 1 1 C3916 CRITICAL
4.7K 4.7K 4.7UF 0.1UF
42
48
BIASVDDH 37
XTALVDDH 17
20
56
62
SR_VDD 14
SR_VDDP 15
SR_LX 16
SR_VFB 13
39
45
51
29
32
GPHY_PLLVDDL 36
35
61
20% 10% C3936 1 1 C3935 LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
7
5% 5% 6.3V
1/20W 1/20W X5R-CERM1 2 2 16V
X5R-CERM 0.1UF 10UF
C MF
201 2
MF
2 201
402 0201 10% 20% the card reader on-chip I/O.
C
PCIE_PLLVDDL
AVDDH VDDO AVDDL VDDC 16V
X5R-CERM 2 2 4V
X5R Connect only to U3900 pin 20.
x
0201 402
1
C3950 R3942 PP3V3R1V8_ENET_LR_OUT_REG 8
1K
0.1UF 5% Current
1 2 1/20WLimiting
14 9 OUT PCIE_ENET_D2R_N MF
2 201 Resistor
fi
10% U3900 PP3V3R1V8_ENET_LR_OUT_REG
16V
X5R-CERM
C3951 ENET_VMAIN_PRSNT 58 VMAIN_PRSNT (IPD) BCM57765B0 TRD0_P 40 NC_ENET_MDI_P<0> BI 6 MAKE_BASE=TRUE
0201 0.1UF QFN-8X8 41 NC_ENET_MDI_N<0> MIN_LINE_WIDTH=0.3 mm
1 2 TRD0_N BI 6
MIN_NECK_WIDTH=0.2 mm
14 9 OUT PCIE_ENET_D2R_P VOLTAGE=1.8V
14 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N TRD1_P 44 NC_ENET_MDI_P<1> BI 6
10% 14 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P TRD1_N 43 NC_ENET_MDI_N<1>
16V
X5R-CERM 46 NC_ENET_MDI_P<2>
BI 6
1 C3970 1 C3971 1 C3972
C3955 TRD2_P
a
0201 14 PCIE_ENET_R2D_P 33 PCIE_RXD_P BI 6
4.7UF 0.1UF 0.1UF
0.1UF TRD2_N 47 NC_ENET_MDI_N<2> 20% 10% 10%
14 PCIE_ENET_R2D_N 34 PCIE_RXD_N CRITICAL BI 6
2 6.3V 2 16V 2 16V
14 9 PCIE_ENET_R2D_C_P 1 2 TRD3_P 50 NC_ENET_MDI_P<3> 6
X5R-CERM1 X5R-CERM X5R-CERM
IN BI 402 0201 0201
10% 14 9 IN PCIE_CLK100M_ENET_P 31 PCIE_REFCLK_P TRD3_N 49 NC_ENET_MDI_N<3> BI 6
16V
X5R-CERM
C3956 14 9 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N OMIT_TABLE
in
0201 0.1UF
(IPD)
1 2 GPIO_0/CR_ACT_LED* 5 NC
14 9 IN PCIE_ENET_R2D_C_N 7 IN ENET_RESET_L 11 PERST* (IPD)
GPIO_1/LR_OUT 8
10% ENET_CLKREQ_ISOL_L 12 CLKREQ* GPIO_2/MEDIA_SENSE 9 NC_ENET_MEDIA_SENSE
R3943 16V
X5R-CERM
7 OUT (OD) OUT 6
NC_ENET_WAKE_L 1
0 2 0201 ENET_WAKE_R_L 3 WAKE* NOTE: "IPx" == Programmable pull-up/down SDCONN_DETECT use high logic
6 OUT (OD)
(IPx) SD_DETECT 1 o SDCONN_DETECT IN 7
(See note) 5%
1/20W SD_DETECT can only be used active low due to errata.
MF 11 7 IN ENET_LOW_PWR 4 LOW_PWR (IPD) (IPU) CR_CMD 26 SDCONN_CMD IN 7 14
WAKE# 201
h
0
BCM57765_SMB_CLK 6 SMB_CLK CR_CLK 21 14 SDCONN_ENET_CLK_R R39811 2 SDCONN_CLK OUT 7 14
Must isolate from PCIe WAKE# if PHY 5% 1/20W MF 201
is powered-down in S3/S5. Standard BCM57765_SMB_DATA 10 SMB_DATA (IPD) CR_DATA0 25 SDCONN_DATA<0> BI 7 14
.c
CR_DATA2 BI 7 14
BCM57765_MISO 64 SI/EEDATA
(IPU)
8
=ENET_WAKE_L to PCIE_WAKE_L. CR_DATA3 22 SDCONN_DATA<3> BI 7 14
8 BCM57765_MOSI 65 SO_LINKLED*
CR_DATA4 52 SDCONN_DATA<4> BI 7 14
8 BCM57765_CS_L 63 CS*/EECLK
CR_DATA5 53 SDCONN_DATA<5>
(IPU)
BI 7 14
MS_INS* 59 TP_CE_L_MS_INS_L
(IPU)
SYSCLK_CLK25M_ENET 18 XTALI No MS (Memory Stick) Insert feature needed.
w
8 6
CR_LED*/CR_BUS_PWR 60 ENET_CR_PWREN OUT 7 Control signal to light LED or control SD bus power.
8 ENET_CLK25M_XTALO 19 XTALO
CR_WP* 57 SDCONN_WP IN 7
69
1
R3965
w
11 8 7 5
ENET_ROM
Caesar IV (ENET) 25MHz Crystal
6
1 C3990
VCC 0.1UF
10%
R3960 C3960
U3990 2 16V
X5R-CERM 27pF
0201 200 1 2
M45PE10 8 ENET_CLK25M_XTALO 1 2 BCM5764_CLK25M_XTALO_R
SOIC NO STUFF 5%
8 BCM57765_SCLK 2 C ENET_ROM D 1 BCM57765_MOSI 8 1/16W 5%
3
402 402
10M
2 4
8 BCM57765_CS_L 4 S* 5% Y3960 NC SYNC_MASTER=K91_ERIC
PAGE TITLE
SYNC_DATE=10/11/2010
1
W* 402 2
NOSTUFF 27pF
1 1 1 2 DRAWING NUMBER SIZE
3 RESET* R3990 R3997 ENET_CLK25M_XTALI
VSS 4.7K 4.7K
8
Apple Inc. D
5% 5% 5% REVISION
7
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
14 10 BI USB_EXTB_N 2
m
11 7 OUT OUT 12 14 10 9 4 OUT
GND_VOID=TRUE
7 IN SDCONN_STATE_CHANGE 7 8 HDMI_DDC_LS_DATA BI 12
6
12 5 PP1V5_S0 11 12 14 10 9 4 IN USB3_EXTB_RX_N 8
13 14 GND_VOID=TRUE 9
15 16 14 12 9 4 OUT HDMI_DATA_C_P<0> GND_VOID=TRUE 10
o
12 11 7 5 4 PP3V3_S3 17 18 14 12 9 4 OUT HDMI_DATA_C_N<0> 11
GND_VOID=TRUE
13 12 7 5 4 PP3V3_S4 19 20 12
.c
27 28 PP5V_S4 4 5 9 10 13 14 12 9 4 OUT HDMI_DATA_C_P<2> GND_VOID=TRUE 16
29 30 14 12 9 4 OUT HDMI_DATA_C_N<2> 17
GND_VOID=TRUE
13 10 9 5 4 PP5V_S4 31 32 18
14 12 OUT HDMI_CLK_C_LS_P 19
HDMI_CLK_C_LS_N 20
C 34 14 12 OUT
21 C
PCIE_CLK100M_ENET_P 22
x
14 8 OUT
14 8 OUT PCIE_CLK100M_ENET_N 23
24
14 8 IN PCIE_ENET_D2R_P 25
PCIE_ENET_D2R_N 26
fi
14 8 IN
27
12 9 I2C_HDMIRDRV_SDA_CONN I2C_HDMIRDRV_SDA_CONN 9 12 30
MAKE_BASE=TRUE
a
12 9 HDMI_HPD_L HDMI_HPD_L 9 12
33
MAKE_BASE=TRUE 34
35
36
in
37
B4401 B4405 38
BEAD-PROBE BEAD-PROBE 39
SM SM
40
1 1
14 10 9 4 USB3_EXTB_TX_P 14 12 9 4 HDMI_DATA_C_P<0> 41
B4402 B4406
BEAD-PROBE BEAD-PROBE 32
h
SM SM
1 1
14 10 9 4 USB3_EXTB_TX_N 14 12 9 4 HDMI_DATA_C_N<0>
13 12 11 9 PM_SLP_S3_L B4403 B4407
B BEAD-PROBE
B
.c
SM BEAD-PROBE
SM
1
1 14 10 9 4 USB3_EXTB_RX_P HDMI_DATA_C_P<1> 1
R4400 14 12 9 4
B4409
BEAD-PROBE
SM
1
14 12 9 4 HDMI_DATA_C_P<2>
B4410
A BEAD-PROBE
SM SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
14 12 9 4 HDMI_DATA_C_N<2> 1
RIO CONNECTORS
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R
D TCM0605-1
SYM_VER-1 D
14 9 BI USB_EXTB_N 1 4 USB3 Connector APN 514-0804
CRITICAL
14 9 BI USB_EXTB_P 2 3 J4600
USB3.0-J5
USB2 common choke 155S0583 F-RT-TH
1
VBUS
14 4 USB_EXTB_F_N 2
D-
14 4 USB_EXTB_F_P 3
D+
4
GND
14 9 4 USB3_EXTB_RX_N 5
m
OUT STDA_SSRX-
14 9 4 USB3_EXTB_RX_P 6
OUT STDA_SSRX+
7
GND_DRAIN
8
STDA_SSTX-
9
STDA_SSTX+
GND_VOID=TRUE GND_VOID=TRUE 10
CRITICAL CRITICAL CRITICAL SHLD
2 2 11
o
USB Port Power Switch USB3_EXTB_TX_N
2 5 3 4 D4601 D4603 12
SHLD
NC
IO
NC
IO
14 9 4 IN ESD0P2RF-02LS ESD0P2RF-02LS 13
SHLD
14 9 4 IN USB3_EXTB_TX_P 6 VBUS TSSLP-2-1 TSSLP-2-1 SHLD
13 9 5 4 PP5V_S4 1 GND GND_VOID=TRUE GND_VOID=TRUE
1 1 14
CRITICAL CRITICAL CRITICAL
.c
CRITICAL 2 2
1 C4690 1 1 C4691 D4602 D4604 15
C4696 10UF 0.1UF CRITICAL
D4600 ESD0P2RF-02LS ESD0P2RF-02LS 16
220UF-35MOHM 20%
6.3V 2
10% TSSLP-2-1 TSSLP-2-1
20% X5R 2 16V
X5R-CERM RCLAMP0502N 17
6.3V
POLY-TANT 2 603 0201 U4600 SLP1210N6 1 1 18
CASE-B2-SM1 TPS2557DRB
SON
C 2 IN_0
3 IN_1
OUT1 6
OUT2 7
C
x
9 USB_EXTB_OC_L 8 FAULT* ILIM 5 USB_ILIM
OUT
4 EN USB3 TVS DIODES 377S0104
CRITICAL
R4601 R46001 C4695 1
fi
9 PM_SLP_S4_L 1
0 2 USB_PWR_EN GND
THRM
PAD 22.1K 10UF
1% 20%
5% 6.3V 2
1
1/20W X5R
1/16W NOSTUFF 1 MF 603
MF-LF R4602 201 2
402 1 C4600 1M PLACE_NEAR=U4600.5:3mm
0.1UF 5%
20% 1/20W USB_MID
2 10V MF R46041
a
CERM 201
402 2 22.1K
1%
1/20W
MF
201 2
PLACE_NEAR=U4600.5:3mm
in
Current limit per port (R4600+R4604): 2.19A min / 2.76A max
U4600 Port C is deleted, only keep dummy USBC connector for PD
h
B B
.c
w
w
w
A SYNC_MASTER=RIO_BEN SYNC_DATE=07/01/2011 A
PAGE TITLE
Apple Inc. D
REVISION
R
Run (S0) 1 1 1 1
Sleep (S3) 1 1 1 0
Deep Sleep (S4) 1 1 0 0
m
o
.c
3.3V ENET Switch
12 9 7 5 4 PP3V3_S3
C U7920 CAESAR IV 1.2V INT.VR CMPTS C
TPS22924
x
PP3V3_ENET 5 7 8 11
CSP CRITICAL
A2 A1
ENETLOWPWR:NO B2 VIN VOUT B1 Max Current = 0.14A (SD only) L7940
R7921 CRITICAL 4.7UH-0.8A
0
fi
11 9 7 IN SD_PWR_EN 1 2 SD_PWR_EN_R C2 ON 11 8 7 5 PP3V3_ENET 1 2 ENET_SR_LX 8
GND PCAA031B-SM MIN_LINE_WIDTH=0.4MM
5% MIN_NECK_WIDTH=0.2MM
1/16W VOLTAGE=1.2V
C1
a
5% 402 402 0201
1/16W 50 mOhm Max PP1V2_ENET
MF-LF 5 7 8 11
402 2
Max Output: 2A per IC
13 12 9 PM_SLP_S3_L CRITICAL
C7943 C7944
in
1 1
10UF 0.1UF
Stuff R7920 & R7921 force ENET switch always on 20% 10%
2 4V
X5R 2 16V
X5R
and connect ENET_LOW_PWR to GPIO instead 402 402
ENETLOWPWR:YES
R7922
SD_PWR_EN 1
0 2 ENET_LOW_PWR
11 9 7 IN OUT 7 8
h
5%
1/16W
MF-LF
402
B B
.c
w
w
w
A SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
Apple Inc. D
REVISION
R
D 0.1UF
10%
0.01UF
10%
10%
16V
2 X5R-CERM
20%
6.3V
2 X5R
MIN_LINE_WIDTH=0.4 mm (=PP1V5_HDMI_VDDTA) 1 2 PP1V5_S0
0402
5 9 12
D
2 16V 2 16V
X5R-CERM
0201
X5R-CERM
0201
0201 0201 1 C9704 1 C9705
0.01UF 1UF
10% 20%
16V
2 X5R-CERM
6.3V
2 X5R
0201 0201
CRITICAL PLACE_NEAR=U9700.19:5mm PLACE_NEAR=U9700.19:5mm
OMIT_TABLE
PLACE_NEAR=U9700.6:5mm PP1V5_HDMI_VDDTA
14 9 4 IN HDMI_DATA_C_P<0> C9713 1 2 GND_VOID=TRUE
10% 16V X5R-CERM 0201
14 HDMI_DATA_LS_P<0> L9702
0.1UF VOLTAGE=1.5V 120OHM-25%-0.45A-0.24DCR
PLACE_NEAR=U9700.7:5mm MIN_NECK_WIDTH=0.2 mm
14 9 4 IN HDMI_DATA_C_N<0> C9712 1 2 GND_VOID=TRUE
10% 16V X5R-CERM 0201
14 HDMI_DATA_LS_N<0> MIN_LINE_WIDTH=0.4 mm PP1V5_HDMI_VDDTX 1 2 PP1V5_S0 5 9 12
0.1UF 0402
C9702 C9703
m
OMIT_TABLE 1 1
HDMI_DATA_C_P<1> C9715 1 2 PLACE_NEAR=U9700.4:5mm
HDMI_DATA_LS_P<1> CRITICAL 0.01UF 1UF
14 9 4 IN GND_VOID=TRUE 14
10% 20%
10% 16V X5R-CERM 0201 16V 6.3V
0.1UF 2 X5R-CERM 2 X5R
PLACE_NEAR=U9700.5:5mm
HDMI_DATA_C_N<1> C9714 1 2 GND_VOID=TRUE HDMI_DATA_LS_N<1> 0201 0201
VDD33 11
VDD33 37
VDDRX 12
VDDRX 40
VDDTA 19
VDDTX 20
VDDTX 31
14 9 4 14
IN
10% 16V X5R-CERM 0201
0.1UF PLACE_NEAR=U9700.20:5mm PLACE_NEAR=U9700.31:5mm
o
14 9 4 IN GND_VOID=TRUE 14
10% 16V X5R-CERM 0201
0.1UF
PLACE_NEAR=U9700.2:5mm
14 9 4 IN HDMI_DATA_C_N<2> C9716 1 2 GND_VOID=TRUE
10% 16V X5R-CERM 0201
14 HDMI_DATA_LS_N<2>
U9700
0.1UF
6 IN_D0P
PS8401A-A3 OUT_D0P 25 HDMI_DATA_P<0>
C9711 OUT 4 13 14
.c
14 9 HDMI_CLK_C_LS_P 1 2 PLACE_NEAR=U9700.9:5mm 14 HDMI_CLK_LS_P QFN
IN 7
10% 16V X5R-CERM 0201 IN_D0N OUT_D0N 24 HDMI_DATA_N<0> OUT 4 13 14
0.1UF NOSTUFF
14 9 IN HDMI_CLK_C_LS_N C9710 1 2 PLACE_NEAR=U9700.10:5mm 14 HDMI_CLK_LS_N 4 IN_D1P OUT_D1P 27 HDMI_DATA_P<1> OUT 4 13 14
R9704
10% 16V X5R-CERM 0201 5
0.1UF PLACE_NEAR=U9700.18:5mm IN_D1N OUT_D1N 26 HDMI_DATA_N<1> OUT 4 13 14 470
1 2 PM_SLP_S3_L IN 9 11 12
12 5 PP3V3_HDMI 1 13
C 1
R9710 1
R9711 1R9708 1
R9702
4.7K
R9701
4.99K
2 IN_D2N OUT_D2N 29 HDMI_DATA_N<2> OUT 4 13 14
1 C9724
1UF
PP3V3_HDMI 5 12 C
R9709 5% 1%
x
2.0K 2.0K 1/20W 1/16W 9 IN_CKP OUT_CKP 22 HDMI_CLK_P 13 14
20%
4.7K 4.7K OUT 6.3V 1 1 1
5%
1/20W
5%
1/20W 5% 5%
MF
2 201
MF-LF
2 402
10 IN_CKN OUT_CKN 21 HDMI_CLK_N OUT 13 14
2 X5R
0201
R9700 R9705 R9706
MF MF 1/20W 1/20W 4.7K 4.7K 150K
2 201 2 201 MF MF
REXT_LS 18 PD* 36 LS_PWR_DWN_L 5% 5% 5%
2 201 2 201 REXT
IPU 150K
1/20W
MF
1/20W
MF
1/20W
MF
NOSTUFF NOSTUFF NOSTUFF NOSTUFF 2 201 2 201 2 201
fi
9 I2C_HDMIRDRV_SDA_CONN 14 DDCBUF/SDA_CTL CFG/I2C_ADDR1 23 LS_CFG_I2C_ADDR1
BI
I2C_HDMIRDRV_SCL_CONN 13 IPD 150K NOSTUFF NOSTUFF
9 DCIN_EN/SCL_CTL
IN
ISET 34 LS_ISET
PLACE_NEAR=J4400.6:10mm 8 IPD 150K
PLACE_NEAR=J4400.8:10mm LS_I2C_CTL_EN I2C_CTL_EN
PLACE_NEAR=J4400.21:10mm I2C_CTL_EN=L, pin control mode IPD 150K CFG=L, HDMI ID disabled
PLACE_NEAR=J4400.23:10mm 17
I2C_CTL_EN=H, I2C control mode 12 EQ_I2C_ADDR0 EQ/I2C_ADDR0 CFG=H, HDMI ID enabled
16 IPD 150K
PREQ PRE
a
12
IPD 150K ISET= L, output swing default
9 HDMI_DDC_LS_CLK 38 SCL_SRC IPU SCL_SNK 32 HDMI_DDC_CLK_5V 13 ISET= H, output swing +13%
IN OUT
9 HDMI_DDC_LS_DATA 39 SDA_SRC IPU SDA_SNK 33 HDMI_DDC_DATA_5V 13 ISET= M, output swing -13%
BI BI
THRM
DDC_CLK/DATA can be programmed to 1.2K, 1.5K or 3.5K
PAD
3 HPD_SNK 28
GND
GND
HPD_NO_USE_LS HPD_SRC IPD 150K PD# =L, PS8401 power down
in
PD# =H, PS8401 in normal mode
R9808/9 need chracterization to confirm 1
R9707
15
35
41
I2C_SDA/SCL already have pull up in MLB
4.7K DEFAULT I2C = 0xCC (write) / 0xCD (read)
5%
1/20W
MF
2 201
NOSTUFF
R9722
h
0
HDMI_HPD_SNK_R 1 2 HDMI_HPD_SINK IN 12 13
MF 1/20W 5% 201
.c 12 5 PP3V3_HDMI
5%
R9730
4.7K
1
R9731
4.7K
5%
w
1/20W 1/20W
HDMI 3.3V_S0 Switch MF
2 201
MF
2 201
R9742 PREQ 12
0
w
11 9 7 5 4 PP3V3_S3 1 2
MF-LF 1/16W 13 9 7 5 4 PP3V3_S4
HDMI_3V3_S0:YES 5%
402 PLACE_NEAR=U9720.5:4mm
C9740 1 1 C9720 I2C control enabled when R9702 is stuffed
1UF HDMI_3V3_S0:YES 0.1UF
10% 10%
U9740
w
6.3V 2
CERM 2 16V
X5R-CERM I2C_ADDR1 I2C_ADDR0 I2C ADDRESS(W/R)
402 TPS22924 PP3V3_HDMI 5 12
0201
0x4C/4D (default)
CSP L L
A2 A1
HDMI_3V3_S0:YES B2 VIN VOUT B1
U9720 5
SN74AHC1G00 L H 0x5C/5D
R9740 SOT-23-5 A 1 HDMI_HPD_SINK IN 12 13
CRITICAL HDMI_HPD_L 4
0 9 OUT Y H L 0xCC/CD
13 12 11 9 IN PM_SLP_S3_L 1 2 HDMI_3V3_PWR_EN C2 ON
2
HPD sink High: 2.0V-5.3V
GND B
5%
1/16W
NOSTUFF HPD sink Low: 0.0V-0.8V
H 0xEC/ED
C9741 H
C1
1 3 1
MF-LF
402
1UF
Part TPS22924C PLACE_NEAR=J4400.12:10mm R9720
470K
A 10%
6.3V
CERM 2
Type Load Switch 5%
1/20W
MF
SYNC_MASTER=MASTER SYNC_DATE=07/07/2011 A
402 PAGE TITLE
R(on) 18 mOhm Typ 2 201
50 mOhm Max NOSTUFF HDMI SHIFTER
DRAWING NUMBER SIZE
Max Output: 2A per IC
Apple Inc. D
PM_SLP_S3_L pull down on csa 44 REVISION
R
Max Current = 30mA (HDMI 3V3_S0 only)
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
97 OF 109
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 12 OF 15
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
HDMI spec allows 55mA
OMIT_TABLE Switch cuts off at 100mA to 200mA
L9890/1/2/3: 155S0726
L9860 CRITICAL
CRITICAL 3.0NH+/-0.2NH-0.45A
HDMI_CLK_FLT_P 1 2 HDMI_CLK_CONN_P U9800
L9893
35-OHM-50MA
14
0201
13 14
TPS2553
HDMI_CLK_P PP5V_S4 1 IN SOT-23 PP5V_HDMI_DDC_FUSE
TCM0605 OUT 6
14 12 IN SYM_VER-1
C9860 1 C9861 1 1
R9864
13 10 9 5 4
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 MM
13
2
14 12 1/20W 20%
D
IN
HDMI_CLK_N PLACE_NEAR=J9800.10:8mm 3.0NH+/-0.2NH-0.45A
HDMI_CLK_CONN_N
13 14 MF
2 201
2 6.3V
X5R
603 CRITICAL D
1 2 L9830 VOLTAGE=5V
PLACE_NEAR=U9700.22:4mm 14 HDMI_CLK_FLT_N 0201 D9811 HDMI_MID
1
400-OHM-EMI MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
CRITICAL R9801 R9804 1 2 PP5V_HDMI_DDC_CONN
C9862 1 C9863 1
PP3V3_S4 1
100K 2 TPS2553_EN
1%
95.3K SM-1
13
2.0PF 2.0PF 1 12 9 7 5 4
1/20W
+/-0.25PF +/-0.25PF
ESD3V3U4ULC
1% MF
25V 25V 1/20W
C0G-CERM 2 C0G-CERM 2 2 201 1 C9830
0201 0201 2
MF
201 R9800 0.01UF
10K
PGTSLP91
GND 3 13 10 9 5 4 PP5V_S4 2 1 HDMI_OC_L 10%
2 16V
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
4 5% X5R-CERM
6 1/16W 0201
MF-LF
7 402
5
NC
m
8
9 J9800
OMIT_TABLE HDMI-J5
GND_VOID=TRUE CRITICAL
L9862 F-RT-SM
3.0NH+/-0.2NH-0.45A 14 13 4 HDMI_DATA_CONN_P<2> 1 2
TMDS_DATA2+ TMDS_DATA2_SHLD
CRITICAL 14 HDMI_DATA_FLT_P<0> 1 2 GND_VOID=TRUE
HDMI_DATA_CONN_P<0> 4 13 14 HDMI_DATA_CONN_N<2> 3 4 HDMI_DATA_CONN_P<1>
14 13 4 4 13 14
TMDS_DATA2- TMDS_DATA1+
o
GND_VOID=TRUE L9890
35-OHM-50MA
GND_VOID=TRUE 0201 5
TMDS_DATA1_SHLD TMDS_DATA1-
6 HDMI_DATA_CONN_N<1> 4 13 14
GND_VOID=TRUE GND_VOID=TRUE
14 12 4 IN HDMI_DATA_P<0> TCM0605 C9864 1
C9865 1 1 14 13 4 HDMI_DATA_CONN_P<0> 7
TMDS_DATA0+ TMDS_DATA0_SHLD
8
GND_VOID=TRUE 4
SYM_VER-1
1
2.0PF
+/-0.25PF 2.0PF
R9865 14 13 4 HDMI_DATA_CONN_N<0> 9 10 HDMI_CLK_CONN_P 13 14
25V +/-0.25PF 220 11
TMDS_DATA0- TMDS_CLK+
12
R98611 GND_VOID=TRUE C0G-CERM 2 25V 1% TMDS_CLK_SHLD TMDS_CLK-
HDMI_CLK_CONN_N 13 14
0201 C0G-CERM 2 1/20W
.c
90.9 MF TP_HDMI_CEC_CONN 13 14
0201 CEC RSRVD
1% GND_VOID=TRUE 2 201 15 16
1/20W 3 2
OMIT_TABLE GND_VOID=TRUE 13 HDMI_DDC_CLK_CONN SCL SDA
HDMI_DDC_DATA_CONN 13
NOSTUFF MF
L9863 17 18
201 GND_VOID=TRUE PLACE_NEAR=J9800.7:4mm DDC/CEC/HEC/GND
GND_VOID=TRUE 2 3.0NH+/-0.2NH-0.45A 19
+5V_PWR
14 12 4 IN 13 HDMI_HPD_CONN HOT_PLUG_DETECT
GND_VOID=TRUE 1 2 GND_VOID=TRUE
HDMI_DATA_N<0> HDMI_DATA_CONN_N<0> 4 13 14
x
24 IO24 IO25 25
2.0PF 2.0PF
+/-0.25PF +/-0.25PF 26 IO26 IO27 27
SHLD
PINS
25V
25V
C0G-CERM 2
0201
C0G-CERM 2
0201 J5 HDMI CONNECTOR 28
30
IO28 IO29 29
IO30
APN 514-0815
fi
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION max Current<7mA
152S1605 8
IDSON:5 ohm
a
IND, 3.8nH, 0201 L9860,L9861,L9862,L9863,L9864,L9865,L9866,L9867
CRITICAL
APN 376S0974 VOLTAGE=5V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP5V_HDMI_DDC_S0_F
3
13
D
PP5V_HDMI_DDC_FUSE
in
OMIT_TABLE NOSTUFF
1
R9850
NOSTUFF Q9851 1 C9852
GND_VOID=TRUE L9864 1 C9850 DFN1006H4-3 0.01UF
3.0NH+/-0.2NH-0.45A 0.01UF
G
220K DMP210DUFB4 10%
2 GND_VOID=TRUE 1% 10%
16V 2 16V
X5R-CERM
HDMI_DATA_FLT_P<1> 1 HDMI_DATA_CONN_P<1>
1
14 4 13 14 MF 2 X5R-CERM 0201
CRITICAL 0201 2 1/20W R9851 0201
GND_VOID=TRUE 201
GND_VOID=TRUE
L9891 GND_VOID=TRUE GND_VOID=TRUE 1K
HDMI_DATA_P<1> C9868 1 C9869 1 1
ENABLE_HDMI_DDC_S0_R 1 2 ENABLE_HDMI_DDC_S0
12 4 35-OHM-50MA
2.0PF 2.0PF R9866
h
IN 5%
14
GND_VOID=TRUE
TCM0605
SYM_VER-1 +/-0.25PF
25V
+/-0.25PF
25V 220 Q9850 1/20W
C0G-CERM 2 C0G-CERM 2 1% SSM3K15FV D 3 CRITICAL MF
R98621 4 1
GND_VOID=TRUE 0201 0201 1/20W
MF SOD-VESM-HF
201
90.9 2 201
1% GND_VOID=TRUE GND_VOID=TRUE
1/20W
B 3 2 PLACE_NEAR=J9800.4:4mm CRITICAL B
.c
MF
NOSTUFF 201 2 L9850
GND_VOID=TRUE
GND_VOID=TRUE 1 G S 2 MIN_LINE_WIDTH=0.4 MM FERR-470-OHM-215MA-1.5OHM
12 4 IN OMIT_TABLE 4 13 14 12 11 9 IN PM_SLP_S3_L MIN_NECK_WIDTH=0.2 MM
14
HDMI_DATA_N<1> PLACE_NEAR=J9800.4:8mm GND_VOID=TRUE HDMI_DATA_CONN_N<1> PP5V_HDMI_DDC_S0 1 2 (PP5V_HDMI_DDC_S0_F)
PLACE_NEAR=U9700.27:4mm
L9865 VOLTAGE=5V 0201
3.0NH+/-0.2NH-0.45A
14 HDMI_DATA_FLT_N<1> 1 2 GND_VOID=TRUE CRITICAL 1 C9851
1 C9810
GND_VOID=TRUE 0.01UF
0201 1 1 0.01UF 10%
GND_VOID=TRUE
D9810 R9810 R9812 10% 2 16V
w
C9870 1 C9871 1 2.0K
5%
2.0K
5%
16V
2 X5R-CERM
X5R-CERM
0201
2.0PF 2.0PF 1/20W 1/20W 0201
+/-0.25PF +/-0.25PF 1
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
25V 25V MF MF
CRITICAL
ESD3V3U4ULC
201 33
GND_VOID=TRUE HDMI_DDC_DATA_CONN 1 2 HDMI_DDC_DATA_F 1 2 HDMI_DDC_DATA_5V
L9866 13
0201 5%
BI 12
DIFF PAIR
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
4
D
USB3_EXTB_RX USB3_85D USB3 USB_EXTC_RX USB3_EXTB_RX_F_P 4
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
m
TABLE_SPACING_RULE_HEAD
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
PCIE_ENET_R2D_C_N
o
TABLE_SPACING_RULE_ITEM
.c
SOURCE: J5 MLB
PCIE_CLK100M CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_ENET_P 8 9
C C
x
USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD
ALLOW ROUTE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
HDMI Net Properties
fi
TABLE_PHYSICAL_RULE_ITEM
NET_TYPE
USB_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
a
TABLE_SPACING_RULE_HEAD
USB * 0.381 MM ?
in
HDMI_DATA HDMI_90D HDMI HDMI_DATA_P<2..0> 4 12 13
h
13
TABLE_PHYSICAL_RULE_HEAD
USB3_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF HDMI_DATA HDMI_90D HDMI HDMI_DATA_LS_N<2..0> 12
B B
.c
HDMI_CLK HDMI_90D HDMI HDMI_CLK_LS_P 12
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SD_DATA * 8 MIL ?
SOURCE: K90i
A SD Net Properties
SYNC_MASTER=K92_YUN
PAGE TITLE
SYNC_DATE=06/25/2010 A
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL SPACING
PCH Constraints 1
DRAWING NUMBER SIZE
CR_DATA ENET_50S SD_DATA SDCONN_DATA<7..0> 7 8
Apple Inc. D
CR_DATA ENET_50S SD_DATA SDCONN_CMD 7 8 REVISION
R
CR_CLK ENET_50S SD_DATA SDCONN_CLK 7 8
TABLE_PHYSICAL_RULE_HEAD
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
STANDARD * =DEFAULT ?
STANDARD * Y =DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT
TABLE_PHYSICAL_RULE_ITEM
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
50_OHM_SE ISL5,ISL6 Y 0.115 MM 0.115 MM TABLE_SPACING_RULE_ITEM
m
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1X_DIELECTRIC ISL6 0.120 MM ?
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
HDMI_keepout should be 1.016mm. Howerver use 0.3mm per layout restriction TABLE_SPACING_RULE_ITEM
o
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
.c
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
C 90_OHM_DIFF
90_OHM_DIFF
ISL3
ISL5,ISL6
Y
Y
0.092 MM
0.110 MM
0.092 MM
0.110 MM
0.160 MM
0.150 MM
0.160 MM
0.150 MM
TABLE_PHYSICAL_RULE_ITEM
NOTE: Based on RIO (J5) stackup 08/26/11.
C
x
top copper
fi
0.070mm
0.101mm
a
ISL3 PLATE SIG
in
0.120mm
0.101mm
h
ISL5 PLATE SIG
B B
.c
0.120mm
0.070mm
BOTTOM copper
0.070mm
w
A SYNC_MASTER=K17_MLB SYNC_DATE=05/14/2010 A
PAGE TITLE
Apple Inc. D
REVISION
R