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  • DELL XPS 13-9350 AAZ80 LA-C881P r1.0 A00

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    nomi_nomi
    1K visualizzazioni59 pagine
    This document provides information about a PCB model number AAZ80 with PCB number LA-C881P and BOM part number TBD. It includes a list of component part numbers and a schematic diagram labeling the connections between various components including the eDP panel connector, Thunderbolt, memory bus, USB ports and more. The document is confidential property of Compal Electronics and contains their secret data.

    Descrizione originale:

    DELL_XPS_13-9350_AAZ80_LA-C881P schematic

    Titolo originale

    DELL_XPS_13-9350_AAZ80_LA-C881P_r1.0_A00

    Copyright

    © © All Rights Reserved

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    This document provides information about a PCB model number AAZ80 with PCB number LA-C881P and BOM part number TBD. It includes a list of component part numbers and a schematic diagram labeling the connections between various components including the eDP panel connector, Thunderbolt, memory bus, USB ports and more. The document is confidential property of Compal Electronics and contains their secret data.

    Copyright:

    © All Rights Reserved
    Scarica in formato PDF, TXT o leggi online su Scribd
    Segnala contenuti inappropriati
    1K visualizzazioni59 pagine

    DELL XPS 13-9350 AAZ80 LA-C881P r1.0 A00

    Caricato da

    nomi_nomi
    This document provides information about a PCB model number AAZ80 with PCB number LA-C881P and BOM part number TBD. It includes a list of component part numbers and a schematic diagram labeling the connections between various components including the eDP panel connector, Thunderbolt, memory bus, USB ports and more. The document is confidential property of Compal Electronics and contains their secret data.

    Copyright:

    © All Rights Reserved
    Scarica in formato PDF, TXT o leggi online su Scribd
    Segnala contenuti inappropriati
    di 59

    A B C D E

    MODEL NAME : AAZ80


    PCB NO : LA-C881P
    BOM P/N : TBD
    ZZZ
    1 1
    R1 R3 R3 R3
    CPN DAA000AW010 DAA000AW011 DAA000AW012 DAA000AW013

    MB_PCB
    DAA000AW000

    Dell/Compal Confidential
    2 2

    Schematic Document
    Dino2 (Skylake ULT)

    3 3

    2015-09-16
    Rev: 1.0 (A00)

    4 4

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P01-Cover Page
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Wednesday, October 14, 2015 Sheet 1 of 59
    A B C D E
    A B C D E

    eDP Panel Conn. eDP 1.3

    P
    .2
    2
    DP 1.2 X2 Channel A
    Alpine Ridge
    USB TypeC Conn. Thunderbolt Memory Bus (LPDDR3) LPDDR3 8Gb or 16Gb (x32) * 2
    PCIe Gen3 X 2
    Dual Channel

    P
    .2
    6

    P
    .1
    2
    ,
    1
    4
    1 1.2V LPDDR3 1866 MHz Non-Interleave Channel B 1

    TI PD LPDDR3 8Gb or 16Gb (x32) * 2


    Controller

    P
    .1
    3
    ,
    1
    4
    Intel
    USB3.0/USB2.0
    Skylake ULT
    USB 3.0 Conn. SPI SPI ROM
    128Mb
    P
    .3
    0

    P
    .0
    8
    USB2.0
    Digital Camera
    15W TDP
    P
    .2
    2

    TPM1.2
    USB2.0 Nuvoton
    Touch Screen

    P
    .2
    7
    P
    .2
    2

    Daughter/B SATA3 X1 / PCIE X4 M.2 Socket3 M-Key


    2
    USB3.0 USB3.0 SSD 2

    USB3.0 Re-Driver

    P
    .2
    9
    USB 3.0 Conn.
    ( Power Share) USB2.0

    USB2.0 M.2 Slot A-SD


    PCIE Gen2 PCIE WLAN
    CardReader BT4.0
    RTS5242

    P
    .2
    8
    I2C
    Precision Touch Pad
    P
    .3
    5

    3 SMBus Headphone Jack 3


    HDA Audio Codec ( iPhone & Nokia compatible)

    Fan conn. ALC3246


    P
    a
    g
    e
    5
    ~
    1
    4

    P
    .2
    5
    P
    .2
    4
    P
    .2
    9

    RTC conn. LPC Bus


    Int. Speaker

    P
    .2
    5
    DC/DC Interface CKT.
    EC GPIO Extender
    P
    .3
    2
    ~
    3
    3

    I2C
    PS/2
    Power Circuit DC/DC MEC 5085 MCP 23017
    P
    .3
    6

    P
    .3
    7
    P
    .3
    8
    ~
    4
    8

    KBC/B BCBUS

    Keyboard Controller KSIO Int.KBD


    LED+DMIC/FPC ECE1117B
    4 4

    Front Side LED+DMICx2 Board DMIC

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P02-Block Diagram
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    0.6
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 2 of 59
    A B C D E
    A B C D E

    2+2 CPU Option 2+3 CPU Option AR Option


    UCPU1 QJKR_2+2@ UCPU1 QJKP_2+2@ UCPU1 QJKM_2+2@ UCPU1 QJKK_2+2@ UCPU1 QJKH_2+2@ UCPU1 QK1Q_2+3@ UCPU1 QK2S_2+3@ UT1 AR_QSJN@

    SA000092N1L SA000092O1L SA000092T1L SA000092P1L SA000092U1L SA00009CL0L SA00009E81L SA000090N3L


    FJ8066201931104 QJKR FJ8066201930409 QJKP FJ8066201924931 QJKM FJ8066201930408 QJKK FJ8066201924950 QJKH FH8066202496511 QK1Q FJ8066202496507 QK2S DSL6340 QSJN B1
    UCPU1 QK1P_2+3@ UCPU1 QK20_2+3@
    UCPU1 SR2EU_2+2@ UCPU1 SR2EY_2+2@ UCPU1 SR2F0_2+2@ UCPU1 SR2EZ_2+2@ UCPU1 SR2F1_2+2@ UT1 AR_SLL42@
    1 1

    SA00009E80L SA00009E70L
    SA000092N4L SA000092O3L SA000092T3L SA000092P3L SA000092U3L FJ8066202496507 QK1P FJ8066202499208 QK20 SA000090N5L
    FJ8066201931104 SR2EU FJ8066201930409 SR2EY FJ8066201924931 SR2F0 FJ8066201930408 SR2EZ FJ8066201924950 SR2F1 DSL6340 SLL42 B1

    DRAM Option DRAM Config Option


    MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3 MEM_CONFIG4
    UD19 M4G_1866@ UD20 M4G_1866@ UD21 M4G_1866@ UD22 M4G_1866@ RH144 M4G_1866@ RH139 M4G_1866@ RH145 M4G_1866@ RH151 M4G_1866@ RH147 M4G_1866@

    Micron 4G/1866
    SA00008PF1L SA00008PF1L SA00008PF1L SA00008PF1L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    EDF8132A3MA-JD-F-R A31! EDF8132A3MA-JD-F-R A31! EDF8132A3MA-JD-F-R A31! EDF8132A3MA-JD-F-R A31! 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

    UD19 M8G_1866@ UD20 M8G_1866@ UD21 M8G_1866@ UD22 M8G_1866@ RH129 M8G_1866@ RH150 M8G_1866@ RH145 M8G_1866@ RH151 M8G_1866@ RH147 M8G_1866@

    Micron 8G/1866
    SA00008Q11L SA00008Q11L SA00008Q11L SA00008Q11L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    EDFA232A2MA-JD-F-R A31! EDFA232A2MA-JD-F-R A31! EDFA232A2MA-JD-F-R A31! EDFA232A2MA-JD-F-R A31! 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

    UD19 H4G_1866@ UD20 H4G_1866@ UD21 H4G_1866@ UD22 H4G_1866@ RH129 H4G_1866@ RH139 H4G_1866@ RH149 H4G_1866@ RH151 H4G_1866@ RH147 H4G_1866@

    Hynix 4G/1866
    2 2
    SA00008G61L SA00008G61L SA00008G61L SA00008G61L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    H9CCNNN8GTMLAR-NUD A31!
    H9CCNNN8GTMLAR-NUD A31!
    H9CCNNN8GTMLAR-NUD A31!
    H9CCNNN8GTMLAR-NUD A31! 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    UD19 H8G_1866@ UD20 H8G_1866@ UD21 H8G_1866@ UD22 H8G_1866@ RH144 H8G_1866@ RH139 H8G_1866@ RH149 H8G_1866@ RH151 H8G_1866@ RH147 H8G_1866@

    Hynix 8G/1866

    SA00008FJ1L SA00008FJ1L SA00008FJ1L SA00008FJ1L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280


    H9CCNNNBJTMLAR-NUD A31!
    H9CCNNNBJTMLAR-NUD A31!
    H9CCNNNBJTMLAR-NUD A31!
    H9CCNNNBJTMLAR-NUD A31! 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    UD19 S4G_1866@ UD20 S4G_1866@ UD21 S4G_1866@ UD22 S4G_1866@ RH144 S4G_1866@ RH150 S4G_1866@ RH149 S4G_1866@ RH151 S4G_1866@ RH147 S4G_1866@

    Samsung 4G/1866
    SA00008PQ1L SA00008PQ1L SA00008PQ1L SA00008PQ1L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    K4E8E304EE-EGCF A31! K4E8E304EE-EGCF A31! K4E8E304EE-EGCF A31! K4E8E304EE-EGCF A31! 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    UD19 S8G_1866@ UD20 S8G_1866@ UD21 S8G_1866@ UD22 S8G_1866@ RH129 S8G_1866@ RH139 S8G_1866@ RH145 S8G_1866@ RH146 S8G_1866@ RH152 S8G_1866@

    Samsung 8G/1866
    SA00008QV1L SA00008QV1L SA00008QV1L SA00008QV1L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    K4E6E304EE-EGCF A31! K4E6E304EE-EGCF A31! K4E6E304EE-EGCF A31! K4E6E304EE-EGCF A31! 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    UD19 M16G_1866@ UD20 M16G_1866@ UD21 M16G_1866@ UD22 M16G_1866@ RH144 M16G_1866@ RH150 M16G_1866@ RH145 M16G_1866@ RH151 M16G_1866@ RH147 M16G_1866@

    Mircon 16G/1866

    3 SA00008QW1L SA00008QW1L SA00008QW1L SA00008QW1L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280 3


    EDFB232A1MA-JD-F-R A31! EDFB232A1MA-JD-F-R A31! EDFB232A1MA-JD-F-R A31! EDFB232A1MA-JD-F-R A31! 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    UD19 S16G_2133@ UD20 S16G_2133@ UD21 S16G_2133@ UD22 S16G_2133@ RH129 S16G_2133@ RH150 S16G_2133@ RH145 S16G_2133@ RH151 S16G_2133@ RH152 S16G_2133@

    Samsung 16G/2133
    SA00008VV1L SA00008VV1L SA00008VV1L SA00008VV1L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    K4EBE304EB-EGCG A31! K4EBE304EB-EGCG A31! K4EBE304EB-EGCG A31! K4EBE304EB-EGCG A31! 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    UD19 S16G_1866@ UD20 S16G_1866@ UD21 S16G_1866@ UD22 S16G_1866@ RH144 S16G_1866@ RH139 S16G_1866@ RH145 S16G_1866@ RH146 S16G_1866@ RH152 S16G_1866@

    Samsung 16G/1866
    SA00008X11L SA00008X11L SA00008X11L SA00008X11L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    K4EBE304EB-EGCF A31! K4EBE304EB-EGCF A31! K4EBE304EB-EGCF A31! K4EBE304EB-EGCF A31! 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    UD19 H16G_1866@ UD20 H16G_1866@ UD21 H16G_1866@ UD22 H16G_1866@ RH129 H16G_1866@ RH150 H16G_1866@ RH149 H16G_1866@ RH151 H16G_1866@ RH147 H16G_1866@

    Hynix 16G/1866
    SA00008YT1L SA00008YT1L SA00008YT1L SA00008YT1L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    H9CCNNNCLTMLAR-NUD A31!
    H9CCNNNCLTMLAR-NUD A31!
    H9CCNNNCLTMLAR-NUD A31!
    H9CCNNNCLTMLAR-NUD A31! 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    4 4

    LA-C881P
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P03-BoM Option
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.6
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, October 13, 2015 Sheet 3 of 59
    A B C D E
    A

    Board ID Table for AD channel USB PORT# DESTINATION

    RE79 CE54 REV 1 External USB3(On IOB)


    SKU PTT TPM2.0 PCH
    240K 4700p X00 2 External USB3(On MB)
    130K 4700p X01 USB 2.0
    Vpro+CS Disable Enable
    62K 4700p X02 Dino2 Port 3 NGFF CARD WLAN
    33K 4700p X03
    8.2K 4700p X04
    nVpro+CS Enable None Mapping 4 Touch Panel
    4.3K 4700p A00
    2K 4700p 5 Camera
    1K 4700p
    6
    BOARD_ID rise time is measured from 5%~68%.
    7
    SMBUS Control Table

    SOURCE 23017 BATTERY Charger PD 5085 XDP Audio Touch Pad

    I2C1A_CLK
    I2C1A_DATA
    MEC5085
    V
    I2C1C_CLK
    I2C1C_DATA
    MEC5085
    V PCH
    1 External USB3(On IOB)
    I2C1G_CLK
    I2C1G_DATA
    MEC5085
    V USB 3.0 2 External USB3(On MB)
    I2C2A_CLK
    I2C2A_DATA
    MEC5085
    V Port
    Mapping
    PCH_SML0CLK PCH
    PCH_SML0DATA

    PCH_SML1CLK
    PCH_SML1DATA
    PCH
    V
    DDI PORT# DESTINATION
    SMBCLK
    SMBDATA
    PCH
    V PCH
    I2C0_CLK
    I2C0_DATA
    PCH DDI 1 Alpine Ridge
    Port
    1 1

    2 Alpine Ridge
    I2C1_CLK
    I2C1_DATA
    PCH
    V Mapping

    DIFFERENTIAL CLK# DESTINATION PCI EXPRESS PORT# DESTINATION SATA PORT# DESTINATION
    CLKOUT_PCIE0 Alpine Ridge Lane 1 Alpine Ridge
    SATA-0
    CLKOUT_PCIE1 NGFF CARD WLAN Lane 2 Alpine Ridge
    SATA-1A
    CLKOUT_PCIE2 Lane 3
    SATA-1B
    CLK CLKOUT_PCIE3 M.2 SSD / PCIe Lane 4
    SATA-2 M.2 SSD
    CLKOUT_PCIE4 Lane 5 NGFF CARD WLAN

    CLKOUT_PCIE5 Card Reader Lane 6 Card Reader

    FLEX CLK# DESTINATION Lane 7 Symbol Note :

    CLKOUT_LPC_0 EC LPC Lane 8 : means Digital Ground

    CLKOUT_LPC_1 Debug Lane 9 M.2 SSD

    Lane 10 M.2 SSD

    :
    m
    e
    a
    n
    s
    A
    n
    a
    lo
    g
    G
    ro
    u
    n
    d
    Lane 11 M.2 SSD

    Lane 12 / SATA 2 M.2 SSD DELL CONFIDENTIAL/PROPRIETARY


    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P04-Notes List
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 4 of 59
    A
    5 4 3 2 1

    SIO_SLP_S4# & CPU PWR


    SM_PG_CTRL
    SY8210A SUS_ON_EC
    SY8210 PCH PWR
    +1.2V_DDR LDOIN +0.6VS
    (PU600) 5500mA (PU600) 600mA
    GPU PWR
    SIO_SLP_S0# & Peripheral Device PWR
    RUN_ON_P MPHYP_PWR_EN
    TPS22961 TPS22961
    +VCCPLL_OC +1.0V_MPHYAON +1.0V_MPHYGT
    ADAPTER (UZ22) 260mA (UZ20) 2100mA

    SIO_SLP_SUS# &
    SIO_SLP_SUS# SUS_ON_P
    D SYX196D TPS22961 D
    +1.0VA +1.0V_VCCST
    (PU700) 880mA (UZ25) 240mA
    SIO_SLP_S0# &
    RUN_ON_P SIO_SLP_S0# &
    TPS62134A RUN_ON_P
    +1.0VS_VCCIO TPS22961
    (PU1400) 3100mA
    +1.0V_VCCSTG
    (UZ19) 40mA

    CHARGER SIO_SLP_SUS# RUN_ON_P


    TPS62134B AOZ1331
    BQ24777 +1.0V_PRIM_CORE +5VS
    (PU1401) 2570mA (U719) 200mA
    (PU300)
    AUD_PWR_EN
    ALWON AOZ1331
    SY8288C +5VS_AUDIO
    +5VALW (U719) 3150mA
    (PU501) 530mA

    B+
    USB_PWR_SHR_VBUS_EN_R
    TPS2544
    +5V_USB_P1
    TLV62150R SIO_SLP_SUS# (US1) 2430mA
    BATTERY +1.8VA
    (PU800) 210mA
    USB2_EN
    G547I1P
    +5V_USB_P2
    C (US2) 2000mA
    C

    AUD_PWR_EN
    SY8286B AOZ1331
    +1.8VS_AUDIO
    (PU500) (U664) 400mA

    ALWON
    ENVDD
    590mA +3VALW TPS22961
    +LCDVDD +V1.8S_EDRAM
    (UZ24) 545mA

    TP_PW_EN
    AOZ1331
    +3VS_TP
    TPS62134C IMVP_VR_ON (U716) 35mA
    +VCC_EDRAM
    (PU1500) 2500mA SD_PWR_EN

    1200mA +3VS_CR
    PCH_PWR_EN
    IMVP_VR_ON (SIO_SLP_SUS#)
    TPS62134C AOZ1331
    +VCC_EOPIO +3V_PCH
    (PU1501) 2000mA (U717) 535mA
    RUN_ON_P
    B 2500mA +3.3VDX_SSD B

    AUX_EN_WOWL
    AOZ1331
    +3VS_NGFF
    (U720) 620mA
    RUN_ON_P
    TLV62150R
    +3VS
    (PU900) 480mA
    EN_CAM
    AOZ1331
    +3VS_CAM
    (U718) 300mA
    3.3V_TS_EN
    SUS_ON_P

    660mA

    45mA +3VS_TS
    AUD_PWR_EN
    AOZ1331
    +3VS_AUDIO
    (U664) 50mA

    ISL95857 Si3457BDV SUS_ON_P


    TPS22961
    (PU1000) (Q70) +3V_TBT
    (UZ23) 600mA
    IMVP_VR_ON

    EN_INVPWR

    590mA
    5100mA

    IMVP_VR_ON

    IMVP_VR_ON
    64000mA

    29000mA

    A A

    +INV_PWR_SRC +1.8VU DELL CONFIDENTIAL/PROPRIETARY


    +VCC_SA +VCC_GT +VCC_CORE
    Compal Electronics, Inc.
    PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
    TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT P05-Power rails
    BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
    NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
    PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 5 of 59
    5 4 3 2 1
    5 4 3 2 1

    1K 2.2K

    1K
    +3V_PCH 2.2K
    +3VS
    R7 MEM_SMBCLK 53
    MEM_SMBDATA
    2N7002 51
    R8 XDP
    2N7002

    D
    SKL-U D

    R9
    W2
    W3 V3
    1K
    SML1_SMBDATA

    SML1_SMBCLK
    +3V_PCH
    1K

    A5 B6 2.2K

    3A 3A
    2.2K +3VALW_5085
    B4 USBC_MCP23017_SMBCLK 8
    1A
    9 MCP_23017
    1A A3 USBC_MCP23017_SMBDAT

    K2
    C L2 C
    PD_Debug

    B5 3
    1B
    A4 6 DBC Buffer
    1B
    2.2K

    KBC 2.2K
    +3VALW_5085
    100 ohm 3
    1C A56 PBAT_SMBCLK
    100 ohm 4 BATTERY
    1C B59 PBAT_SMBDAT CONN
    2.2K

    +3VALW_5085
    2.2K
    B49 B5
    2A UPD_SMBCLK
    MEC 5085 2A
    B48
    UPD_SMBDAT
    A1 UPD
    B B

    2B A49

    2B B52

    8.2K
    8.2K
    +3VALW_5085
    B50 12
    1G CHARGER_SMBCLK
    A47 11 Charger
    1G CHARGER_SMBDAT

    2D B7
    A A
    2D A7

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    2A Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P06-SMBus block diagram
    2A Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 6 of 59
    5 4 3 2 1
    5 4 3 2 1

    @ UCPU1A SKL-U

    E55 C47
    <39> DDI1_PTX_TBRX_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 eDP_TXN_P0 <25>
    <39> DDI1_PTX_TBRX_P0 E58 DDI1_TXP[0] EDP_TXP[0] D46 eDP_TXP_P0 <25>
    <39> DDI1_PTX_TBRX_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 eDP_TXN_P1 <25>
    <39> DDI1_PTX_TBRX_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 eDP_TXP_P1 <25> Support QHD
    <39> DDI1_PTX_TBRX_N2 G53 DDI1_TXN[2] EDP_TXN[2] B45 eDP_TXN_P2 <25>
    <39> DDI1_PTX_TBRX_P2 F56 DDI1_TXP[2] EDP_TXP[2] A47 eDP_TXP_P2 <25>
    <39> DDI1_PTX_TBRX_N3 G56 DDI1_TXN[3] EDP_TXN[3] B47 eDP_TXN_P3 <25>
    <39> DDI1_PTX_TBRX_P3 DDI1_TXP[3] EDP_TXP[3] eDP_TXP_P3 <25>
    D C50 E45 D
    Alpine Ridge <39> DDI2_PTX_TBRX_N0 D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 eDP_AUXN <25>
    <39> DDI2_PTX_TBRX_P0 C52 DDI2_TXP[0] EDP_AUXP eDP_AUXP <25>
    <39> DDI2_PTX_TBRX_N1 D52 DDI2_TXN[1] B52
    <39> DDI2_PTX_TBRX_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
    <39> DDI2_PTX_TBRX_N2 B50 DDI2_TXN[2] G50
    <39> DDI2_PTX_TBRX_P2 D51 DDI2_TXP[2] DDI1_AUXN F50 CPU_DDI1_AUXN <39>
    +3VS
    <39> DDI2_PTX_TBRX_N3 C51 DDI2_TXN[3] DDI1_AUXP E48 CPU_DDI1_AUXP <39>
    <39> DDI2_PTX_TBRX_P3 DDI2_TXP[3] DDI2_AUXN F48 CPU_DDI2_AUXN <39>
    2 1 CPU_DP1_CTRL_CLK DDI2_AUXP G46 CPU_DDI2_AUXP <39> 2 1
    EDP_HPD
    DISPLAY SIDEBANDS DDI3_AUXN F46 PAD~D @ T1
    RC175 2.2K_0402_5% 100K_0402_5% RC1
    2 1 CPU_DP1_CTRL_DATA CPU_DP1_CTRL_CLK L13 DDI3_AUXP PAD~D @ T2 CPU_DP1_HPD 2 1
    RC178 2.2K_0402_5% <39> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9 CPU_DP1_HPD 100K_0402_5% RC312
    2 1 CPU_DP2_CTRL_CLK <39> CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_DP2_HPD CPU_DP1_HPD <39> CPU_DP2_HPD 2 1
    CPU_DP2_CTRL_CLK N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_HPD <39>
    RC176 2.2K_0402_5% 100K_0402_5% RC242
    2 1 CPU_DP2_CTRL_DATA <39> CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9
    <39> CPU_DP2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EDP_HPD
    RC177 2.2K_0402_5%
    N11 GPP_E17/EDP_HPD EDP_HPD <25>
    N12 GPP_E22/DDPD_CTRLCLK R12
    GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R11 PANEL_BKLEN <25>
    RC2 1 2 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 EDP_BIA_PWM <25>
    +1.0VS_VCCIO EDP_RCOMP EDP_VDDEN ENVDD_PCH <33,37>
    1 OF 20
    SKL-U_BGA1356
    COMPENSATION PU FOR eDP
    CAD Note:Trace width=20 mils, Isolation Spacing=25mil, SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
    Max length=100 mils.

    C C

    SKL_ULT
    @ UCPU1I

    CSI-2

    A36 C37
    B36 CSI2_DN0 CSI2_CLKN0 D37
    C38 CSI2_DP0 CSI2_CLKP0 C32
    D38 CSI2_DN1 CSI2_CLKN1 D32 GPIO Pin Pin Name Micron 4G Micron 8G Mircon 16G Hynix 4G Hynix 8G Hynix 16G Samsung 4G Samsung 8G Samsung 16G
    C36 CSI2_DP1 CSI2_CLKP1 C29
    D36 CSI2_DN2 CSI2_CLKN2 D29
    A38 CSI2_DP2 CSI2_CLKP2 B26 GPP_D5 MEM_CONFIG0 0 1 0 1 0 1 0 1 0
    B38 CSI2_DN3 CSI2_CLKN3 A26
    CSI2_DP3 CSI2_CLKP3
    C31 E13 CSI2_COMP 1 2 GPP_D6 MEM_CONFIG1 0 0 1 1 0 0 1 1 0
    D31 CSI2_DN4 CSI2_COMP B7 RC3 100_0402_1%
    C33 CSI2_DP4 GPP_D4/FLASHTRIG
    1600 Mbps
    D33 CSI2_DN5 GPP_D7 MEM_CONFIG2 0 0 0 0 1 1 1 1 0
    A31 CSI2_DP5 EMMC
    B31 CSI2_DN6 AP2 MEM_CONFIG0
    A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1 MEM_CONFIG1 GPP_D8 MEM_CONFIG3 0 0 0 0 0 0 0 0 1
    B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3 MEM_CONFIG2
    CSI2_DP7 GPP_F15/EMMC_DATA2 AN3 MEM_CONFIG3
    A29 GPP_F16/EMMC_DATA3 AN1 MEM_CONFIG4 GPP_D9 MEM_CONFIG4 0 0 0 0 0 0 0 0 0
    B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
    C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
    D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
    B A27 CSI2_DP9 GPP_F20/EMMC_DATA7 GPIO Pin Pin Name Micron 4G Micron 8G Mircon 16G Hynix 4G Hynix 8G Hynix 16G Samsung 4G Samsung 8G Samsung 16G B
    B27 CSI2_DN10 AM2
    C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
    D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4 GPP_D5 MEM_CONFIG0 1 0 1 0 1 0 1 0 1
    CSI2_DP11 GPP_F12/EMMC_CMD
    AT1 EMMC_RCOMP 1 2
    EMMC_RCOMP RC4 200_0402_1% GPP_D6 MEM_CONFIG1 0 1 1 0 0 1 1 0 0
    SKL-U_BGA1356 9 OF 20
    1866 Mbps
    GPP_D7 MEM_CONFIG2 0 0 0 1 1 1 1 0 0

    GPP_D8 MEM_CONFIG3 1 1 1 1 1 1 1 0 0

    DDR Memory Configuratino Type Strap pin GPP_D9 MEM_CONFIG4 0 0 0 0 0 0 0 1 1


    +1.8VA

    @RH144
    @ RH144 2 1 10K_0402_5% MEM_CONFIG0 @ RH129 2 1 10K_0402_5% GPIO Pin Pin Name Micron 4G Micron 8G Mircon 16G Hynix 4G Hynix 8G Hynix 16G Samsung 4G Samsung 8G Samsung 16G

    @RH150
    @ RH150 2 1 10K_0402_5% MEM_CONFIG1 @ RH139 2 1 10K_0402_5%
    GPP_D5 MEM_CONFIG0 0 1 0 1 0 1 0 1 0
    @RH149
    @ RH149 2 1 10K_0402_5% MEM_CONFIG2 @ RH145 2 1 10K_0402_5%

    @RH151
    @ RH151 2 1 10K_0402_5% MEM_CONFIG3 @ RH146 2 1 10K_0402_5% GPP_D6 MEM_CONFIG1 1 1 0 0 1 1 0 0 1
    @RH152
    @ RH152 2 1 10K_0402_5% MEM_CONFIG4 @ RH147 2 1 10K_0402_5% 2133 Mbps
    GPP_D7 MEM_CONFIG2 0 0 1 1 1 1 0 0 0

    GPP_D8 MEM_CONFIG3 0 0 0 0 0 0 1 1 1
    A A

    GPP_D9 MEM_CONFIG4 1 1 1 1 1 1 1 1 1

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P07-MCP(1/14)DDI,EDP,CSI2,EMMC
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 7 of 59
    5 4 3 2 1
    5 4 3 2 1

    LPDDR3, Ballout for side by side(Non-Interleave)

    SKL-U
    @ UCPU1B SKL-U @ UCPU1C

    AU53 DDR_A_CLK#0
    <21> DDR_A_D[0..15] DDR_A_D0 AL71 DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_A_CLK#0 <21,23> <21> DDR_A_D[16..31] DDR_A_D16 AF65 AN45 DDR_B_CLK#0
    AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDR_A_CLK0 <21,23> AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#0 <22,23>
    DDR_A_D1 DDR_A_CLK#1 DDR_A_D17 DDR_B_CLK#1
    DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 <21,23> DDR_A_D18 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 <22,23>
    D AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 <21,23> AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK0 <22,23> D
    DDR_A_D3 DDR_A_D19 DDR_B_CLK1
    DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDR_A_CKE0 DDR_A_D20 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <22,23>
    DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 <21,23> DDR_A_D21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
    DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 <21,23> DDR_A_D22 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 <22,23>
    AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_A_CKE2 <21,23> AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE1 <22,23>
    DDR_A_D7 DDR_A_CKE3 DDR_A_D23 DDR_B_CKE2
    AR70 DDR0_DQ[7] DDR0_CKE[3] DDR_A_CKE3 <21,23> AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_CKE2 <22,23>
    DDR_A_D8 DDR_A_D24 DDR_B_CKE3
    DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_A_D25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] DDR_B_CKE3 <22,23>
    DDR_A_D10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <21,23> DDR_A_D26 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
    DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 <21,23> DDR_A_D27 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 <22,23>
    AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDR_A_ODT0 <21,23> AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_CS#1 <22,23>
    DDR_A_D12 DDR_A_D28 DDR_B_ODT0
    AR69 DDR0_DQ[12] DDR0_ODT[1] AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT0 <22,23>
    DDR_A_D13 DDR_A_D29
    DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_D30 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
    DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_CA1_0 <21,23> DDR_A_D31 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
    <21> DDR_A_D[32..47] DDR_A_D32 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_CA1_1 <21,23> <21> DDR_A_D[48..63] DDR_A_D48 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_CA1_0 <22,23>
    DDR_A_D33 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_CA1_2 <21,23> DDR_A_D49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_CA1_1 <22,23>
    AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_CA1_3 <21,23> AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_CA1_2 <22,23>
    DDR_A_D34 DDR_A_D50
    DDR_A_D35 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_CA1_4 <21,23> DDR_A_D51 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_CA1_3 <22,23>
    DDR_A_D36 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_CA1_5 <21,23> DDR_A_D52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_CA1_4 <22,23>
    DDR_A_D37 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_CA1_6 <21,23> DDR_A_D53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_CA1_5 <22,23>
    DDR_A_D38 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_CA1_7 <21,23> DDR_A_D54 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_CA1_6 <22,23>
    DDR_A_D39 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_CA1_8 <21,23> DDR_A_D55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_CA1_7 <22,23>
    DDR_A_D40 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_CA1_9 <21,23> DDR_A_D56 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_CA1_8 <22,23>
    DDR_A_D41 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_D57 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_CA1_9 <22,23>
    BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CA2_0 <21,23> AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
    DDR_A_D42 DDR_A_D58
    DDR_A_D43 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_CA2_1 <21,23> DDR_A_D59 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CA2_0 <22,23>
    DDR_A_D44 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_CA2_2 <21,23> DDR_A_D60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_CA2_1 <22,23>
    DDR_A_D45 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_CA2_3 <21,23> DDR_A_D61 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_CA2_2 <22,23>
    DDR_A_D46 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_CA2_4 <21,23> DDR_A_D62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_CA2_3 <22,23>
    AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_CA2_5 <21,23> AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_CA2_4 <22,23>
    DDR_A_D47 DDR_A_D63
    <22> DDR_B_D[0..15] DDR_B_D0 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_CA2_6 <21,23> <22> DDR_B_D[16..31] DDR_B_D16 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_CA2_5 <22,23>
    DDR_B_D1 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_CA2_7 <21,23> DDR_B_D17 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_CA2_6 <22,23>
    DDR_B_D2 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_CA2_8 <21,23> DDR_B_D18 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_CA2_7 <22,23>
    C DDR_B_D3 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_CA2_9 <21,23> DDR_B_D19 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_CA2_8 <22,23> C
    DDR_B_D4 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_B_D20 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_CA2_9 <22,23>
    DDR_B_D5 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_B_D21 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47
    DDR_B_D6 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_B_D22 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
    DDR_B_D7 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS#0 <21> DDR_B_D23 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66
    DDR_B_D8 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS0 <21> DDR_B_D24 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_A_DQS#2 <21>
    DDR_B_D9 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS#1 <21> DDR_B_D25 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_A_DQS2 <21>
    AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS1 <21> AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_A_DQS#3 <21>
    DDR_B_D10 DDR_B_D26
    AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS#4 <21> AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_A_DQS3 <21>
    DDR_B_D11 DDR_B_D27
    DDR_B_D12 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS4 <21> DDR_B_D28 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_A_DQS#6 <21>
    DDR_B_D13 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS#5 <21> DDR_B_D29 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_A_DQS6 <21>
    BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_A_DQS5 <21> AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_A_DQS#7 <21>
    DDR_B_D14 DDR_B_D30
    BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_B_DQS#0 <22> AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_A_DQS7 <21>
    DDR_B_D15 DDR_B_D31
    <22> DDR_B_D[32..47] AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_B_DQS0 <22> <22> DDR_B_D[48..63] AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS#2 <22>
    DDR_B_D32 DDR_B_D48
    DDR_B_D33 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_B_DQS#1 <22> DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS2 <22>
    DDR_B_D34 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_B_DQS1 <22> DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS#3 <22>
    AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_B_DQS#4 <22> AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS3 <22>
    DDR_B_D35 DDR_B_D51
    DDR_B_D36 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_B_DQS4 <22> DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS#6 <22>
    BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_B_DQS#5 <22> AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS6 <22>
    DDR_B_D37 DDR_B_D53
    DDR_B_D38 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_DQS5 <22> DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS#7 <22>
    DDR_B_D39 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7] DDR_B_DQS7 <22>
    AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 PAD~D @ T19 AT22 DDR1_DQ[55] AN43
    DDR_B_D40 DDR_B_D56
    DDR_B_D41 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR PAD~D @ T7 DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 PAD~D @ T21
    DDR_B_D42 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 PAD~D @ T8
    DDR_B_D43 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68 +V_DDR_REF_CA <23> DDR_B_D59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP0 PAD~D @ T18
    DDR_B_D44 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ BA67 +V_DDR_REFA_R <23> DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1
    DDR CH - A
    DDR_B_D45 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +V_DDR_REFB_R <23> DDR_B_D61 AP22 DDR1_DQ[60] DDR CH - B DDR_RCOMP[1] AU18 SM_RCOMP2
    DDR_B_D46 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
    DDR_B_D47 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 AN21 DDR1_DQ[62]
    DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63]

    SKL-U_BGA1356 2 OF 20 SKL-U_BGA1356 3 OF 20
    B B

    +1.2V_DDR

    UC2
    1 5
    NC VCC
    DDR_VTT_CNTL 2
    A 4
    1
    @ +3VS
    LPDDR3 COMPENSATION SIGNALS
    3 Y CC240
    GND 0.1U_0402_10V7K SM_RCOMP0 RC5 1 2 200_0402_1%
    1

    74AUP1G07GW_TSSOP5 2
    RE60 SM_RCOMP1 RC6 1 2 80.6_0402_1%
    100K_0402_5%
    SM_RCOMP2 RC7 1 2 162_0402_1%
    2

    SM_PG_CTRL <49> CAD Note:


    Trace width=12~15 mil, Spacing=20 mils
    Max trace length= 500 mil

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P08-MCP(2/14)LPDDR3
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 8 of 59
    5 4 3 2 1
    5 4 3 2 1

    +3VS
    SPI_MOSI= SPI_IO0
    SPI_MISO= SPI_IO1
    PCH EDS R0.7 p.235~236 @ UCPU1E
    SKL-U

    2
    SPI - FLASH
    SMBUS, SMLINK
    PCH_SPI_CLK AV2 MEM_SMBCLK 6 1 DDR_XDP_SMBCLK
    PCH_SPI_SO AW3 SPI0_CLK R7 MEM_SMBCLK DDR_XDP_SMBCLK <15>
    RC10 1 2 1K_0402_1% PCH_SPI_SI AV3 SPI0_MISO GPP_C0/SMBCLK R8 MEM_SMBDATA QC2A
    <15> PCH_SPI_DO_XDP SPI0_MOSI GPP_C1/SMBDATA

    5
    RC11 1 2 1K_0402_1% PCH_SPI_IO2 AW2 R10 PCH_SMB_ALERT# DMN66D0LDW-7_SOT363-6
    <15> PCH_SPI_DO2_XDP PCH_SPI_IO3 AU4 SPI0_IO2 GPP_C2/SMBALERT#
    PCH_SPI_CS0# AU3 SPI0_IO3 R9 MEM_SMBDATA 3 4 DDR_XDP_SMBDAT
    D AU2 SPI0_CS0# GPP_C3/SML0CLK W2 DDR_XDP_SMBDAT <15> D
    AU1 SPI0_CS1# GPP_C4/SML0DATA W1 GPP_C5 QC2B
    <28> PCH_SPI_CS2# SPI0_CS2# GPP_C5/SML0ALERT# DMN66D0LDW-7_SOT363-6 +3VS
    W3 SML1_SMBCLK
    SPI - TOUCH GPP_C6/SML1CLK V3 SML1_SMBDAT SML1_SMBCLK <37>
    M2 GPP_C7/SML1DATA AM7 SML1_SMBDAT <37> 2 1
    GPP_B23 DDR_XDP_SMBDAT
    M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# 2.2K_0402_5% RN19
    <28> TPM_PIRQ# J4 GPP_D2/SPI1_MISO DDR_XDP_SMBCLK 2 1
    V1 GPP_D3/SPI1_MOSI 2.2K_0402_5% RN20
    V2 GPP_D21/SPI1_IO2 CLKRUN# 2 1
    M1 GPP_D22/SPI1_IO3 8.2K_0402_5% RC27
    LPC
    <24> MEDIACARD_IRQ# GPP_D0/SPI1_CS# AY13
    GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD0 <37>
    +3V_PCH
    C LINK GPP_A2/LAD1/ESPI_IO1 BB13 LPC_AD1 <37>
    G3 GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD2 <37> +3V_PCH
    <29> CL_CK CL_CLK GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <37>
    RC13 1 2 10K_0402_5% MEDIACARD_IRQ# G2 BA12
    <29> CL_DAT G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 LPC_FRAME# <37>
    <29> CL_RST# CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# MEM_SMBCLK 1 2
    +3VS RC12 1K_0402_5%
    SIO_RCIN# AW13 AW9 PCI_CLK_LPC0 RC18 1 2 22_0402_5% MEM_SMBDATA 1 2
    <37> SIO_RCIN# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_MEC <37>
    RC16 1 2 10K_0402_5% SIO_RCIN# AY9 PCI_CLK_LPC1 RC22 1 2 22_0402_5% RC14 1K_0402_5%
    IRQ_SERIRQ AY11 GPP_A10/CLKOUT_LPC1 AW11 CLKRUN# CLK_LPC_DEBUG <37> SML1_SMBCLK 1 2
    <37> IRQ_SERIRQ GPP_A6/SERIRQ GPP_A8/CLKRUN# CLKRUN# <37>
    RC21 1 2 10K_0402_1% IRQ_SERIRQ RC15 1K_0402_5%
    SML1_SMBDAT 1 2
    SKL-U_BGA1356 5 OF 20 RC17 1K_0402_5%

    C C

    RP5 CLK_PCI_MEC 2 1 +3V_PCH


    SPI_SI_VROM 1 8 PCH_SPI_SI 12P_0402_50V8J @
    SPI_CLK_VROM 2 7 PCH_SPI_CLK CC4
    3 6
    <28> PCH_SPI_CLK_TPM
    +3V_PCH 4 5 CLK_LPC_DEBUG 2 1 PCH_SMB_ALERT# 1 2
    <28> PCH_SPI_SI_TPM
    12P_0402_50V8J @ RC23 8.2K_0402_5%
    CC9 33_8P4R_5% CC5
    1 2
    TLS CONFIDENTIALITY
    128Mb Flash ROM 0.1U_0402_25V6 HIGH ENABLE
    UH8 RP6
    PCH_SPI_CS0# 1
    /CS VCC
    8
    <28> PCH_SPI_SO_TPM
    1 8 PCH_SPI_SO LOW(DEFAULT) DISABLE
    SPI_SO_VROM 2 7 SPI_IO3_VROM SPI_SO_VROM 2 7
    SPI_IO2_VROM 3 DO(IO1) /HOLD(IO3) 6 SPI_CLK_VROM SPI_IO2_VROM 3 6 PCH_SPI_IO2 Reserve for RF
    4 /WP(IO2) CLK 5 SPI_SI_VROM SPI_IO3_VROM 4 5 PCH_SPI_IO3
    GND DI(IO0)
    W25Q128FVSIQ_SO8 33_8P4R_5% +3V_PCH

    GPP_C5 1 2
    @ RC25 10K_0402_5%
    +3V_PCH

    RH59 1
    @RH59
    @ 2 1K_0402_5%~D PCH_SPI_IO2
    EC interface
    HIGH ESPI
    B SPI_CLK_VROM RH58 1
    @RH58
    @ 2 1K_0402_5%~D PCH_SPI_IO3 LOW(DEFAULT) LPC B
    2
    33_0402_5%

    RH56 1
    @RH56
    @ 2 1K_0402_5%~D PCH_SPI_IO3
    +3V_PCH
    @ RC29
    1

    GPP_B23 1 2
    9/5 MOW
    33P_0402_50V8J

    @ RC26 4.7K_0402_5%
    Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the
    2

    @ CC8

    required 1 kOhm pull-up resistor(MOW WW5).


    EXI BOOT STALL BYPASS
    In this case, customers must ensure that the SPI
    1

    flash device on the platform has HOLD functionality disabled by default. HIGH ENABLE
    LOW(DEFAULT) DISABLE
    Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms
    with ES and SKL S/H platforms with pre-ES1/ES1 samples(MOW WW9).

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P09-MCP(3/14)SPI,SMB,LPC
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 9 of 59
    5 4 3 2 1
    5 4 3 2 1

    @ UCPU1F SKL-U

    LPSS ISH

    +3VS AN8 +3VS


    AP7 GPP_B15/GSPI0_CS# P2
    AP8 GPP_B16/GSPI0_CLK GPP_D9 P3
    1 2 HOST_SD_WP# NRB_BIT AR7 GPP_B17/GSPI0_MISO GPP_D10 P4 DDR_CHA_EN RH440 1 2 100K_0402_5%~D
    RC292 10K_0402_5% GPP_B18/GSPI0_MOSI GPP_D11 P1
    AM5 GPP_D12 DDR_CHB_EN RH441 1 2 100K_0402_5%~D
    D 1 2 SIO_EXT_SCI# SIO_EXT_SCI# AN7 GPP_B19/GSPI1_CS# M4 D
    <37> SIO_EXT_SCI# AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3
    RC237 10K_0402_5%
    <33> 3.3V_TS_EN GPP_B22 AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL DDR_CHA_EN 1 2 SHORT PADS
    @RH442
    @ RH442
    1 2 UART1_TXD GPP_B22/GSPI1_MOSI N1
    RH562 49.9K_0402_1% AB1 GPP_D7/ISH_I2C1_SDA N2 DDR_CHB_EN @RH443
    @ RH443 1 2 SHORT PADS
    AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL
    1 2 UART1_RXD <37> UART0_TX W4 GPP_C9/UART0_TXD AD11
    RH563 49.9K_0402_1% HOST_SD_WP# AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
    <24> HOST_SD_WP# GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
    AD1
    AD2 GPP_C20/UART2_RXD U1 DDR_CHB_EN
    SIO_EXT_WAKE# AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 DDR_CHA_EN
    <37> SIO_EXT_WAKE# AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
    T125@ PAD~D GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4
    GPP_D16/ISH_UART0_CTS#/SML0BALERT#
    U7 AC1 UART1_RXD
    <25> I2C0_SDA_EDP_PCH U6 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 UART1_TXD
    <25> I2C0_SCK_EDP_PCH GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3
    I2C1_SDA_TP U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 PAD~D @ T124
    <36> I2C1_SDA_TP I2C1_SCK_TP U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
    <36> I2C1_SCK_TP GPP_C19/I2C1_SCL AY8
    AH9 GPP_A18/ISH_GP0 BA8 PAD~D @ T121
    +3V_PCH AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7 KB_DET#
    GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 KB_DET# <35>
    AH11 GPP_A21/ISH_GP3 AY7 USB2_PWR_EN AUD_PWR_EN <33>
    1 2 SIO_EXT_WAKE# AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7 TBT_PWR_EN USB2_PWR_EN <31>
    RC283 10K_0402_5% GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13 TPM_DET
    AF11 GPP_A12/BM_BUSY#/ISH_GP6
    1 2 KB_DET# AF12 GPP_F8/I2C4_SDA
    RC288 100K_0402_5%~D GPP_F9/I2C4_SCL

    1 2 I2C1_SDA_TP SKL-U_BGA1356 6 OF 20
    C RC284 4.7K_0402_5% C

    1 2 I2C1_SCK_TP
    RC285 4.7K_0402_5%

    1 2 USB2_PWR_EN
    RC293 10K_0402_5%

    2 1 TBT_PWR_EN
    RH556 100K_0402_5%~D

    TPM@ +3V_PCH

    TPM_DET 100K_0402_5% 2 1 RH148

    TPM_DET 100K_0402_5% 1 2 RH153

    +3V_PCH TPM BOM Optional


    TPM_DET
    1 2 NRB_BIT
    @ RC186 4.7K_0402_5%
    TPM 1 = W/TPM
    NO REBOOT STRAP 0 = W/O TPM
    HIGH No REBOOT
    B LOW(DEFAULT) REBOOT ENABLE B

    Weak IPD

    +5VS

    JUART
    1
    UART1_TXD 2 1
    UART1_RXD 3 2
    +3V_PCH 4 3
    4
    5
    6 GND
    GND
    1

    @ RC184 ACES_50207-00471-P01
    8.2K_0402_5% CONN@
    2

    GPP_B22

    BOOT BIOS Destination(Bit 6)


    HIGH LPC
    LOW(DEFAULT) SPI

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P10-MCP(4/14)GSPI,I2C,UART,ISH
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 10 of 59
    5 4 3 2 1
    5 4 3 2 1

    @ UCPU1H SKL-U

    SSIC / USB3
    PCIE/USB3/SATA
    H8
    USB3_1_RXN USB3RN1 <24>
    G8
    USB3_1_RXP USB3RP1 <24>
    H13 C13 USB3.0 IO/B Side
    D <39> PCIE_PRX_TBTX_N1 PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3TN1 <24> D
    G13 D13
    <39> PCIE_PRX_TBTX_P1 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3TP1 <24>
    B17
    <39> PCIE_PTX_TBRX_N1 PCIE1_TXN/USB3_5_TXN
    A17 J6
    Alpine Ridge <39> PCIE_PTX_TBRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6
    USB3RN2 <31>
    USB3_2_RXP/SSIC_1_RXP USB3RP2 <31>
    PCIe Gen3 x 2 <39> PCIE_PRX_TBTX_N2
    G11
    PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN
    B13
    USB3TN2 <31> USB3.0 M/B Side
    F11 A13
    <39> PCIE_PRX_TBTX_P2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3TP2 <31>
    D16
    <39> PCIE_PTX_TBRX_N2 PCIE2_TXN/USB3_6_TXN
    C16 J10
    <39> PCIE_PTX_TBRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
    H16 USB3_3_RXP/SSIC_2_RXP B15
    G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
    D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
    C17 PCIE3_TXN E10
    PCIE3_TXP USB3_4_RXN F10
    G15 USB3_4_RXP C15
    F15 PCIE4_RXN USB3_4_TXN D15
    B19 PCIE4_RXP USB3_4_TXP
    A19 PCIE4_TXN AB9
    PCIE4_TXP USB2N_1 USB20_N1 <24>
    AB10 USB2.0 IO/B Side
    USB2P_1 USB20_P1 <24>
    F16
    <29> PCIE_PRX_WLANTX_N5 PCIE5_RXN
    E16 AD6
    WLAN <29> PCIE_PRX_WLANTX_P5
    C19 PCIE5_RXP USB2N_2 AD7
    USB20_N2 <31>
    PCIe Gen2 x 1 <29> PCIE_PTX_WLANRX_N5
    D19 PCIE5_TXN USB2P_2 USB20_P2 <31> USB2.0 M/B Side
    <29> PCIE_PTX_WLANRX_P5 PCIE5_TXP AH3
    USB2N_3 USB20_N3 <29>
    G18 AJ3 NGFF (WLAN)
    <24> PCIE_PRX_CARDTX_N6 PCIE6_RXN USB2P_3 USB20_P3 <29>
    F18
    Cardreader <24> PCIE_PRX_CARDTX_P6
    D20 PCIE6_RXP AD9
    <24> PCIE_PTX_CARDRX_N6 PCIE6_TXN USB2N_4 USB20_N4 <25>
    PCIe Gen2 x 1 <24> PCIE_PTX_CARDRX_P6
    C20
    PCIE6_TXP USB2P_4
    AD10
    USB20_P4 <25> Touch Panel
    F20 AJ1
    PCIE7_RXN/SATA0_RXN USB2N_5 USB20_N5 <25>
    E20 AJ2 Camera
    PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <25>
    B21 USB2
    C A21 PCIE7_TXN/SATA0_TXN AF6 C
    PCIE7_TXP/SATA0_TXP USB2N_6 AF7
    G21 USB2P_6
    F21 PCIE8_RXN/SATA1A_RXN AH1
    D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2
    C21 PCIE8_TXN/SATA1A_TXN USB2P_7
    PCIE8_TXP/SATA1A_TXP AF8
    E22 USB2N_8 AF9
    <30> PCIE_PRX_SSDTX_N9 PCIE9_RXN USB2P_8
    E23
    <30> PCIE_PRX_SSDTX_P9 PCIE9_RXP
    B23 AG1
    <30> PCIE_PTX_SSDRX_N9 PCIE9_TXN USB2N_9
    A23 AG2
    <30> PCIE_PTX_SSDRX_P9 PCIE9_TXP USB2P_9
    F25 AH7
    <30> PCIE_PRX_SSDTX_N10 PCIE10_RXN USB2N_10
    E25 AH8
    <30> PCIE_PRX_SSDTX_P10 PCIE10_RXP USB2P_10
    D23
    <30> PCIE_PTX_SSDRX_N10 PCIE10_TXN
    C23 AB6 USBCOMP RC44 1 2 113_0402_1%
    <30> PCIE_PTX_SSDRX_P10 PCIE10_TXP USB2_COMP AG3 USB2_ID RC19 1 @ 2 0_0402_1%
    M.2 SSD PCIE_RCOMPN F5 USB2_ID AG4 VBUSSENSE RC20 1 2 1K_0402_5%
    PCIe Gen3 x 4 RC45 1 2 100_0402_1% PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
    +3VS PCIE_RCOMPP A9 TBT_USB_OC0#
    D56 GPP_E9/USB2_OC0# C9 USB_OC1# TBT_USB_OC0# <41>
    <15> CPU_XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC1# <24>
    USB_OC2#
    RC245 1 2 10K_0402_5%<15> CPU_XDP_PRDY# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# USB_OC2# <31>
    GPP_A7/PIRQA# GPP_E12/USB2_OC3#
    E28 J1
    <30> PCIE_PRX_SSDTX_N11 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0
    E27 J2
    <30> PCIE_PRX_SSDTX_P11 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1
    D24 J3
    <30> PCIE_PTX_SSDRX_N11 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 SSD_DEVSLP <30>
    C24
    <30> PCIE_PTX_SSDRX_P11 PCIE11_TXP/SATA1B_TXP
    E30 H2
    <30> SATA_PRX_SSDTX_N2 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0
    F30 H3 GPP_E1 1 2
    <30> SATA_PRX_SSDTX_P2 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1
    SATA SSD <30> SATA_PTX_SSDRX_N2
    A25
    B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
    G4 RC51 0_0201_5%
    SSD_IFDET <30>
    B <30> SATA_PTX_SSDRX_P2 PCIE12_TXP/SATA2_TXP B
    H1
    GPP_E8/SATALED# R07_0720: Add GPIO to disable SATA#1
    SKL-U_BGA1356 8 OF 20
    +3V_PCH

    TBT_USB_OC0# 1 2
    RC189 10K_0402_5%
    USB_OC1# 1 2
    RC185 10K_0402_5%
    USB_OC2# 1 2
    RC188 10K_0402_5%
    USB_OC3# 1 2
    RC191 10K_0402_5%

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P11-MCP(5/14)PCIE,USB,SATA
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 11 of 59
    5 4 3 2 1
    5 4 3 2 1

    CC21
    1 2
    SUSCLK 1 2
    @ RC48 1K_0402_5% 15P_0402_50V8J

    2
    1M_0402_1%

    3
    4
    RC46
    @ UCPU1J SKL_ULT
    YC1
    CLOCK SIGNALS 24MHZ_12PF_X3G024000DC1H

    1
    2
    D42
    <39> CLK0_PCIE_TBT# C42 CLKOUT_PCIE_N0 XTAL24_IN CC22
    Alpine Ridge---> <39> CLK0_PCIE_TBT AR10 CLKOUT_PCIE_P0 XTAL24_OUT 1 2
    <39> CLKREQ_PCIE#0 GPP_B5/SRCCLKREQ0#
    @ RC63 1 2 10K_0402_5%
    +3VS
    B42 15P_0402_50V8J
    D <29> CLK1_PCIE_WLAN# A42 CLKOUT_PCIE_N1 F43 CLK_ITPXDP_N_R 1 2 0_0402_1% D
    WLAN---> <29> CLK1_PCIE_WLAN CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N
    RC297 @
    CLK_ITPXDP_N <15> R04_0609: Remove RC295 for layout limitation
    AT7 E43 CLK_ITPXDP_P_R RC298 1 @ 2 0_0402_1%
    <29> CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P CLK_ITPXDP_P <15>
    RC47 1 2 10K_0402_5%
    +3VS
    D41 BA17 SUSCLK
    C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <29,30>
    CC23
    RC49 1 2 10K_0402_5% AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN PCH_RTCX1 1 2
    +3VS GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT PCH_RTCX2
    D40 XTAL24_OUT 6.8P_0402_50V8J
    <30> CLK_PCIE_SSD# C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF 1 2
    SDD---> <30> CLK_PCIE_SSD CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK

    1
    AT10 RC52 2.7K_0402_1%
    <30> CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3#
    RC59 1 2 10K_0402_5% AM18 PCH_RTCX1 RC54 YC2
    +3VS RTCX1
    B40 AM20 PCH_RTCX2 10M_0402_5% 9PF 20PPM 9H03280012
    A40 CLKOUT_PCIE_N4 RTCX2 ESR MAX=50k ohm

    2
    RC50 1 2 10K_0402_5% AU8 CLKOUT_PCIE_P4 AN18 SRTCRST# RC56 1 2 20K_0402_5%
    +3VS +RTCVCC

    1
    GPP_B9/SRCCLKREQ4# SRTCRST# AM16 CC26
    E40 RTCRST# CC24 1 2 1U_0402_6.3V6K 1 @ 2 PCH_RTCX2_R 1 2
    <24> CLK_PCIE_MMI# E38 CLKOUT_PCIE_N5 RC296 0_0402_1%
    Card Reader ---> <24> CLK_PCIE_MMI AU7 CLKOUT_PCIE_P5 6.8P_0402_50V8J
    <24> CLKREQ_PCIE#5 GPP_B10/SRCCLKREQ5#
    RC190 1 2 10K_0402_5% PCH_RTCRST# RC57 1 2 20K_0402_5%
    +3VS
    R04_0609: Fine tune cap by vendor suggestion
    CC25 1 2 1U_0402_6.3V6K

    SKL-U_BGA1356 10 OF 20

    1 2
    1 2

    +3V_PCH_DSW SHORT PADS~D


    @ CMOS1
    1 2
    1 2 PCH_PCIE_WAKE# @ RC226 0_0402_5%
    CMOS1 must take care short & touch risk on layout placement
    C RC67 1K_0402_5% C

    1 2 LAN_WAKE# +3VS
    RC95 10K_0402_5%

    5
    +3VS 1 PCH_PLTRST#

    P
    4 B
    <24,28,29,30,37,39> PCH_PLTRST#_EC O 2
    A

    G
    1

    1 2 ME_RESET# UC7

    2
    @ RC225 8.2K_0402_5% RC65 TC7SH08FU_SSOP5~D

    3
    100K_0402_5% RC85 @ +RTCVCC
    10K_0402_5%
    2

    INTRUDER# 1 2

    1
    RC69 330K_0402_5%

    +1.0V_VCCST +3V_PCH_DSW +3V_PCH

    1 2 H_VCCST_PWRGD_P
    RC71 1K_0402_5% PCH_BATLOW# 1 2 VRALERT# 1 2
    RC72 8.2K_0402_5% RC73 10K_0402_5%
    +3V_PCH AC_PRESENT 1 2
    RC243 10K_0402_5%
    1 2 ME_SUS_PWR_ACK @ UCPU1K SKL-U
    @ RC74 10K_0402_5%
    SYSTEM POWER MANAGEMENT
    AT11 SIO_SLP_S0# SLP_S0# for support connect stand by mode
    GPP_B12/SLP_S0# AP15 SIO_SLP_S3# SIO_SLP_S0# <28,34,56>
    PCH_PLTRST# AN10 GPD4/SLP_S3# BA16 SIO_SLP_S4# SIO_SLP_S3# <36,37,39>
    <15,37> PCH_RSMRST# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S4# <36,37>
    SYS_RESET# SIO_SLP_S5#
    B 1 2 10K_0402_5% AY17 SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <37> B
    RC75 PCH_RSMRST# 8/21 CRB1.0 change to 0603 1/10W
    RSMRST# AN15
    H_CPUPWRGD_R @ RC77 1
    @RC77 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_SUS# <33,36,37,50,51,56>
    T9 @ PAD~D PROCPWRGD SLP_LAN# PAD~D @ T116
    H_VCCST_PWRGD_P RC78 1 2 60.4_0402_1% VCCST_PWRGD B65 BB17
    <15,36> H_VCCST_PWRGD_P VCCST_PWRGD GPD9/SLP_WLAN# AN16 SIO_SLP_WLAN# <37>
    GPD6/SLP_A# SIO_SLP_A# <37>
    APS CONN
    B6
    <15,37> RESET_OUT# BA20 SYS_PWROK BA15
    <53> PCH_PWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT SIO_PWRBTN# <15,37>
    H_CPUPWRGD H_VCCST_PWRGD_P <37> PCH_DPWROK_R DSW_PWROK GPD1/ACPRESENT AU13 PCH_BATLOW# AC_PRESENT <37>
    JAPS1
    ME_SUS_PWR_ACKAR13 GPD0/BATLOW# 1
    <37> ME_SUS_PWR_ACK GPP_A13/SUSWARN#/SUSPWRDNACK +3V_PCH 1
    100P_0402_50V8J~D

    100P_0402_50V8J~D

    AP11 SIO_SLP_S3# 2
    <37> SUSACK# GPP_A15/SUSACK# AU11 3 2
    PME#
    PCH_PCIE_WAKE# BB15 GPP_A11/PME# AP16 INTRUDER# PAD~D @ T115 +3VALW
    SIO_SLP_S5# 4 3
    1 1 <37> PCH_PCIE_WAKE# WAKE# INTRUDER# 4
    CA35

    CA32

    LAN_WAKE# AM15 SIO_SLP_S4# 5


    <37> LAN_WAKE# AW17 GPD2/LAN_WAKE# AM10 SIO_SLP_A# 6 5
    AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# MPHYP_PWR_EN <34> 7 6
    2 2 <33> 3.3V_CAM_EN# GPD7/RSVD GPP_B2/VRALERT# +3VALW 7
    8
    PCH_RTCRST# 9 8
    SKL-U_BGA1356 11 OF 20 10 9
    11 10
    <24,37> PBTN_SW# 12 11
    ESD Request:place near CPU side RC290 1 @ 2 0_0402_1% +3VS SYS_RESET# 13 12
    14 13
    14
    10K_0402_5%
    SIO_SLP_S0# 15
    15
    1

    16
    +3VS 16
    @ RC291
    @RC291

    17
    RC215 18 17
    19 18
    POP NO Support Deep sleep GND
    5

    20
    2

    DE-POP Support Deep sleep XDP_DBRESET# 1 GND


    P

    <15> XDP_DBRESET# B 4 SYS_RESET#_R 1 2 SYS_RESET# CONN@


    PCH_DPWROK_R1 2 PCH_RSMRST# 2 1 ME_RESET# 2 O RC224 1K_0402_5% ACES_50506-01841-P01
    A
    G

    A @RC215
    @ RC215 0_0402_5% @ RC227 8.2K_0402_5% @ UC12 A
    74AHC1G09GW_TSSOP5
    3
    1
    0.01U_0402_16V7K

    100K_0402_5%~D

    1
    CC266

    RC220

    2 if pop UC12, RC291 also need pop(74AHC1G09GW is OD output) DELL CONFIDENTIAL/PROPRIETARY


    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P12-MCP(6/14)CLK,PM,RTC
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 12 of 59
    5 4 3 2 1
    5 4 3 2 1

    +1.0V_VCCST

    1 2 H_CATERR#
    @ RC79 49.9_0402_1% +1.0V_VCCSTG
    1 2 H_THERMTRIP#
    RC80 1K_0402_5%
    +1.0V_VCCSTG @ UCPU1D SKL-U TDI_XDP 2 1 RC81
    51_0402_5%
    1 2 H_PROCHOT# H_CATERR# D63 TDO_XDP 2 1 RC82
    RC83 1K_0402_5% A54 CATERR# 51_0402_5%
    <37> PECI_EC H_PROCHOT# 1 2 H_PROCHOT#_R C65 PECI TMS_XDP 2 1
    JTAG RC130
    <37,46,47,53> H_PROCHOT# C63 PROCHOT#
    RC84 499_0402_1% H_THERMTRIP# 51_0402_5%
    <37> H_THERMTRIP# A65 THERMTRIP# B61 TCLK_XDP PCH_JTAG_TCLK 2 1
    D +3VS SKTOCC# PROC_TCK D60 TCLK_XDP <15> D
    CPU MISC TDI_XDP @ RC86 51_0402_5%
    C55 PROC_TDI A61 TDO_XDP TDI_XDP <15>
    1 2 TOUCHPAD_INTR# <15> XDP_OBS0_R D55 BPM#[0] PROC_TDO C60 TMS_XDP TDO_XDP <15>
    <15> XDP_OBS1_R XDP_OBS2_R B54 BPM#[1] PROC_TMS B59 TRST#_XDP TMS_XDP <15>
    RC272 10K_0402_5% T10 @ PAD~D
    1 2 TOUCH_SCREEN_PD# BPM#[2] PROC_TRST# TRST#_XDP <15>
    XDP_OBS3_R C56
    T11 @ PAD~D BPM#[3]
    RC277 10K_0402_5% B56 PCH_JTAG_TCLK
    1 2 EC_SLP_S0IX# SIO_EXT_SMI# A6 PCH_JTAG_TCK D59 TDI_XDP PCH_JTAG_TCLK <15>
    <37> SIO_EXT_SMI# TOUCH_SCREEN_PD# A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 TDO_XDP
    @ RC246 10K_0402_5%
    <25> TOUCH_SCREEN_PD# TOUCHPAD_INTR# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 TMS_XDP
    AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 TRST#_XDP
    +3V_PCH <37> EC_SLP_S0IX# GPP_B4/CPU_GP3 PCH_TRST# A59 1 2
    TCLK_XDP +1.0V_VCCSTG
    CPU_POPIRCOMP AT16 JTAGX @RC87
    @ RC87 1K_0402_5%
    1 2 SIO_EXT_SMI# PCH_POPIRCOMP AU16 PROC_POPIRCOMP
    RC236 10K_0402_5% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
    EOPIO_RCOMP H65 OPCE_RCOMP
    OPC_RCOMP

    1
    49.9_0402_1%

    49.9_0402_1%

    49.9_0402_1%

    49.9_0402_1%
    RC88

    RC89

    RC90

    RC91
    SKL-U_BGA1356 4 OF 20
    Service Mode Switch:
    DZ3 Add a switch to ME_FWP signal to unlock the ME region and

    2
    RB751S40T1G_SOD523-2
    1 2 TOUCHPAD_INTR# allow the entire region of the SPI flash to be updated using FPT.
    <36,37> PTP_INT#_EC +3VS_AUDIO

    1
    RC9 @
    1K_0402_5%
    SW1 @

    2
    C 1 C
    HDA_SDOUT 1K_0402_5%~D 2 1 RH24 ME_EN 2
    3
    0_0402_5%~D 2 1 R1191
    4
    G
    5
    <37> ME_FWP_EC G
    SSAL120100_3P

    ME_FWP PCH has internal 20K PD.


    FLASH DESCRIPTOR SECURITY OVERRIDE
    Disable ME Protect (ME can be updated) ----> Pin1 & Pin2 short
    @ UCPU1G SKL-U Enable ME Protect (ME cannot be updated)-->Pin3 & Pin2 short(Default position)
    AUDIO

    RC92 1 2 33_0402_5% HDA_SYNC BA22


    <26> HDA_SYNC_R 1 2 HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
    RC93 33_0402_5%
    <26> HDA_BIT_CLK_R 1 2 BB22 HDA_BLK/I2S0_SCLK
    RC94 33_0402_5% HDA_SDOUT SDIO/SDXC
    <26> HDA_SDOUT_R BA21 HDA_SDO/I2S0_TXD
    <26> HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11 CAM_CBL_DET#
    AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 CAM_CBL_DET# <25>
    PAD~D @ T192
    J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
    AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12 TBT_CIO_PLUG_EVENT# <39>
    AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11 SSD_PWR_EN <33> +3VS
    HDA_BIT_CLK_R
    I2S1_TXD GPP_G4/SD_DATA3 W10
    AK7 GPP_G5/SD_CD# W8 CAM_CBL_DET# 1 2
    1 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK
    AK6 W7 RC280 100K_0402_5%~D
    CC27 AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
    B AK10 GPP_F2/I2S2_TXD BA9 B
    22P_0402_50V8J GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 SD_PWR_EN <33>
    2 BB9
    GPP_A16/SD_1P8_SEL
    RC248 2 @ 1 0_0402_1% PCH_RTD3_CIO_PWR_ENH5 AB7 SD_RCOMPRC96 1 2 200_0402_1%
    <39> RTD3_CIO_PWR_EN 2 1 0_0402_1% GPP_D19/DMIC_CLK0 SD_RCOMP
    Close to RC93 RC247 @ PCH_TBT_FORCE_PWR D7
    <39> TBT_FORCE_PWR GPP_D20/DMIC_DATA0
    D8 AF13
    C8 GPP_D17/DMIC_CLK1 GPP_F23
    GPP_D18/DMIC_DATA1
    SPKR AW5
    <26> SPKR GPP_B14/SPKR

    SKL-U_BGA1356 7 OF 20

    +3V_PCH +3V_PCH

    A 1 2 SPKR 1 2 HDA_SDOUT A
    @ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5%

    TOP SWAP STRAP Flash Descriptor Security override DELL CONFIDENTIAL/PROPRIETARY


    HIGH ENABLE HIGH DISABLE Security Classification Compal Secret Data Compal Electronics, Inc.
    LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P13-MCP(7/14)MISC,JTAG,HDA,SDIO
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 13 of 59
    5 4 3 2 1
    5 4 3 2 1

    <15> CFG[0..15]
    CFG0
    CFG1
    CFG2
    CFG3
    CFG4
    CFG5
    CFG6
    CFG7
    CFG8
    CFG9
    CFG10
    CFG11
    CFG12
    CFG13
    D CFG14 D
    CFG15

    @ UCPU1S SKL-U
    @ UCPU1T SKL-U
    RESERVED SIGNALS-1
    1 2 CFG0 SPARE
    @ RC113 10K_0402_1% CFG0 E68 BB68
    1 2 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 PAD~D @ T12 AW69 F6
    CFG2 D65 CFG[1] RSVD_TP_BB69 PAD~D @ T13 AW68 RSVD_AW69 RSVD_F6 E3
    @RC112
    @ RC112 10K_0402_1%
    1 2 CFG3 D67 CFG[2] AK13 AU56 RSVD_AW68 RSVD_E3 C11
    CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 PAD~D @ T14 AW48 RSVD_AU56 RSVD_C11 B11
    @RC110
    @ RC110 10K_0402_1%
    C68 CFG[4] RSVD_TP_AK12 PAD~D @ T15 C7 RSVD_AW48 RSVD_B11 A11
    CFG5
    CFG6 D68 CFG[5] BB2 U12 RSVD_C7 RSVD_A11 D12
    Stall reset sequence CFG7 C67 CFG[6] RSVD_BB2 BA3 U11 RSVD_U12 RSVD_D12 C12
    CFG8 F71 CFG[7] RSVD_BA3 H11 RSVD_U11 RSVD_C12 F52
    HIGH(DEFAULT) No stall(Normal Operation) CFG9 G69 CFG[8] RSVD_H11 RSVD_F52
    LOW stall CFG10 F70 CFG[9] AU5
    CFG11 G68 CFG[10] TP5 AT5 PAD~D @ T128
    CFG12 H70 CFG[11] TP6 PAD~D @ T129
    SKL-U_BGA1356 20 OF 20
    CFG13 G71 CFG[12]
    CFG14 H69 CFG[13] D5
    CFG15 G70 CFG[14] RSVD_D5 D4
    CFG[15] RSVD_D4 B2
    E63 RSVD_B2 C2
    <15> CFG16 CFG[16] RSVD_C2
    <15> CFG17 F63
    CFG[17] B3
    E66 RSVD_B3 A3
    <15> CFG18 CFG[18] RSVD_A3
    <15> CFG19 F66
    C 1 2 CFG4 CFG[19] AW1 C
    RC109 10K_0402_1% 2 1 CFG_RCOMP E60 RSVD_AW1
    RC114 49.9_0402_1% CFG_RCOMP E1
    2 1 ITP_PMODE E8 RSVD_E1 E2
    +1.0VA_XDP ITP_PMODE RSVD_E2
    RC115 1.5K_0402_5%
    AY2 BA4
    AY1 RSVD_AY2 RSVD_BA4 BB4
    <15> ITP_PMODE RSVD_AY1 RSVD_BB4
    eDP enable D1 A4
    D3 RSVD_D1 RSVD_A4 C4
    HIGH(DEFAULT) Disabled RSVD_D3 RSVD_C4
    LOW Enabled K46
    RSVD_K46 TP4
    BB5
    PAD~D @ T130
    K45
    RSVD_K45 A69
    AL25 RSVD_A69 B69
    AL27 RSVD_AL25 RSVD_B69
    RSVD_AL27 AY3
    C71 RSVD_AY3
    B70 RSVD_C71 D71
    RSVD_B70 RSVD_D71 C70
    F60 RSVD_C70
    RSVD_F60 C54
    A52 RSVD_C54 D54
    RSVD_A52 RSVD_D54
    BA70 AY4
    T16 @ PAD~D RSVD_TP_BA70 TP1 PAD~D @ T126
    BA68 BB3
    T17 @ PAD~D RSVD_TP_BA68 TP2 PAD~D @ T127
    J71 AY71
    J68 RSVD_J71 VSS_AY71 AR56
    RSVD_J68 ZVM# LPM_ZVM_N <57> ZVM# for SKYLAKE-U 2+3e
    F65 AW71
    G65 VSS_F65 RSVD_TP_AW71 AW70 PAD~D @ T113
    B VSS_G65 RSVD_TP_AW70 PAD~D @ T114 B
    F61 AP56
    E61 RSVD_F61 MSM# C64 1 2
    MSM_N <57> MSM# for SKYLAKE-U 2+3e
    RSVD_E61 PROC_SELECT# +1.0V_VCCST
    RC120 100K_0402_5%

    SKL-U_BGA1356 19 OF 20

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P14-MCP(8/14)CFG,RSVD
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 14 of 59
    5 4 3 2 1
    5 4 3 2 1

    +1.0VA RC216 +1.0VA_XDP


    0_0603_5%
    1 @ 2 +1.0VA_XDP CXDP@
    CPU XDP XDP_PRSNT_PIN1 1
    RC121
    2 CFG3
    1K_0402_5% +1.0VA_XDP
    1 2
    @ RC122 0_0402_5%
    +1.0VA_XDP JXDP1
    D 1 2 D
    Place near CPU_XDP_PREQ# 3 GND0 GND1 4 CFG17
    <11> CPU_XDP_PREQ# CFG17 <14>
    JXDP1 5 OBSFN_A0 OBSFN_C0 6 CFG16 CFG16 <14>
    <11> CPU_XDP_PRDY# 7 OBSFN_A1 OBSFN_C1

    0.1U_0402_10V7K

    0.1U_0402_10V7K
    1 1 8
    9 GND2 GND3

    @ CC28

    @ CC29
    <14> CFG0 CFG0 10 CFG8 CFG8 <14>
    <14> CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9 CFG9 <14>
    13 OBSDATA_A1 OBSDATA_C1 14
    2 2 15 GND4 GND5 16 CFG10
    <14> CFG2 CFG10 <14>
    <14> CFG3 CFG3 17 OBSDATA_A2 OBSDATA_C2 18 CFG11 CFG11 <14>
    19 OBSDATA_A3 OBSDATA_C3 20
    CXDP@ RC239 1 2 0_0402_5% XDP_OBS0 21 GND6 GND7 22 CFG19 CFG19 <14>
    <13> XDP_OBS0_R 23 OBSFN_B0 OBSFN_D0
    CXDP@ RC240 1 2 0_0402_5% XDP_OBS1 24 CFG18 CFG18 <14>
    <13> XDP_OBS1_R 25 OBSFN_B1 OBSFN_D1 26
    27 GND8 GND9 28 CFG12
    <14> CFG4 CFG12 <14>
    <14> CFG5 29 OBSDATA_B0 OBSDATA_D0 30 CFG13 CFG13 <14>
    +1.0V_VCCSTG
    RC5 need to close to JCPU1 31 OBSDATA_B1 OBSDATA_D1 32
    33 GND10 GND11 34 CFG14 TMS_XDP 2 1 RC131
    <14> CFG6 CFG14 <14>
    @ RC1231 2 1K_0402_5% <14> CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15 CFG15 <14> 51_0402_5%
    <12,36> H_VCCST_PWRGD_P 37 OBSDATA_B3 OBSDATA_D3 38 TDI_XDP 2 1 RC134
    <12,37> PCH_RSMRST# CXDP@ RC1241 2 H_VCCST_PWRGD_XDP 39 GND12 GND13 40 51_0402_5%
    SIO_PWRBTN# 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 CLK_ITPXDP_P <12> TDO_XDP 2 1
    1K_0402_5% RC135
    FIVR_EN <12,37>
    1 SIO_PWRBTN#
    2 43 HOOK1 ITPCLK#/HOOK5 44 CLK_ITPXDP_N <12>
    @ RC217 0_0402_5% 51_0402_5%
    CFG0 @ RC1261 2 1K_0402_5% FIVR_EN_R 45 VCC_OBS_AB VCC_OBS_CD 46
    47 HOOK2 RESET#/HOOK6 ITP_PMODE <14>
    PCH_SPI_DO_XDP CXDP@ RC1281 2 0_0402_5% RESET_OUT#_R 48 XDP_DBRESET# XDP_DBRESET# <12>
    <9> PCH_SPI_DO_XDP 49 HOOK3 DBR#/HOOK7
    @ RC1291 2 0_0402_5% 50 TRST#_XDP 2 1 @ RC136
    <12,37> RESET_OUT# 51 GND14 GND15 52 TDO_XDP <13> 51_0402_5%
    <9> DDR_XDP_SMBDAT 53 SDA TD0 54 TCLK_XDP 2 1
    TRST#_XDP <13> RC139
    <9> DDR_XDP_SMBCLK 55 SCL TRST# 56 TDI_XDP <13> 51_0402_5%
    <13> PCH_JTAG_TCLK 57 TCK1 TDI 58
    <13> TCLK_XDP TCLK_XDP TMS_XDP <13>
    59 TCK0 TMS 60
    GND16 GND17 PCH_SPI_DO2_XDP <9>
    SAMTE_BSH-030-01-L-D-A CONN@
    C C

    +1.0VS_VCCIO

    1 2 FIVR_EN_R
    @ RC132 150_0402_5%
    +3VS +3V_PCH_DSW
    +3V_PCH
    +1.0V_VCCST

    1
    1K_0402_5%

    1.5K_0402_5%
    @ RC241
    1

    RC137
    1.5K_0402_5%
    RC133
    1 2 FIVR_EN
    @ RC218 150_0402_5%

    1 2 FIVR_EN

    2
    @ RC219 10K_0402_5%

    2
    XDP_DBRESET# SIO_PWRBTN#

    0.1U_0402_25V6
    CXDP@ CC32

    0.1U_0402_25V6
    PCH_SPI_DO_XDP

    @CC269
    @
    1

    CC269
    +1.0VA_XDP
    Place near JXDP1.48 Place near JXDP1.41

    2
    @ RC138 1 2 CPU_XDP_PREQ#
    51_0402_5%

    2 1 RESET_OUT#_R
    @ CC33 0.1U_0402_25V6

    B Place near JXDP1.47 B

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P15-MCP(9/14)XDP
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 15 of 59
    5 4 3 2 1
    5 4 3 2 1

    PSC(Primary side cap) : Place as close to the package as possible +VCC_CORE +VCC_CORE
    BSC(Backside cap) : Place on secondary side, underneath the package
    @ UCPU1L SKL-U
    CPU POWER 1 OF 4
    Component placement order: A30 G32
    Package edge > 0402 caps > 0805 caps > Bulk caps >Power source A34 VCC_A30 VCC_G32 G33
    A39 VCC_A34 VCC_G33 G35
    A44 VCC_A39 VCC_G35 G37
    AK33 VCC_A44 VCC_G37 G38
    +VCC_CORE: 0.55~1.5V, 29A +1.8VA +V1.8S_EDRAM
    AK35 VCC_AK33
    VCC_AK35
    VCC_G38
    VCC_G40
    G40
    AK37 G42
    D
    +VCC_EDRAM: 1V, 2.5A R1334
    0_0603_5%
    AK38
    AK40
    VCC_AK37
    VCC_AK38
    VCC_G42
    VCC_J30
    J30
    J33
    D

    VCC_AK40 1.5V@29A VCC_J33


    +V1.8S_EDRAM: 1.8V, 50mA 1 @ 2 AL33
    AL37 VCC_AL33 VCC_J37
    J37
    J40
    AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE
    +VCC_EOPIO: 0.8~1V, 2A AM32 VCC_AL40
    VCC_AM32
    VCC_K33
    VCC_K35
    K35
    AM33 K37
    VCC_AM33 VCC_K37

    100_0402_1%
    AM35 K38
    AM37 VCC_AM35 VCC_K38 K40
    VCC_AM37 VCC_K40
    Close CPU

    RC140
    AM38 K42
    G30 VCC_AM38 VCC_K42 K43
    VCC_G30 VCC_K43

    2
    +VCC_CORE_G0 K32 E32 VCCSENSE
    T122@ PAD~D RSVD_K32 VCC_SENSE VCCSENSE <53>
    E33 VSSSENSE
    +VCC_CORE_G1 AK32 VSS_SENSE VSSSENSE <53>
    T123@ PAD~D RSVD_AK32

    100_0402_1%
    B63 H_CPU_SVIDALRT#
    AB62 VIDALERT# A63 VIDSCLK_R
    +VCC_EDRAM VCCOPC_AB62 VIDSCK

    RC141
    P62 1V@2.5A D64 VIDSOUT_R
    V62 VCCOPC_P62 VIDSOUT
    VCCOPC_V62 G20

    2
    H63 VCCSTG_G20
    +V1.8S_EDRAM VCC_OPC_1P8_H63 1V@0.05A
    RC2321 @ 2 0_0603_5% G61
    VCC_OPC_1P8_G61
    AC63
    <57> VCC_EDRAM_SENSE AE63 VCCOPC_SENSE
    <57> VSS_EDRAM_SENSE VSSOPC_SENSE +1.0V_VCCSTG_R 1 2 0_0603_5%
    RC143 @ +1.0V_VCCSTG
    AE62
    +VCC_EOPIO VCCEOPIO
    AG62 1V@2A
    VCCEOPIO
    AL63
    <57> VCC_EOPIO_SENSE AJ62 VCCEOPIO_SENSE
    C <57> VSS_EOPIO_SENSE VSSEOPIO_SENSE C

    SKL-U_BGA1356 12 OF 20

    VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e


    (w/ on package cache)

    +VCC_EDRAM Decoupling Requirment +VCC_EOPIO Decoupling Requirment


    Back Side (underneath the package): Back Side (underneath the package): +1.0V_VCCST
    10U_0402*1 pcs + 1U_0201*6 pcs 10U_0402*2 pcs SVID ALERT
    +VCC_EDRAM +VCC_EOPIO

    1
    56_0402_1%
    RC152
    BSC BSC CAD Note: Place the PU resistors close to CPU
    RC204 close to CPU 300 - 1500mils
    10U_0402_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    2
    1 1 1 1 1 1 1 1 1
    CC180

    CC183

    CC188

    CC189

    CC190

    CC191

    CC192

    CC184

    CC187

    2 1 H_CPU_SVIDALRT#
    <53> VIDALERT_N
    220_0402_5% RC153
    2 2 2 2 2 2 2 2 2
    B B
    +1.0V_VCCST
    SVID DATA

    100_0402_1%
    1
    CAD Note: Place the PU resistors close to CPU

    RC157
    RC208close to CPU 300 - 1500mils

    2
    2 @ 1 VIDSOUT_R
    <53> VIDSOUT
    0_0402_1% RC154

    +1.0V_VCCST
    SVID CLK

    100_0402_1%
    1

    @ RC158
    CAD Note: Place the PU resistors close to CPU
    RC208close to CPU 300 - 1500mils

    2
    2 @ 1 VIDSCLK_R
    <53> VIDSCLK
    0_0402_1% RC155

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P16-MCP(10/14)PWR-VCC CORE
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 16 of 59
    5 4 3 2 1
    5 4 3 2 1

    +VCCGT: 0.55~1.5V, 54A


    +VCCGTX : 0.55~1.5V, 7A
    +VCC_GT +VCC_GT

    D @ UCPU1M SKL-U D

    CPU POWER 2 OF 4
    N70
    A48 VCCGT N71
    A53 VCCGT VCCGT R63
    A58 VCCGT VCCGT R64
    A62 VCCGT VCCGT R65
    A66 VCCGT VCCGT R66
    AA63 VCCGT VCCGT R67
    AA64 VCCGT VCCGT R68
    AA66 VCCGT VCCGT R69
    AA67 VCCGT
    VCCGT
    1.5V@54A VCCGT
    VCCGT
    R70
    AA69 R71
    AA70 VCCGT VCCGT T62
    AA71 VCCGT VCCGT U65
    AC64 VCCGT VCCGT U68
    AC65 VCCGT VCCGT U71
    AC66 VCCGT VCCGT W63
    AC67 VCCGT VCCGT W64
    AC68 VCCGT VCCGT W65
    AC69 VCCGT VCCGT W66
    AC70 VCCGT VCCGT W67
    AC71 VCCGT VCCGT W68
    J43 VCCGT VCCGT W69
    J45 VCCGT VCCGT W70
    J46 VCCGT VCCGT W71
    J48 VCCGT
    VCCGT
    1.5V@7A VCCGT
    VCCGT
    Y62
    J50 +VCC_GT
    J52 VCCGT
    J53 VCCGT AK42
    J55 VCCGT VCCGTX_AK42 AK43
    C J56 VCCGT VCCGTX_AK43 AK45 C
    J58 VCCGT VCCGTX_AK45 AK46
    J60 VCCGT VCCGTX_AK46 AK48
    K48 VCCGT VCCGTX_AK48 AK50
    K50 VCCGT VCCGTX_AK50 AK52
    K52 VCCGT VCCGTX_AK52 AK53
    K53 VCCGT VCCGTX_AK53 AK55
    K55 VCCGT VCCGTX_AK55 AK56
    K56 VCCGT VCCGTX_AK56 AK58
    K58 VCCGT VCCGTX_AK58 AK60
    K60 VCCGT VCCGTX_AK60 AK70
    L62 VCCGT VCCGTX_AK70 AL43
    L63 VCCGT VCCGTX_AL43 AL46
    L64 VCCGT VCCGTX_AL46 AL50
    L65 VCCGT VCCGTX_AL50 AL53
    VCCGTX for SKYLAKE-U 2+3e
    L66 VCCGT VCCGTX_AL53 AL56 Merged the GT and GTx rail
    L67 VCCGT VCCGTX_AL56 AL60
    L68 VCCGT VCCGTX_AL60 AM48
    +VCC_GT L69 VCCGT VCCGTX_AM48 AM50
    L70 VCCGT VCCGTX_AM50 AM52
    L71 VCCGT VCCGTX_AM52 AM53
    M62 VCCGT VCCGTX_AM53 AM56
    VCCGT VCCGTX_AM56
    1

    100_0402_1%
    N63 AM58
    N64 VCCGT VCCGTX_AM58 AU58
    VCCGT VCCGTX_AU58
    RC161

    Close CPU N66 AU63


    N67 VCCGT VCCGTX_AU63 BB57
    N69 VCCGT VCCGTX_BB57 BB66
    2

    VCCGT VCCGTX_BB66
    VCC_GT_SENSE J70 AK62 T195 PAD~D @
    <53> VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61 T196 PAD~D @
    <53> VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
    1

    100_0402_1%

    B SKL-U_BGA1356 13 OF 20 B
    RC163
    2

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P17-MCP(11/14)PWR-VCCGT
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 17 of 59
    5 4 3 2 1
    5 4 3 2 1

    +1.2V_DDR: 1.2V, 3.5A


    +1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA
    +1.0V_VCCSTG: 1V, 40mA
    +VCCPLL_OC: 1.2V, 260mA +1.2V_DDR +1.0VS_VCCIO
    +1.0VS_VCCIO: 0.85~0.95V, 3.1A @ UCPU1N SKL-U
    CPU POWER 3 OF 4
    +VCC_SA: 1.15V, 5.1A AU23 AK28
    VDDQ_AU23
    D AU28 0.95V@3.1A VCCIO AK30 D
    AU35 VDDQ_AU28 VCCIO AL30
    AU42 VDDQ_AU35 VCCIO AL42
    BB23 VDDQ_AU42 VCCIO AM28
    +1.2V_DDR +1.2V_MEM_CPUCLK BB32 VDDQ_BB23 VCCIO AM30
    1.2V@3.5A
    BB41 VDDQ_BB32 VCCIO AM42 +VCC_SA
    +1.2V_MEM_CPUCLK BB47 VDDQ_BB41 VCCIO
    1 @ 2 BB51 VDDQ_BB47 AK23
    RC171 0_0402_1% VDDQ_BB51 VCCSA AK25
    VCCSA G23
    AM40 VCCSA G25
    VDDQC VCCSA G27
    1V@0.12A A18 VCCSA G28 +1.0VS_VCCIO
    VCCST 1.15V@5.1A VCCSA J22
    1V@0.04A A22 VCCSA J23
    VCCSTG_A22 VCCSA J27
    VCCSA

    100_0402_1%
    1.2V@0.26A AL23 VCCPLL_OC VCCSA
    K23

    RC165
    K25
    +1.0V_VCCST 1V@0.12A K20 VCCSA K27
    VCCPLL_K20 VCCSA
    Close CPU
    K21 K28
    VCCPLL_K21 VCCSA K30
    PSC

    2
    VCCSA
    close to package AM23 VCCIO_SENSE
    VCCIO_SENSE AM22 VCCIO_SENSE <56>
    VSSIO_SENSE
    +1.0V_VCCSTG VSSIO_SENSE VSSIO_SENSE <56>

    1U_0402_6.3V6K
    1
    H21
    VSSSA_SENSE

    CC195
    H20
    BSC VCCSA_SENSE

    1
    100_0402_1%

    100_0402_1%
    2 underneath the package

    RC166

    RC167
    SKL-U_BGA1356 14 OF 20

    1U_0402_6.3V6K
    1 1 2
    +VCCPLL_OC +1.0V_VCCST +VCC_SA

    @ CC199
    RC168 100_0402_1%

    2
    C C

    2 PSC PSC
    close to package close to package

    1U_0201_6.3V6M

    1U_0402_6.3V6K
    1 1 VSA_SEN- <53>

    CC261
    VSA_SEN+ <53>

    CC202
    2 2

    +1.0VS_VCCIO Decoupling Requirment +1.2V_MEM_CPUCLK (VDDQC) Place on CPU


    +1.2_DDR Decoupling Requirment Back Side (underneath the package): Back Side (underneath the package):
    Back Side (underneath the package): 10U_0402*2 pcs + 1U_0201*4 pcs (@) 1U_0201*1 pcs (@)
    10U_0402*2 pcs + 1U_0201*4 pcs (@) Primary Side (close to package): Primary Side (close to package):
    Primary Side (close to package): 1U_0402*4 pcs 10U_0402 * 1 pcs
    10U_0402*4 pcs + 22U_0603*3 pcs
    +1.0VS_VCCIO +1.2V_DDR
    B +1.2V_DDR B

    PSC BSC
    PSC
    PSC

    10U_0402_6.3V6M

    1U_0201_6.3V6M
    1 1
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    CC194

    @ CC260
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    1 1 1 1
    1 1 1 1 1 1 1
    CC34

    CC31

    CC35

    CC177

    CC178

    CC179

    CC176

    CC252

    CC253

    CC250

    CC251
    2 2
    2 2 2 2
    2 2 2 2 2 2 2

    BSC BSC
    10U_0402_6.3V6M

    10U_0402_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1 1 1 1 1 1 1 1 1 1 1 1
    @ CC174

    @ CC175

    @ CC258

    @ CC259

    @ CC256

    @ CC257

    @ CC248

    @ CC249

    @ CC181

    @ CC182

    @ CC185

    @ CC186
    2 2 2 2 2 2 2 2 2 2 2 2

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P18-MCP(12/14)PWR-VCCIO,MEM
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 18 of 59
    5 4 3 2 1
    5 4 3 2 1

    +3V_PCH +3.3V_PGPP

    1 @ 2 close UC1.AG15 and <120mil


    close UC1.Y16 and <400mil close UC1.T16 and <400mil
    RC211 0_0603_5%
    1 1 1

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    @CC265
    CC265

    @CC267
    CC267

    @CC268
    CC268
    D PCH PWR 2 2 2
    D

    @
    +3VALW +1.8VA +1.0VA +1.0V_PRIM_CORE

    @
    1 1 1 1 8/26 vender suggestion
    47U_0805_6.3V6M

    47U_0805_6.3V6M

    47U_0805_6.3V6M

    47U_0805_6.3V6M
    +1.0V_MPHYAON +1.0V_PRIM_CORE +1.0VA
    CC271

    CC272

    CC273

    CC274
    2 2 2 2
    close UC1.AB19 and <400mil

    1 1 1 1

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    @ CC205

    @ CC206
    R04_0625: Add 4.7pF for RF request

    CC203

    CC204
    @ UCPU1O SKL-U
    2 2 2 2 +3.3V_PGPP +3V_PCH +1.8VA
    CPU POWER 4 OF 4

    1.0V@0.696A AB19
    AB20 VCCPRIM_1P0 AK15
    VCCPRIM_1P0 VCCPGPPA
    1.0V@0.085A
    P18 AG15

    4.7P_0402_50V8C
    VCCPRIM_1P0 VCCPGPPB Y16 1

    1U_0402_6.3V6K
    VCCPGPPC

    1
    +1.0VA close UC1.AF18 and <400mil 1.0V@2.57A AF18 Y15

    CC209
    AF19 VCCPRIM_CORE VCCPGPPD T16

    CC212
    V20 VCCPRIM_CORE VCCPGPPE AF16 1.0V@0.161A +1.8V_PGPP

    2
    +1.0V_MPHYAON V21 VCCPRIM_CORE VCCPGPPF AD15 2
    VCCPRIM_CORE VCCPGPPG +3.3V_PGPP

    close UC1.AL1 and <120mil AL1 V19 close UC1.V19 and <120mil
    1 @ 2 DCPDSW_1P0 VCCPRIM_3P3_V19
    RC299 0_0603_5% +1.0V_MPHYGT close UC1.K17 and <120mil 1.0V@0.022A K17 T1
    VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS +3V_PCH
    +1.0V_DTS L1
    VCCMPHYAON_1P0 AA1
    VCCATS_1P8
    1.8V@0.006A close UC1.AA1 and <400mil
    1 @ 2 close UC1.N15 and CC210 <400mil, CC211 <120mil 1.0V@2.1A N15
    RC301 0_0402_1% N16 VCCMPHYGT_1P0_N15 AK17 3.3V@0.001A close UC1.AK17 and <120mil
    N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
    1 1

    1U_0402_6.3V6K
    47U_0805_6.3V6M
    P15 VCCMPHYGT_1P0_N17 AK19 3.0V@0.001A close UC1.AK19 and <120mil

    @ CC210
    VCCMPHYGT_1P0_P15 VCCRTC_AK19 +RTCVCC
    P16 BB14

    CC211
    1 1

    1U_0402_6.3V6K
    0.1U_0402_10V7K
    VCCMPHYGT_1P0_P16 VCCRTC_BB14

    CC223
    1 1

    1U_0402_6.3V6K
    0.1U_0402_10V7K
    2 2 1.0V@0.088A K15 BB10 close UC1.BB10 and <120mil

    CC224
    C +1.0V_AMPHYPLL C
    L15 VCCAMPHYPLL_1P0 DCPRTC

    CC270

    CC213
    VCCAMPHYPLL_1P0 A14 2 2
    1.0V@0.135A +1.0V_CLK 1

    0.1U_0402_10V7K
    +3V_PCH +3.3V_SPI V15 VCCCLK1 2 2
    1.0V@0.026A

    CC214
    +1.0V_APLL VCCAPLL_1P0 K19
    1 @ 2 +3V_PCH AB17 VCCCLK2
    +1.0VA VCCPRIM_1P0_AB17 2
    RC213 0_0402_1% Y18 L21
    VCCPRIM_1P0_Y18 VCCCLK3
    3.3V@0.118A AD17 N20
    +3V_PCH_DSW VCCDSW_3P3_AD17 VCCCLK4
    AD18
    AJ17 VCCDSW_3P3_AD18 L19
    VCCDSW_3P3_AJ17 VCCCLK5
    1

    3.9p_0201_25V6K 4.7_0201_5%
    R9

    close UC1.AJ19 and <400mil 3.3V@0.068A AJ19 A10


    VCCHDA VCCCLK6
    +1.0V_SRAM 3.3V@0.011A AJ16 AN11
    +3.3V_SPI VCCSPI GPP_B0/CORE_VID0 CORE_VID0 <56>
    +1.0V_MPHYGT AN13 CORE_VID1 <56>
    2

    GPP_B1/CORE_VID1
    close UC1.AF20 and <400mil 1.0V@0.642A AF20 VCCSRAM_1P0
    AF21
    CC125

    1 1
    +1.0V_SRAM 1U_0402_6.3V6K T19 VCCSRAM_1P0
    @ CC217
    @CC217

    T20 VCCSRAM_1P0 Take care!!! Note1 on Page 19


    1 @ 2 VCCSRAM_1P0
    RC309 0_0603_5% 2 2 3.3V@0.075A AJ21
    +1.0V_APLLEBB +3V_PCH VCCPRIM_3P3_AJ21
    +1.0V_APLLEBB AK20
    +1.0VA VCCPRIM_1P0_AK20
    1 @ 2 close UC1.N18 and <120mil 1.0V@0.033A N18
    RC310 0_0402_1% VCCAPLLEBB
    R07_0810: Add RC to prevent RF noise
    1
    1U_0402_6.3V6K

    SKL-U_BGA1356 15 OF 20
    CC218

    B B

    +1.0V_MPHYGT +1.0V_AMPHYPLL +3VALW +3V_PCH_DSW


    +1.0VA +1.0V_CLK
    +1.0VA +1.0V_APLL 1 @ 2
    RC169 1 @ 2 0_0402_1% +1.8VA +1.8V_PGPP RC214 0_0603_5% 1 @ 2
    close UC1.K15 and <120mil RC172 1 2 0_0402_5%~D RC170 0_0603_5%

    22U_0603_6.3V6M
    @ CC279

    22U_0603_6.3V6M
    @ CC280
    1 1 @ 2 1 1 1 close UC1.A10 and <120mil
    1U_0402_6.3V6K

    1U_0402_6.3V6K
    RC304 0_0603_5% close UC1.V15 and <100mil
    @ CC264

    @ CC220
    1

    3.9p_0201_25V6K 4.7_0201_5%

    2 2 2 2
    R10
    2

    CC225

    1
    8/26 vender suggest depop

    R07_0810: Add RC to prevent RF noise

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P19-MCP(13/14)PCH PWR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 19 of 59
    5 4 3 2 1
    5 4 3 2 1

    Note1: VCCPRIM_CORE Implementation with PCH CORE_VID Recommendation

    @ UCPU1P SKL-U @ UCPU1Q SKL-U R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
    @ UCPU1R SKL-U
    GND 1 OF 3 GND 2 OF 3
    GND 3 OF 3
    A5 AL65 AT63 BA49 F8 L18
    A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
    A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
    AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
    AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
    D AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 D
    AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
    AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
    AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
    AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
    AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
    AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
    AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
    AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
    AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
    AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
    AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
    AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
    AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
    AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
    AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
    AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
    AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
    AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
    AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
    AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
    AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
    AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
    AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
    AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
    AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
    AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
    AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
    AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
    AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
    AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
    AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
    C AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17 C
    AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
    AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
    AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
    AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
    AH64 VSS VSS AR15 AY66 VSS VSS E11
    AH67 VSS VSS AR16 B10 VSS VSS E15
    AJ15 VSS VSS AR20 B14 VSS VSS E18
    AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356 18 OF 20
    AJ20 VSS VSS AR28 B22 VSS VSS E46
    AJ4 VSS VSS AR35 B30 VSS VSS E50
    AK11 VSS VSS AR42 B34 VSS VSS E53
    AK16 VSS VSS AR43 B39 VSS VSS E56
    AK18 VSS VSS AR45 B44 VSS VSS E6
    AK21 VSS VSS AR46 B48 VSS VSS E65
    AK22 VSS VSS AR48 B53 VSS VSS E71
    AK27 VSS VSS AR5 B58 VSS VSS F1
    AK63 VSS VSS AR50 B62 VSS VSS F13
    AK68 VSS VSS AR52 B66 VSS VSS F2
    AK69 VSS VSS AR53 B71 VSS VSS F22
    AK8 VSS VSS AR55 BA1 VSS VSS F23
    AL2 VSS VSS AR58 BA10 VSS VSS F27
    AL28 VSS VSS AR63 BA14 VSS VSS F28
    AL32 VSS VSS AR8 BA18 VSS VSS F32
    AL35 VSS VSS AT2 BA2 VSS VSS F33
    AL38 VSS VSS AT20 BA23 VSS VSS F35
    AL4 VSS VSS AT23 BA28 VSS VSS F37
    AL45 VSS VSS AT28 BA32 VSS VSS F38
    AL48 VSS VSS AT35 BA36 VSS VSS F4
    AL52 VSS VSS AT4 F68 VSS VSS F40
    AL55 VSS VSS AT42 BA45 VSS VSS F42
    AL58 VSS VSS AT56 VSS VSS BA41
    B AL64 VSS VSS AT58 VSS B
    VSS VSS

    SKL-U_BGA1356 16 OF 20 SKL-U_BGA1356 17 OF 20

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P20-MCP(14/14)VSS
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 20 of 59
    5 4 3 2 1
    5 4 3 2 1

    +1.8VU +1.8VU +1.8VU +1.8VU

    +1.8VU UD19 @ +1.8VU UD20 @

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    A3 P9 DDR_A_D21 A3 P9 DDR_A_D61
    A4 VDD1 DQ0 N9 DDR_A_D16 A4 VDD1 DQ0 N9 DDR_A_D56
    <8> DDR_A_DQS#[0..7] 1 1 VDD1 DQ1 1 1 VDD1 DQ1

    1
    CD92

    CD164

    CD146

    CD42

    CD143

    CD145
    A5 N10 DDR_A_D19 A5 N10 DDR_A_D59
    A6 VDD1 DQ2 N11 DDR_A_D18 A6 VDD1 DQ2 N11 DDR_A_D58
    <8> DDR_A_DQS[0..7] VDD1 DQ3 VDD1 DQ3
    A10 M8 DDR_A_D17 A10 M8 DDR_A_D60

    2
    2 2 U3 VDD1 DQ4 M9 DDR_A_D20 2 2 U3 VDD1 DQ4 M9 DDR_A_D57
    <8> DDR_A_D[0..63] VDD1 DQ5 VDD1 DQ5
    U4 M10 DDR_A_D23 U4 M10 DDR_A_D62
    U5 VDD1 DQ6 M11 DDR_A_D22 U5 VDD1 DQ6 M11 DDR_A_D63
    <23,8> DDR_A_CA1_[0..9] VDD1 DQ7 VDD1 DQ7
    U6 F11 DDR_A_D24 U6 F11 DDR_A_D55
    U10 VDD1 DQ8 F10 DDR_A_D25 U10 VDD1 DQ8 F10 DDR_A_D49
    <23,8> DDR_A_CA2_[0..9] +1.2V_DDR VDD1 DQ9 +1.2V_DDR VDD1 DQ9
    F9 DDR_A_D31 F9 DDR_A_D54
    DQ10 F8 DDR_A_D27 DQ10 F8 DDR_A_D50
    D
    A8 DQ11 E11 DDR_A_D29 A8 DQ11 E11 DDR_A_D53 D
    A9 VDD2 DQ12 E10 DDR_A_D28 A9 VDD2 DQ12 E10 DDR_A_D48
    D4 VDD2 DQ13 E9 DDR_A_D30 +1.2V_DDR +1.2V_DDR D4 VDD2 DQ13 E9 DDR_A_D52
    +1.2V_DDR +1.2V_DDR D5 VDD2 DQ14 D9 DDR_A_D26 D5 VDD2 DQ14 D9 DDR_A_D51
    D6 VDD2 DQ15 T8 DDR_A_D15 D6 VDD2 DQ15 T8 DDR_A_D45
    G5 VDD2 DQ16 T9 DDR_A_D14 G5 VDD2 DQ16 T9 DDR_A_D40
    VDD2 DQ17 VDD2 DQ17

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    H5 T10 DDR_A_D11 H5 T10 DDR_A_D43
    VDD2 DQ18 VDD2 DQ18
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    H6 T11 DDR_A_D12 1 1 1 H6 T11 DDR_A_D42
    VDD2 DQ19 VDD2 DQ19

    1
    CD6

    CD158

    CD159

    CD41
    1 1 1 H12 R8 DDR_A_D13 H12 R8 DDR_A_D44
    VDD2 DQ20 VDD2 DQ20
    1
    CD86

    CD3

    CD148

    CD149
    J5 R9 DDR_A_D10 J5 R9 DDR_A_D41
    J6 VDD2 DQ21 R10 DDR_A_D8 J6 VDD2 DQ21 R10 DDR_A_D46

    2
    K5 VDD2 DQ22 R11 DDR_A_D9 2 2 2 K5 VDD2 DQ22 R11 DDR_A_D47
    2

    2 2 2 K6 VDD2 DQ23 C11 DDR_A_D6 K6 VDD2 DQ23 C11 DDR_A_D33


    K12 VDD2 DQ24 C10 DDR_A_D7 K12 VDD2 DQ24 C10 DDR_A_D38
    L5 VDD2 DQ25 C9 DDR_A_D2 L5 VDD2 DQ25 C9 DDR_A_D39
    P4 VDD2 DQ26 C8 DDR_A_D0 P4 VDD2 DQ26 C8 DDR_A_D35
    P5 VDD2 DQ27 B11 DDR_A_D1 P5 VDD2 DQ27 B11 DDR_A_D34
    P6 VDD2 DQ28 B10 DDR_A_D3 P6 VDD2 DQ28 B10 DDR_A_D37
    U8 VDD2 DQ29 B9 DDR_A_D4 U8 VDD2 DQ29 B9 DDR_A_D32
    U9 VDD2 DQ30 B8 DDR_A_D5 U9 VDD2 DQ30 B8 DDR_A_D36
    +1.2V_DDR VDD2 DQ31 +1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR VDD2 DQ31

    +1.2V_DDR +1.2V_DDR +1.2V_DDR A11 R2 DDR_A_CA1_0 Closed to UD20 A11 R2 DDR_A_CA2_0


    C12 VDDQ CA0 P2 DDR_A_CA1_1 C12 VDDQ CA0 P2 DDR_A_CA2_1
    VDDQ CA1 VDDQ CA1

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    0.1U_0402_16V7K~D

    0.1U_0402_16V7K~D
    Closed to UD19 E8 N2 DDR_A_CA1_2 E8 N2 DDR_A_CA2_2
    E12 VDDQ CA2 N3 DDR_A_CA1_3 E12 VDDQ CA2 N3 DDR_A_CA2_3
    VDDQ CA3 1 1 1 1 1 1 VDDQ CA3

    1
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    0.1U_0402_16V7K~D

    0.1U_0402_16V7K~D

    CD34

    CD156

    CD157

    CD160

    CD161
    G12 M3 DDR_A_CA1_4 G12 M3 DDR_A_CA2_4
    VDDQ CA4 VDDQ CA4

    CD154

    CD155
    1 1 1 1 1 1 H8 F3 DDR_A_CA1_5 H8 F3 DDR_A_CA2_5
    VDDQ CA5 VDDQ CA5
    1
    CD8

    CD150

    CD33

    CD151

    CD37

    CD152

    H9 E3 DDR_A_CA1_6 H9 E3 DDR_A_CA2_6

    2
    VDDQ CA6 2 2 2 2 2 2 VDDQ CA6
    CD153

    H11 E2 DDR_A_CA1_7 H11 E2 DDR_A_CA2_7


    J9 VDDQ CA7 D2 DDR_A_CA1_8 J9 VDDQ CA7 D2 DDR_A_CA2_8
    2

    2 2 2 2 2 2 J10 VDDQ CA8 C2 DDR_A_CA1_9 J10 VDDQ CA8 C2 DDR_A_CA2_9


    K8 VDDQ CA9 K8 VDDQ CA9
    K11 VDDQ K11 VDDQ
    L12 VDDQ L10 DDR_A_DQS2 L12 VDDQ L10 DDR_A_DQS7
    N8 VDDQ DQS0 G10 DDR_A_DQS3 N8 VDDQ DQS0 G10 DDR_A_DQS6
    N12 VDDQ DQS1 P10 DDR_A_DQS1 N12 VDDQ DQS1 P10 DDR_A_DQS5
    R12 VDDQ DQS2 D10 DDR_A_DQS0 R12 VDDQ DQS2 D10 DDR_A_DQS4
    C C
    U11 VDDQ DQS3 U11 VDDQ DQS3
    +1.2V_DDR VDDQ +1.2V_DDR +1.2V_DDR +1.2V_DDR VDDQ
    L11 DDR_A_DQS#2 L11 DDR_A_DQS#7
    F2 DQS0# G11 DDR_A_DQS#3 F2 DQS0# G11 DDR_A_DQS#6
    +1.2V_DDR +1.2V_DDR G2 VDDCA DQS1# P11 DDR_A_DQS#1 G2 VDDCA DQS1# P11 DDR_A_DQS#5
    VDDCA DQS2# VDDCA DQS2#

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    H3 D11 DDR_A_DQS#0 H3 D11 DDR_A_DQS#4
    L2 VDDCA DQS3# L2 VDDCA DQS3#
    VDDCA 1 1 VDDCA

    1
    CD2

    CD7

    CD5
    M2 M2
    VDDCA VDDCA
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    L8 L8
    DM0 G8 DM0 G8
    1 1

    2
    DM1 DM1
    1

    2 2
    CD4

    CD1

    CD29

    A1 P8 A1 P8
    A2 NC DM2 D8 A2 NC DM2 D8
    A12 NC DM3 A12 NC DM3
    2

    2 2 A13 NC A13 NC
    B1 NC B3 DDR_A0_ZQ0 RD51 1 2 240_0402_1% B1 NC B3 DDR_A1_ZQ0 RD52 1 2 240_0402_1%
    B13 NC ZQ0 B4 DDR_A0_ZQ1 RD53 1 2 240_0402_1% B13 NC ZQ0 B4 DDR_A1_ZQ1 RD54 1 2 240_0402_1%
    C4 NC ZQ1 C4 NC ZQ1
    K9 NC K9 NC
    R3 NC K3 R3 NC K3
    NC CKE0 DDR_A_CKE0 <23,8> NC CKE0 DDR_A_CKE2 <23,8>
    T1 K4 DDR_A_CKE1 <23,8> T1 K4 DDR_A_CKE3 <23,8>
    T13 NC CKE1 T13 NC CKE1
    U1 NC U1 NC
    U2 NC L3 DDR_A_CS#0 U2 NC L3 DDR_A_CS#0
    NC CS0# DDR_A_CS#0 <23,8> NC CS0#
    U12 L4 DDR_A_CS#1 U12 L4 DDR_A_CS#1
    NC CS1# DDR_A_CS#1 <23,8> NC CS1#
    U13 U13
    NC NC
    J3 DDR_A_CLK0 <23,8> J3 DDR_A_CLK1 <23,8>
    P3 CK J2 P3 CK J2
    VSSCA CK# DDR_A_CLK#0 <23,8> All VREF traces should VSSCA CK# DDR_A_CLK#1 <23,8>
    M4 have 10 mil trace width M4
    J4 VSSCA J4 VSSCA
    G4 VSSCA J8 DDR_A_ODT0 G4 VSSCA J8 DDR_A_ODT0
    VSSCA ODT DDR_A_ODT0 <23,8> VSSCA ODT
    G3 G3
    F4 VSSCA F4 VSSCA
    D3 VSSCA J11 D3 VSSCA J11
    VSSCA Vref_DQ +VREFDQ_A VSSCA Vref_DQ +VREFDQ_A
    C3 H4 +VREFCA C3 H4 +VREFCA
    VSSCA Vref_CA VSSCA Vref_CA

    B B
    T12 B2 T12 B2
    T6 VSSQ VSS B5 T6 VSSQ VSS B5
    VSSQ VSS Closed to DRAM VSSQ VSS Closed to DRAM
    R6 C5 R6 C5
    P12 VSSQ VSS E4 +VREFDQ_A +VREFCA P12 VSSQ VSS E4 +VREFDQ_A +VREFCA
    N6 VSSQ VSS E5 N6 VSSQ VSS E5
    M12 VSSQ VSS F5 M12 VSSQ VSS F5
    VSSQ VSS VSSQ VSS
    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D
    M6 H2 M6 H2
    L9 VSSQ VSS J12 L9 VSSQ VSS J12
    K10 VSSQ VSS K2 K10 VSSQ VSS K2
    VSSQ VSS 1 1 R04_0603: Change 0.047uF CPN VSSQ VSS 1 1
    CD117

    CD180

    CD118

    CD181
    H10 L6 H10 L6
    G9 VSSQ VSS M5 G9 VSSQ VSS M5
    G6 VSSQ VSS N4 G6 VSSQ VSS N4
    F12 VSSQ VSS N5 2 2 F12 VSSQ VSS N5 2 2
    F6 VSSQ VSS R4 F6 VSSQ VSS R4
    E6 VSSQ VSS R5 E6 VSSQ VSS R5
    D12 VSSQ VSS T2 D12 VSSQ VSS T2
    C6 VSSQ VSS T3 C6 VSSQ VSS T3
    B12 VSSQ VSS T4 B12 VSSQ VSS T4
    B6 VSSQ VSS T5 B6 VSSQ VSS T5
    VSSQ VSS VSSQ VSS
    R04_0603: Change 0.047uF CPN
    H9CCNNN8JTMLAR-NTM_FBGA178~D H9CCNNN8JTMLAR-NTM_FBGA178~D

    Decoupling per DRAM device


    VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF +1.2V_DDR +1.8VU
    VDDCA 2x 0402 1uF 1x 0603 10uF
    VDD2 3x 0402 1uF 1x 0603 10uF
    VDD1 2x 0402 1uF 1x 0603 10uF
    10U_0603_6.3V6M~D

    10U_0603_6.3V6M~D

    intel uesd 0201 for 0.1uF


    1

    1
    CD182

    CD147
    2

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P21-DDRIII Channel A
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 21 of 59
    5 4 3 2 1
    5 4 3 2 1

    <8> DDR_B_DQS#[0..7] +1.8VU +1.8VU +1.8VU +1.8VU


    <8> DDR_B_DQS[0..7] +1.8VU +1.8VU
    UD21 @ UD22 @
    <8> DDR_B_D[0..63]

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    A3 P9 DDR_B_D27 A3 P9 DDR_B_D61
    A4 VDD1 DQ0 N9 DDR_B_D26 A4 VDD1 DQ0 N9 DDR_B_D57
    <23,8> DDR_B_CA1_[0..9] 1 1 VDD1 DQ1 1 1 VDD1 DQ1

    1
    CD90

    CD162

    CD163

    CD38

    CD144

    CD165
    A5 N10 DDR_B_D29 A5 N10 DDR_B_D63
    A6 VDD1 DQ2 N11 DDR_B_D24 A6 VDD1 DQ2 N11 DDR_B_D59
    <23,8> DDR_B_CA2_[0..9] VDD1 DQ3 VDD1 DQ3
    A10 M8 DDR_B_D30 A10 M8 DDR_B_D60

    2
    2 2 U3 VDD1 DQ4 M9 DDR_B_D31 2 2 U3 VDD1 DQ4 M9 DDR_B_D56
    U4 VDD1 DQ5 M10 DDR_B_D25 U4 VDD1 DQ5 M10 DDR_B_D62
    U5 VDD1 DQ6 M11 DDR_B_D28 U5 VDD1 DQ6 M11 DDR_B_D58
    U6 VDD1 DQ7 F11 DDR_B_D2 U6 VDD1 DQ7 F11 DDR_B_D39
    U10 VDD1 DQ8 F10 DDR_B_D1 U10 VDD1 DQ8 F10 DDR_B_D38
    +1.2V_DDR VDD1 DQ9 F9 DDR_B_D4 +1.2V_DDR VDD1 DQ9 F9 DDR_B_D34
    DQ10 F8 DDR_B_D6 DQ10 F8 DDR_B_D33
    D
    A8 DQ11 E11 DDR_B_D0 A8 DQ11 E11 DDR_B_D32 D
    A9 VDD2 DQ12 E10 DDR_B_D5 A9 VDD2 DQ12 E10 DDR_B_D37
    +1.2V_DDR +1.2V_DDR D4 VDD2 DQ13 E9 DDR_B_D7 +1.2V_DDR +1.2V_DDR D4 VDD2 DQ13 E9 DDR_B_D35
    D5 VDD2 DQ14 D9 DDR_B_D3 D5 VDD2 DQ14 D9 DDR_B_D36
    D6 VDD2 DQ15 T8 DDR_B_D14 D6 VDD2 DQ15 T8 DDR_B_D55
    G5 VDD2 DQ16 T9 DDR_B_D10 G5 VDD2 DQ16 T9 DDR_B_D50
    VDD2 DQ17 VDD2 DQ17
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    H5 T10 DDR_B_D9 H5 T10 DDR_B_D48
    H6 VDD2 DQ18 T11 DDR_B_D8 H6 VDD2 DQ18 T11 DDR_B_D49
    1 1 1 VDD2 DQ19 1 1 1 VDD2 DQ19
    1

    1
    CD30

    CD85

    CD89

    CD91

    CD88

    CD177

    CD178

    CD179
    H12 R8 DDR_B_D15 H12 R8 DDR_B_D54
    J5 VDD2 DQ20 R9 DDR_B_D11 J5 VDD2 DQ20 R9 DDR_B_D51
    J6 VDD2 DQ21 R10 DDR_B_D13 J6 VDD2 DQ21 R10 DDR_B_D53
    2

    2
    2 2 2 K5 VDD2 DQ22 R11 DDR_B_D12 2 2 2 K5 VDD2 DQ22 R11 DDR_B_D52
    K6 VDD2 DQ23 C11 DDR_B_D18 K6 VDD2 DQ23 C11 DDR_B_D46
    K12 VDD2 DQ24 C10 DDR_B_D23 K12 VDD2 DQ24 C10 DDR_B_D44
    L5 VDD2 DQ25 C9 DDR_B_D22 L5 VDD2 DQ25 C9 DDR_B_D45
    P4 VDD2 DQ26 C8 DDR_B_D21 P4 VDD2 DQ26 C8 DDR_B_D41
    P5 VDD2 DQ27 B11 DDR_B_D19 P5 VDD2 DQ27 B11 DDR_B_D47
    P6 VDD2 DQ28 B10 DDR_B_D16 P6 VDD2 DQ28 B10 DDR_B_D43
    U8 VDD2 DQ29 B9 DDR_B_D17 U8 VDD2 DQ29 B9 DDR_B_D42
    U9 VDD2 DQ30 B8 DDR_B_D20 U9 VDD2 DQ30 B8 DDR_B_D40
    +1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR VDD2 DQ31 +1.2V_DDR VDD2 DQ31
    +1.2V_DDR +1.2V_DDR +1.2V_DDR
    Closed to UD21 A11 R2 DDR_B_CA1_0 A11 R2 DDR_B_CA2_0
    C12 VDDQ CA0 P2 DDR_B_CA1_1 C12 VDDQ CA0 P2 DDR_B_CA2_1
    VDDQ CA1 Closed to UD22 VDDQ CA1
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    0.1U_0402_16V7K~D

    0.1U_0402_16V7K~D

    E8 N2 DDR_B_CA1_2 E8 N2 DDR_B_CA2_2
    VDDQ CA2 VDDQ CA2

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    0.1U_0402_16V7K~D

    0.1U_0402_16V7K~D
    1 1 1 1 1 1 E12 N3 DDR_B_CA1_3 E12 N3 DDR_B_CA2_3
    VDDQ CA3 VDDQ CA3
    1
    CD58

    CD173

    CD174

    CD175

    CD176

    G12 M3 DDR_B_CA1_4 1 1 1 1 1 1 G12 M3 DDR_B_CA2_4


    VDDQ CA4 VDDQ CA4

    1
    CD166

    CD167

    CD60

    CD87

    CD170

    CD171

    CD172
    H8 F3 DDR_B_CA1_5 H8 F3 DDR_B_CA2_5
    VDDQ CA5 VDDQ CA5

    CD168

    CD169
    H9 E3 DDR_B_CA1_6 H9 E3 DDR_B_CA2_6
    2

    2 2 2 2 2 2 H11 VDDQ CA6 E2 DDR_B_CA1_7 H11 VDDQ CA6 E2 DDR_B_CA2_7

    2
    J9 VDDQ CA7 D2 DDR_B_CA1_8 2 2 2 2 2 2 J9 VDDQ CA7 D2 DDR_B_CA2_8
    J10 VDDQ CA8 C2 DDR_B_CA1_9 J10 VDDQ CA8 C2 DDR_B_CA2_9
    K8 VDDQ CA9 K8 VDDQ CA9
    K11 VDDQ K11 VDDQ
    L12 VDDQ L10 DDR_B_DQS3 L12 VDDQ L10 DDR_B_DQS7
    N8 VDDQ DQS0 G10 DDR_B_DQS0 N8 VDDQ DQS0 G10 DDR_B_DQS4
    N12 VDDQ DQS1 P10 DDR_B_DQS1 N12 VDDQ DQS1 P10 DDR_B_DQS6
    R12 VDDQ DQS2 D10 DDR_B_DQS2 R12 VDDQ DQS2 D10 DDR_B_DQS5
    C C
    U11 VDDQ DQS3 U11 VDDQ DQS3
    +1.2V_DDR VDDQ +1.2V_DDR +1.2V_DDR +1.2V_DDR VDDQ
    +1.2V_DDR +1.2V_DDR L11 DDR_B_DQS#3 L11 DDR_B_DQS#7
    F2 DQS0# G11 DDR_B_DQS#0 F2 DQS0# G11 DDR_B_DQS#4
    G2 VDDCA DQS1# P11 DDR_B_DQS#1 G2 VDDCA DQS1# P11 DDR_B_DQS#6
    VDDCA DQS2# VDDCA DQS2#

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    H3 D11 DDR_B_DQS#2 H3 D11 DDR_B_DQS#5
    VDDCA DQS3# VDDCA DQS3#
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    L2 1 1 L2
    VDDCA VDDCA

    1
    CD64

    CD57

    CD59
    1 1 M2 M2
    VDDCA VDDCA
    1
    CD62

    CD61

    CD63

    L8 L8
    DM0 G8 DM0 G8

    2
    A1 DM1 P8 2 2 A1 DM1 P8
    2

    2 2 A2 NC DM2 D8 A2 NC DM2 D8
    A12 NC DM3 A12 NC DM3
    A13 NC A13 NC
    B1 NC B3 DDR_B0_ZQ0 RD57 1 2 240_0402_1% B1 NC B3 DDR_B1_ZQ0 RD55 1 2 240_0402_1%
    B13 NC ZQ0 B4 DDR_B0_ZQ1 RD58 1 2 240_0402_1% B13 NC ZQ0 B4 DDR_B1_ZQ1 RD56 1 2 240_0402_1%
    C4 NC ZQ1 C4 NC ZQ1
    K9 NC K9 NC
    R3 NC K3 R3 NC K3
    NC CKE0 DDR_B_CKE0 <23,8> NC CKE0 DDR_B_CKE2 <23,8>
    T1 K4 DDR_B_CKE1 <23,8> T1 K4 DDR_B_CKE3 <23,8>
    T13 NC CKE1 T13 NC CKE1
    U1 NC U1 NC
    U2 NC L3 DDR_B_CS#0 U2 NC L3 DDR_B_CS#0
    NC CS0# DDR_B_CS#0 <23,8> NC CS0#
    U12 L4 DDR_B_CS#1 U12 L4 DDR_B_CS#1
    NC CS1# DDR_B_CS#1 <23,8> NC CS1#
    U13 U13
    NC NC
    J3 DDR_B_CLK0 <23,8> J3 DDR_B_CLK1 <23,8>
    P3 CK J2 P3 CK J2
    VSSCA CK# DDR_B_CLK#0 <23,8> All VREF traces should VSSCA CK# DDR_B_CLK#1 <23,8>
    M4 have 10 mil trace width M4
    J4 VSSCA J4 VSSCA
    G4 VSSCA J8 DDR_B_ODT0 G4 VSSCA J8 DDR_B_ODT0
    VSSCA ODT DDR_B_ODT0 <23,8> VSSCA ODT
    G3 G3
    F4 VSSCA F4 VSSCA
    D3 VSSCA J11 D3 VSSCA J11
    VSSCA Vref_DQ +VREFDQ_B VSSCA Vref_DQ +VREFDQ_B
    C3 H4 +VREFCA C3 H4 +VREFCA
    VSSCA Vref_CA VSSCA Vref_CA

    B B
    T12 B2 T12 B2
    T6 VSSQ VSS B5 T6 VSSQ VSS B5
    VSSQ VSS Closed to DRAM VSSQ VSS Closed to DRAM
    R6 C5 R6 C5
    P12 VSSQ VSS E4 +VREFDQ_B +VREFCA P12 VSSQ VSS E4 +VREFDQ_B +VREFCA
    N6 VSSQ VSS E5 N6 VSSQ VSS E5
    M12 VSSQ VSS F5 M12 VSSQ VSS F5
    VSSQ VSS VSSQ VSS
    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D
    M6 H2 M6 H2
    L9 VSSQ VSS J12 L9 VSSQ VSS J12
    K10 VSSQ VSS K2 K10 VSSQ VSS K2
    VSSQ VSS 1 1 R04_0603: Change 0.047uF CPN VSSQ VSS 1 1
    CD119

    CD183

    CD120

    CD184
    H10 L6 H10 L6
    G9 VSSQ VSS M5 G9 VSSQ VSS M5
    G6 VSSQ VSS N4 G6 VSSQ VSS N4
    F12 VSSQ VSS N5 2 2 F12 VSSQ VSS N5 2 2
    F6 VSSQ VSS R4 F6 VSSQ VSS R4
    E6 VSSQ VSS R5 E6 VSSQ VSS R5
    D12 VSSQ VSS T2 D12 VSSQ VSS T2
    C6 VSSQ VSS T3 C6 VSSQ VSS T3
    B12 VSSQ VSS T4 B12 VSSQ VSS T4
    B6 VSSQ VSS T5 B6 VSSQ VSS T5
    VSSQ VSS VSSQ VSS R04_0603: Change 0.047uF CPN

    H9CCNNN8JTMLAR-NTM_FBGA178~D H9CCNNN8JTMLAR-NTM_FBGA178~D

    Decoupling per DRAM device


    VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF
    VDDCA 2x 0402 1uF 1x 0603 10uF
    VDD2 3x 0402 1uF 1x 0603 10uF
    VDD1 2x 0402 1uF 1x 0603 10uF
    intel uesd 0201 for 0.1uF

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P22-DDRIII Channel B
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 22 of 59
    5 4 3 2 1
    5 4 3 2 1

    +1.2V_DDR

    M3 M1

    1
    VREF traces should be at least 20 mils wide
    with 20 mils spacing to other signals/planes.
    RD17
    8.2K_0402_1%

    2
    RD111
    1 2
    <8> +V_DDR_REF_CA +VREFCA
    1
    4.99_0402_1%~D
    CD185
    0.022U_0402_16V7K~D

    1
    D 2 D

    RD19

    1
    8.2K_0402_1%
    RD112

    2
    24.9_0402_1%

    2
    +1.2V_DDR +1.2V_DDR

    M3 M1 M3 M1

    1
    RD21 RD22
    8.2K_0402_1% 8.2K_0402_1%

    2
    RD113 RD114
    1 2 1 2
    <8> +V_DDR_REFA_R +VREFDQ_A <8> +V_DDR_REFB_R +VREFDQ_B

    1 10_0402_1%~D 1 10_0402_1%~D

    CD186 CD187

    1
    0.022U_0402_16V7K~D 0.022U_0402_16V7K~D
    2 2
    RD25 RD26

    1
    8.2K_0402_1% 8.2K_0402_1%
    1

    RD116

    2
    RD115 24.9_0402_1%
    24.9_0402_1%
    C C

    2
    2

    +0.6VS +0.6VS

    RD59 1 2 68_0402_1% RD60 1 2 68_0402_1%


    <21,8> DDR_A_CA1_0 <22,8> DDR_B_CA1_0
    RD61 1 2 68_0402_1% RD62 1 2 68_0402_1%
    <21,8> DDR_A_CA1_1 1 2 <22,8> DDR_B_CA1_1 1 2
    RD63 68_0402_1% RD64 68_0402_1%
    <21,8> DDR_A_CA1_2 <22,8> DDR_B_CA1_2
    RD65 1 2 68_0402_1% RD66 1 2 68_0402_1%
    <21,8> DDR_A_CA1_3 1 2 <22,8> DDR_B_CA1_3 1 2
    RD67 68_0402_1% RD68 68_0402_1%
    <21,8> DDR_A_CA1_4 <22,8> DDR_B_CA1_4
    RD69 1 2 68_0402_1% RD70 1 2 68_0402_1%
    <21,8> DDR_A_CA1_5 <22,8> DDR_B_CA1_5
    RD71 1 2 68_0402_1% RD72 1 2 68_0402_1%
    <21,8> DDR_A_CA1_6 1 2 <22,8> DDR_B_CA1_6 1 2
    RD73 68_0402_1% RD74 68_0402_1%
    <21,8> DDR_A_CA1_7 <22,8> DDR_B_CA1_7
    RD75 1 2 68_0402_1% RD76 1 2 68_0402_1%
    <21,8> DDR_A_CA1_8 1 2 <22,8> DDR_B_CA1_8 1 2
    RD77 68_0402_1% RD78 68_0402_1%
    <21,8> DDR_A_CA1_9 <22,8> DDR_B_CA1_9

    RD79 1 2 68_0402_1% RD80 1 2 68_0402_1%


    <21,8> DDR_A_CA2_0 <22,8> DDR_B_CA2_0
    RD81 1 2 68_0402_1% RD82 1 2 68_0402_1%
    <21,8> DDR_A_CA2_1 <22,8> DDR_B_CA2_1
    RD83 1 2 68_0402_1% RD84 1 2 68_0402_1%
    <21,8> DDR_A_CA2_2 1 2 <22,8> DDR_B_CA2_2 1 2
    RD85 68_0402_1% RD86 68_0402_1%
    <21,8> DDR_A_CA2_3 <22,8> DDR_B_CA2_3
    RD87 1 2 68_0402_1% RD88 1 2 68_0402_1%
    <21,8> DDR_A_CA2_4 1 2 <22,8> DDR_B_CA2_4 1 2
    RD89 68_0402_1% RD90 68_0402_1%
    <21,8> DDR_A_CA2_5 <22,8> DDR_B_CA2_5
    RD91 1 2 68_0402_1% RD92 1 2 68_0402_1%
    <21,8> DDR_A_CA2_6 <22,8> DDR_B_CA2_6
    RD93 1 2 68_0402_1% RD94 1 2 68_0402_1%
    <21,8> DDR_A_CA2_7 1 2 <22,8> DDR_B_CA2_7 1 2
    RD95 68_0402_1% RD96 68_0402_1%
    <21,8> DDR_A_CA2_8 <22,8> DDR_B_CA2_8
    RD97 1 2 68_0402_1% RD98 1 2 68_0402_1%
    <21,8> DDR_A_CA2_9 <22,8> DDR_B_CA2_9

    RD99 1 2 80.6_0402_1%~D RD100 1 2 80.6_0402_1%~D


    <21,8> DDR_A_CS#0 <22,8> DDR_B_CS#0
    <21,8> DDR_A_CS#1 RD101 1 2 80.6_0402_1%~D <22,8> DDR_B_CS#1 RD102 1 2 80.6_0402_1%~D

    +0.6VS
    B B
    RD103 1 2 80.6_0402_1%~D RD104 1 2 80.6_0402_1%~D
    <21,8> DDR_A_CKE0 <22,8> DDR_B_CKE0
    RD105 1 2 80.6_0402_1%~D RD106 1 2 80.6_0402_1%~D
    <21,8> DDR_A_CKE1 <22,8> DDR_B_CKE1
    <21,8> DDR_A_CKE2 RD107 1 2 80.6_0402_1%~D <22,8> DDR_B_CKE2 RD108 1 2 80.6_0402_1%~D
    RD109 1 2 80.6_0402_1%~D RD110 1 2 80.6_0402_1%~D
    <21,8> DDR_A_CKE3 <22,8> DDR_B_CKE3
    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    22U_0603_6.3V6M~D
    1 1 1 1 1

    CD196
    CD129 CD132 CD133 CD135 RD117 1 2 80.6_0402_1%~D RD118 1 2 80.6_0402_1%~D
    <21,8> DDR_A_ODT0 <22,8> DDR_B_ODT0

    2 2 2 2 2

    +0.6VS +0.6VS

    <21,8> DDR_A_CLK0 RD35 1 2 37.4_0402_1%~D <22,8> DDR_B_CLK0 RD36 1 2 37.4_0402_1%~D

    <21,8> DDR_A_CLK#0 RD37 1 2 37.4_0402_1%~D <22,8> DDR_B_CLK#0 RD38 1 2 37.4_0402_1%~D

    +0.6VS
    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    22U_0603_6.3V6M~D

    1 1 1 1 1
    CD197

    CD136 CD139 CD140 CD142


    +0.6VS +0.6VS

    2 2 2 2 2

    <21,8> DDR_A_CLK1 RD46 1 2 37.4_0402_1%~D <22,8> DDR_B_CLK1 RD47 1 2 37.4_0402_1%~D

    <21,8> DDR_A_CLK#1 RD45 1 2 37.4_0402_1%~D <22,8> DDR_B_CLK#1 RD48 1 2 37.4_0402_1%~D

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P23-DDRIII Vref & Termination
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 23 of 59
    5 4 3 2 1
    5 4 3 2 1

    JIO1
    1
    D +5VALW +3VALW +3VS_CR +3VS 2 1 D
    <11> USB3RN1 2
    3
    4 3
    <11> USB3RP1 4
    1 1 1 1 5
    6 5
    C1321 C1322 C1325 C1324 7 6
    1U_0402_6.3V6K~D 0.1U_0402_10V7K 1U_0402_6.3V6K~D 0.1U_0402_10V7K 8 7
    2 2 2 2 <11> USB3TN1 9 8
    10 9
    <11> USB3TP1 11 10
    12 11
    13 12
    CH13 1 2 0.1U_0402_10V7K~D PCIE_PTX_CARDRX_P6_C 14 13
    <11> PCIE_PTX_CARDRX_P6 14
    15
    CH14 1 2 0.1U_0402_10V7K~D PCIE_PTX_CARDRX_N6_C 16 15
    <11> PCIE_PTX_CARDRX_N6 16
    17
    18 17
    <38> USB_PWR_SHR_EN_R# 19 18
    20 19
    <12> CLK_PCIE_MMI 21 20
    22 21
    <12> CLK_PCIE_MMI# 23 22
    24 23
    <11> USB_OC1# 24
    25
    C 25 C
    26
    <11> PCIE_PRX_CARDTX_P6 26
    27
    27
    NPI Stage Power Switch
    28
    <11> PCIE_PRX_CARDTX_N6 28
    29
    30 29
    <12> CLKREQ_PCIE#5 31 30
    32 31
    <11> USB20_P1 32
    33
    34 33
    <11> USB20_N1 34
    3 @ SW2 4 PBTN_SW# PBTN_SW# 35
    <12,37> PBTN_SW# 36 35
    <37> USB1_DET# 37 36
    <10> HOST_SD_WP# 38 37
    <12,28,29,30,37,39> PCH_PLTRST#_EC 39 38
    1 2 <38> USB_PWR_SHR_VBUS_EN_R 40 39
    41 40
    SKRBAAE010_4P <37> PWRBTN_LED# 41
    42
    <9> MEDIACARD_IRQ# 43 42
    44 43
    <37> LID_SW_IN# 44
    +3VS_CR 45
    46 45
    47 46
    48 47
    49 48
    B +3VALW B
    50 49
    +3VS 50
    51
    52 51
    +5VALW 52
    53
    54 53
    55 54
    56 55
    57 56
    58 57
    59 58
    60 59
    61 60
    61 62
    GND 63
    GND

    JXT_FP270H-061G1AM
    CONN@

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P24-BTB CONN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 24 of 59
    5 4 3 2 1
    5 4 3 2 1

    JCAM +LCDVDD

    Camera + Touch Screen 8


    7 GND
    GND
    eDP Conn JEDP

    .1U_0402_16V7K~D

    10U_0603_6.3V6M~D
    40 45
    +3VS 40 G5
    <13> CAM_CBL_DET# RH438 1 2 1K_0402_5%~D CAM_CBL_DET#_R 6 0.1U_0402_10V7K L57 EMI@ 1 1 1 EMI@ 39 44
    6 39 G4

    C1145

    C1143
    5 C1060 1 2 1 2 38 43

    C6
    USB20_P5_CONN <7> eDP_TXP_P0 eDP_TXP_P0_C eDP_TXP_P0_CONN eDP_TXN_P3_CONN

    15P_0402_50V8J
    USB20_N5_CONN 4 5 eDP_TXP_P3_CONN 37 38 G3 42
    3 4 36 37 G2 41
    CAM_CBL_DET#_R 2 3 C1062 1 2 eDP_TXN_P0_C 4 3 eDP_TXN_P0_CONN 2 2 2 eDP_TXN_P2_CONN 35 36 G1

    Camera L55 EMI@


    +3VS_CAM 1 2
    1
    CVILU_CI1806M2HRP-NH
    <7> eDP_TXN_P0
    0.1U_0402_10V7K HCM1012GH900BP
    eDP_TXP_P2_CONN

    eDP_TXN_P1_CONN
    34
    33
    32
    35
    34
    33
    1 2 USB20_P5_CONN CONN@ eDP_TXP_P1_CONN 31 32
    <11> USB20_P5 +3VS_CAM 31
    30
    eDP_TXN_P0_CONN 29 30
    4 3 USB20_N5_CONN 0.1U_0402_10V7K L56 EMI@ eDP_TXP_P0_CONN 28 29
    <11> USB20_N5 28
    1 EMI@ C1061 1 2 eDP_TXP_P1_C 1 2 eDP_TXP_P1_CONN 27

    C1221
    1 <7> eDP_TXP_P1

    1U_0402_6.3V6K~D
    D 27 D

    C4
    MCM1012B900F06BP_4P eDP_AUXP_CONN 26

    15P_0402_50V8J
    26

    2
    eDP_AUXN_CONN 25
    1 2 4 3 24 25

    DI3 EMI@
    <7> eDP_TXN_P1 C1063 eDP_TXN_P1_C eDP_TXN_P1_CONN
    24

    L30ESDL5V0C3-2_SOT23-3
    2 2 23
    +LCDVDD 23
    0.1U_0402_10V7K HCM1012GH900BP 22
    21 22
    20 21
    19 20
    <37> LCD_TST 19
    18
    0.1U_0402_10V7K L59 EMI@ 17 18

    1
    C1067 1 2 eDP_TXP_P2_C 1 2 eDP_TXP_P2_CONN 16 17
    <7> eDP_TXP_P2 16
    15
    14 15
    <7> EDP_HPD 14
    C1066 1 2 eDP_TXN_P2_C 4 3 eDP_TXN_P2_CONN 13

    Touch Screen <7> eDP_TXN_P2


    0.1U_0402_10V7K HCM1012GH900BP
    12
    11
    10
    13
    12
    11
    JTS DISPOFF# 9 10
    1 INV_PWM_R 8 9
    ML9 EMI@ USB20_P4_CONN 2 1 7 8
    2 +3VS_CR 7
    4 3 USB20_P4_CONN USB20_N4_CONN 3 0.1U_0402_10V7K L60 EMI@ I2C0_SDA_EDP 6
    <11> USB20_P4 3 6
    4 C1069 1 2 eDP_TXP_P3_C 1 2 eDP_TXP_P3_CONN 5
    4 <7> eDP_TXP_P3 +INV_PWR_SRC 5
    5 4
    1 2 <13> TOUCH_SCREEN_PD# 6 5 3 4
    <11> USB20_N4 USB20_N4_CONN +3VS_TSLDO 6 C1068 1 2 eDP_TXN_P3_C 4 3 eDP_TXN_P3_CONN 2 3
    <7> eDP_TXN_P3 2
    MCM1012B900F06BP_4P I2C0_SCK_EDP 1
    2 1

    3
    7 0.1U_0402_10V7K HCM1012GH900BP
    +3VS_TSLDO 8 GND
    DI4 EMI@

    B+ ACES_50398-04041-001
    GND
    L30ESDL5V0C3-2_SOT23-3

    CONN@
    CVILU_CI1806M2HRP-NH
    1 EMI@ CONN@

    C1222
    1

    1U_0402_6.3V6K~D

    0.1U_0402_25V6K~D

    0.1U_0402_25V6K~D

    0.1U_0402_25V6K~D

    0.1U_0402_25V6K~D
    C5
    L58 EMI@ 1 1 1 1

    15P_0402_50V8J

    C614

    C615

    C616

    C617
    <7> eDP_AUXN C1065 1 2 eDP_AUXN_C 1 2 eDP_AUXN_CONN
    2 2 0.1U_0402_10V7K
    1

    C1064 1 2 eDP_AUXP_C 4 3 eDP_AUXP_CONN 2 2 2 2


    <7> eDP_AUXP
    C 0.1U_0402_10V7K HCM1012GH900BP C

    R04_0608: Change eDP CMC footprint

    Touch Screen LDO eDP BackLight Power B+ +INV_PWR_SRC

    @ R531 1 2 0_0603_5%~D

    +3VS_TS Q70
    +3VS_TSLDO SI3457BDV-T1-E3_TSOP6~D

    D
    6
    60mil 60mil

    S
    1 @ 2 4 5
    RH357 0_0603_5% 2
    1

    G
    1
    U728 @ C613 R535

    3
    1 5 0.1U_0402_25V6K~D 1M_0402_5%~D
    VIN VOUT
    C1223

    1 1
    1U_0402_6.3V6K~D

    0.1U_0402_25V6K~D
    2.2U_0603_6.3V6K~D

    2 2
    1

    10U_0603_25V6M
    2
    GND

    1
    C8

    @ @
    3 4 EN_INVPWR_R

    C612

    @ C2982
    2 EN NC 2

    2
    1
    G9091-330TO1U_TSOT-23-5 2

    R1161 2 1 220K_0402_5%~D EN_INVPWR R536


    100K_0402_5%~D

    2
    B B

    1
    D
    <37> EN_INVPWR EN_INVPWR 2 Q71
    G L2N7002WT1G_SC-70-3
    S

    3
    DBC delay schematic

    +LCDVDD
    @ U48
    1 8 R289 2 @ 1 0_0402_1%
    NC VCC

    BackLight PWM Control <37,38,41> USBC_MCP23017_SMBCLK


    2

    3
    SCL0 SCL1
    7

    6
    I2C0_SCK_EDP@ R291 2

    I2C0_SDA_EDP@ R292 2
    1 0_0402_5%~D

    1 0_0402_5%~D
    I2C0_SCK_EDP_PCH <10>

    <37,38,41> USBC_MCP23017_SMBDAT SDA0 SDA1 I2C0_SDA_EDP_PCH <10>


    D72
    2 4 5
    <7> PANEL_BKLEN GND EN DBC_I2C_EN <38>
    1 DISPOFF# PCA9515BDGKR_VSSOP8
    1

    3 +LCDVDD
    <38> PANEL_BKEN_EC
    R540
    BAT54CW-7-F_SOT323-3~D 220K_0402_5%~D
    A A
    I2C0_SCK_EDP 2.2K_0402_5% 2 1 @ R287
    2

    I2C0_SDA_EDP 2.2K_0402_5% 2 1 @ R288

    D73
    <7> EDP_BIA_PWM 2

    1 INV_PWM_R DELL CONFIDENTIAL/PROPRIETARY


    Security Classification Compal Secret Data Compal Electronics, Inc.
    1

    3 1
    <37> BIA_PWM_EC
    R545 2013/07/04 2013/10/28 Title
    Issued Date Deciphered Date
    BAT54CW-7-F_SOT323-3~D @MC3
    @ MC3
    220K_0402_5%~D
    2
    680P_0402_50V7K~D
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P25-eDP/ Camera CONN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    2

    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 25 of 59
    5 4 3 2 1
    5 4 3 2 1

    LA2
    BLM15PX600SN1D_2P
    +PVDD2
    HD Audio Codec moat
    2 1 50mil
    +5VS_AUDIO +AVDD1 +5VS_AUDIO

    0.1U_0402_16V7K~N
    10U_0805_10V6K

    0.1U_0402_16V7K~N
    1 1 1 1

    10U_0805_10V6K
    BLM21PG600SN1D_0805~D LA3

    CA98

    CA97

    CA99

    CA100
    2 1
    2 2 2 2
    1

    10U_0805_10V6K

    CA101
    D D
    2

    +AVDD1

    LA4 +PVDD1 Place close to Pin26


    BLM15PX600SN1D_2P AGND
    2 1 50mil
    +5VS_AUDIO

    10U_0805_10V6K
    0.1U_0402_16V7K~N
    1 1

    0.1U_0402_16V7K~N

    0.1U_0402_16V7K~N

    CA103

    CA102
    1 1
    10U_0805_10V6K

    10U_0805_10V6K

    CA2

    CA3
    1 1
    moat
    CA112

    CA111
    2 2
    2 2
    2 2

    AGND +AVDD2 +1.8VS_AUDIO Beep sound moat


    RA63
    2 @ 1

    Place close to Pin9 CA34


    +DVDDIO 0_0402_1% RA24

    10U_0603_6.3V6M~D
    1 1 <37> BEEP 1 2 1 2 MONO_IN

    0.1U_0402_10V7K
    +1.8VS_AUDIO

    CA80

    CA82
    0.1U_0402_16V7K~N

    1 1 1K_0402_1%
    10U_0805_10V6K

    Place close to Pin1 0.1U_0402_10V7K


    CA6

    CA7

    +DVDD 2 2

    10U_0603_6.3V6M~D
    RA25

    0.1U_0402_10V7K
    0.1U_0402_16V7K~N
    2 2 1 2
    1 1 1 1 <13> SPKR
    10U_0805_10V6K

    CA5

    CA4

    CA78

    CA83

    1
    1K_0402_1% 1
    R7 @ CA33
    2 2 2 2 100P_0402_50V8J~D
    1K_0402_1%
    AGND
    2

    2
    C C

    41

    46

    26

    40

    36
    1

    9
    UA2 Close to UA2 Pin2

    PVDD1

    PVDD2

    AVDD1

    AVDD2
    DVDD

    CPVDD
    DVDD-IO
    11
    12 I2C_SDA 31
    I2C_SCL LINE1-VREFO-L LINE1-VREFO_L <27>
    30
    LINE1-VREFO-R LINE1-VREFO_R <27>
    HDA_SYNC_R 10 29
    <13> HDA_SYNC_R SYNC MIC2-VREFO MIC2-VREFO <27>
    <13> HDA_BIT_CLK_R HDA_BIT_CLK_R 6 28 AUDIO_VREF
    HDA_SDOUT_R 5 BIT-CLK VREF 35 CA86 2 1 2.2U_0603_6.3V6K~D
    <13> HDA_SDOUT_R SDATA-OUT CBN R04_0526: Change CA86 size to 0603
    <13> HDA_SDIN0 RA62 1 2 33_0402_5%~D HDA_SDIN0_R 8 37
    SDATA-IN CBP
    4 20 RA54 2 @ 1 0_0402_1%
    EAPD/DC DET 5VSTB +RTCVCC
    2
    <35> DMIC_DAT_CODEC GPIO0/DMIC-DATA12
    RA58 1 2 22_0402_5% DMIC_CLK_CODEC_R 3 34 CPVEE
    <35> DMIC_CLK_CODEC GPIO1/DMIC-CLK CPVEE
    <27,38> NB_MUTE# RA59 1 @ 2 0_0402_1% HDA_AUDIO_PD# 47
    48 PDB
    SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI
    27
    CA110 1 2 10U_0603_6.3V6M~D 39 LDO1-CAP 17
    LDO2-CAP MIC2-L/RING2 RING2 <27>
    CA108 1 2 10U_0603_6.3V6M~D 7 18
    100K_0402_1%~D

    SLEEVE <27>
    10U_0603_6.3V6M~D

    LDO3-CAP MIC2-R/SLEEVE
    1

    1 19 CA107 2 1 10U_0603_6.3V6M~D
    MIC-CAP AGND
    24
    RA77

    42 LINE2-L 23
    CA109

    <27> SPK_OUT_L+ SPK-L+ LINE2-R


    AGND 43 22
    2 <27> SPK_OUT_L- SPK-L- LINE1-L LINE1_L <27>
    <27> SPK_OUT_R- 44 21 LINE1_R <27>
    2

    45 SPK-R- LINE1-R 16 MONO_IN AUDIO_VREF


    <27> SPK_OUT_R+ SPK-R+ PCBEEP 32
    HP-OUT-L HP2_D_L <27>
    13 33 HP2_D_R <27> CPVEE
    14 HP/LINE1 JD1 HP-OUT-R
    15 MIC2/LINE2 JD2 25
    moat SPDIFO/FRONT JD3/GPIO3 AVSS1 38

    CA87
    C1205
    AGND AVSS2 49
    THERMAL PAD 1 1

    +DVDD RA76 1 2 100K_0402_1%~D

    2.2U_0603_6.3V6K~D
    ALC3246-CG_MQFN48_6X6

    2.2U_0402_6.3V6M
    B 2 2 B

    RA75
    200K_0402_1% AGND
    <27> JACK_PLUG_DL# 1 2

    1
    @ CA106
    0.1U_0402_10V7K AGND
    2
    R04_0526: Change C1205 from 1U to 2.2U moat
    1 2
    +3VS_AUDIO +DVDD
    LA14
    2.2U_0402_6.3V6M

    0.1U_0402_10V7K

    BLM15BB220SN1D_2P 1 1
    CA42

    CA31

    @ JPA1
    1 2 2 1
    +1.8VS_AUDIO 2 2
    @ RA81 JUMP_43X39
    0_0603_5%~D CA18 close Close to UA2 Close to UA2 @ JPA2
    2 1
    UA2 Pin12 HDA_SYNC_R HDA_BIT_CLK_R
    2 JUMP_43X39
    DMIC_CLK_CODEC 2
    2 EMI@ CA24 GND AGND
    10P_0402_50V8J~D EMI@ CA30
    EMI@ CA23 1 10P_0402_50V8J~D Near AVDD1 and AVDD2 power source input
    10P_0402_50V8J~D 1
    1
    For EMI @ JPA3
    DMIC_DAT_CODEC HDA_SDOUT_R 2 1

    2 @ 1
    3mA 10mil 2 2
    JUMP_43X39
    +3VS_AUDIO +DVDDIO
    EMI@ CA25 EMI@ CA27
    2.2U_0402_6.3V6M

    0.1U_0402_10V7K

    RA80 1 1 10P_0402_50V8J~D 10P_0402_50V8J~D GND AGND


    1 1
    CA105

    CA104

    A 0_0603_5% A
    Tied at one point only under
    1 2 2 2 Codec or near the Codec
    +1.8VS_AUDIO Reserved for EMI Reserved for EMI Reserved for EMI
    @ RA82
    0_0603_5%~D

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P26-Audio Codec
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 26 of 59
    5 4 3 2 1
    5 4 3 2 1

    Universal Audio Jack Int. Speaker Conn.

    100P_0402_50V8J~D

    100P_0402_50V8J~D
    L2
    BLM15PX181SN1D_2P
    40mil = For 4ohm 2W Speaker
    +3VS_AUDIO 1 2
    1 1 <26> SPK_OUT_L+

    CA68

    CA29
    RA27 AGND <26> SPK_OUT_L- 1 2
    2.2K_0402_5%~D L3
    1 2 BLM15PX181SN1D_2P
    <26> MIC2-VREFO

    1
    2 2

    1000P_0402_50V7K~D

    1000P_0402_50V7K~D
    @

    2
    1 2 RA19 2 2

    CA53

    CA55
    RA28 10K_0402_5%~D
    2.2K_0402_5%~D JHP1
    40mil
    Ring2
    7

    2
    D 1 1 D
    RA64 1 @ 2 0_0402_1% RING2_R 4
    <26> RING2 1 JSPK1
    HP2_D_L 1 2 HP2_D_L_R1 LA7 1 2 PBY100505T-700Y-N HP2_D_L_C 6
    <26> HP2_D_L 5 G2
    RA17 10_0402_5%
    5 DA3 EMI@ SPK_L+_C 4 G1

    1
    PJDLC05C_SOT23-3 SPK_L-_C 3 4
    JACK_PLUG SPK_R-_C 2 3
    6 SPK_R+_C 1 2
    HP2_D_R 1 2 HP2_D_R_R2 LA6 1 2 PBY100505T-700Y-N HP2_D_R_C 1
    <26> HP2_D_R
    RA15 10_0402_5% 2 ACES_50224-00401-001
    RA65 1 @ 2 0_0402_1% SLEEVE_R 3 CONN@
    <26> SLEEVE
    Sleeve

    DA2 EMI@

    DA1 EMI@
    SINGA_2SJ3095-022111F
    40mil CONN@ L4

    EMI@ DA5

    EMI@ DA7

    @ RA35

    @ RA30
    BLM15PX181SN1D_2P
    1 2
    <26> SPK_OUT_R-
    1 2
    <26> SPK_OUT_R+

    2
    100P_0402_50V8J~D

    100P_0402_50V8J~D

    100K_0402_5%~D
    L5

    1
    0_0402_1%
    BLM15PX181SN1D_2P

    AZ5125-02S.R7G_SOT23-3

    AZ5125-02S.R7G_SOT23-3
    AZ5123-01F.R7G_DFN1006P2X2

    AZ5123-01F.R7G_DFN1006P2X2

    1000P_0402_50V7K~D

    1000P_0402_50V7K~D
    1 1

    2
    CA28

    CA69
    2 2

    CA56

    CA54
    2

    2
    2 2
    1 1

    1
    DA4 EMI@

    1
    AGND AGND AGND PJDLC05C_SOT23-3

    C C

    RA48 1 2 4.7K_0402_5%~D
    <26> LINE1-VREFO_L
    RA49 1 2 4.7K_0402_5%~D
    <26> LINE1-VREFO_R

    CA70 1 2 4.7U_0402_6.3V6M LINE1_L_C RA50 1 2 1K_0402_1% HP2_D_L


    <26> LINE1_L
    CA71 1 2 4.7U_0402_6.3V6M LINE1_R_C RA51 1 2 1K_0402_1% HP2_D_R
    <26> LINE1_R
    1

    @ RA60 @ RA61
    9.09K_0402_1% 9.09K_0402_1%
    2

    AGND AGND

    B B

    Prevent S3/S4/S5 Background Noise. Reserved Delay cricutis


    ALC3234/3246 has already integrated this grounding circuit inside +3VS_AUDIO
    the pin20
    1

    1
    +3VS_AUDIO +RTCVCC RA31 1 @ 2
    @ RA37 @ RA38 0_0402_1% JACK_PLUG_DL# <26>
    SLEEVE_R 100K_0402_5%~D 100K_0402_5%~D
    1

    @ RA16

    1
    @ RA18 D
    2

    10K_0402_5%~D 100K_0402_5%~D JACK_PLUG_DL JACK_PLUG_DL 2 @


    3

    @ RA39 G QA6
    6

    D
    5 G 100K_0402_5%~D QA3B @ S DII-DMN65D8LW-7~D
    2

    3
    D
    S DMN66D0LDW-7_SOT363-6 1 2 2 G DMN66D0LDW-7_SOT363-6
    QA1A DMN66D0LDW-7_SOT363-6 S
    4

    @ @ QA3A
    1
    1

    D JACK_PLUG 5 G
    D

    1
    <26,38> NB_MUTE# RA57 1 @ 2 2 S @CA40
    @ CA40
    G QA9 AGND 0.1U_0402_25V6K~D @ RA20
    4

    1K_0402_5%~D S DII-DMN65D8LW-7~D 100K_0402_5%~D


    3
    1

    @ RING2_R
    @ RA41

    2
    100K_0402_5%~D 4/16, Reserved Delay cricutis 1 @
    6

    10U_0603_6.3V6M~D
    CA74
    D
    AGND
    2 G
    2

    S RA26 1 @ 2 0_0402_1%
    QA1B @ 2
    1

    DMN66D0LDW-7_SOT363-6
    AGND AGND AGND

    AGND AGND
    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P27-Audio Jack / Speaker
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 27 of 59
    5 4 3 2 1
    5 4 3 2 1

    TPM NOTE:
    Place 0.1 uF capacitors as close as
    possible to the device power pins
    NOTE:
    Follow the SPI topology layout guidelines
    in the relevant Intel Platform Design Guide +3VS_TPM
    D D

    TPM@

    TPM@

    TPM@

    TPM@
    C95 C96 C97 C94
    1 1 1 1

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    10U_0603_6.3V6M
    +3V_PCH +3VS_TPM
    2 2 2 2
    R1393 1 @ 2 0_0805_5%

    +3VS_TPM

    TPM@
    RH1261 2 10K_0201_5% TPM_PIRQ# R07_0720: Change TPM VSB power to "+3VALW" for DS3
    R04_0623: Change CPN +3VALW
    for TPM1.2 FW
    C C
    +3VS_TPM U15
    1 +TPM_LPM 2 1 +3VS_TPM
    1 @ 2 29 VSB 0_0402_5% RC229 @
    <12,34,56> SIO_SLP_S0# GPIO0/SDA/XOR_OUT
    RE92 0_0402_1% 30 8 +TPM_LPM
    TPM_LPM# 1 @ 2 3 GPIO1/SCL VDD 14 2 @ 1
    GPIO2/GPX VDD +3VS_TPM +3VS
    R1006 0_0402_1% 6 22 0_0402_1% RC228
    GPIO3/BADD VDD
    3

    G DMG2301U-7_SOT23-3
    PCH_SPI_CS2# 1 2 2 24 2
    RH127 100_0402_1% Q72 <9> PCH_SPI_SO_TPM 21 LAD0/MISO NC 7
    D <9> PCH_SPI_SI_TPM LAD1/MOSI NC
    TPM@ TPM@ TPM_PIRQ# 18 10
    1

    <9> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11


    LAD3 NC 25
    PCH_SPI_CLK_TPM 19 NC 26
    S <9> PCH_SPI_CLK_TPM LCKL/SCLK NC
    R04_0514: Change SB00000QP00 TPM_LPM# PCH_SPI_CS2# 20 31
    <9> PCH_SPI_CS2# LFRAME#/SCS# NC
    <12,24,29,30,37,39> PCH_PLTRST#_EC 17
    to SB00000PJ00 for completely replace 2 1 27 LRESET#/SPI_RST#/SRESET# 9
    SERIRQ GND
    1

    PCH_SPI_CS2# TPM@ R60 2 1 10K_0201_5% 13 16


    RE91 TPM@ @RC230
    @ RC230 0_0402_5% 28 CLKRUN#/GPIO4/SINT# GND 23
    LPCPD# GND 32
    10K_0402_5% GND
    4 33 +TPM_LPM
    5 PP PGND 12 close to U15.8
    2

    TEST Reserved

    TPM@

    TPM@
    C98 CA72

    4.7U_0402_6.3V6M
    NPCT650JA0YX 1 1

    0.1U_0201_10V6K
    B TPM@ B

    2 2

    @ C135
    2 1 PCH_SPI_CLK_TPM

    0.1U_0201_10V6K
    Reserve for EMI please close to U15

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P28-TPM
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 28 of 59
    5 4 3 2 1
    A B C D E

    M.2 Slot-A Key-A (WLAN)

    +3VS_NGFF

    RF Reserved.
    Slot A -DP
    ML10 EMI@
    <11> USB20_P3 4 3 USB20_P3_R Close to JNGFF

    1 1 1 1 EMI@ 1

    22U_0603_6.3V6M~D
    C712

    0.1U_0402_10V7K
    C715

    15P_0402_50V8J
    C1297
    1 2 USB20_N3_R
    <11> USB20_N3 JNGFF1
    MCM1012B900F06BP_4P 1 2
    USB20_P3_R 3 1 2 4 2 2 2 WLAN_WIGIG60GHZ_DIS#_R 2 1
    3 4 WLAN_WIGIG60GHZ_DIS# <38>
    USB20_N3_R 5 6
    7 5 6 DZ1
    7 RB751S40T1G_SOD523-2

    BT_RADIO_DIS#_R 2 1
    BT_RADIO_DIS# <38>
    8
    9 8 10 DZ2
    11 9 10 12 RB751S40T1G_SOD523-2
    13 11 12 14
    15 13 14 16
    17 15 16 18
    19 17 18 20
    21 19 20 22
    23 21 22 24
    CLK1_PCIE_WLAN 25 23 24 26
    CLK1_PCIE_WLAN# CH12 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_P5_C 27 25 26 28
    <11> PCIE_PTX_WLANRX_P5 27 28
    <11> PCIE_PTX_WLANRX_N5 CH11 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_N5_C 29 30 CL_RST#_R R1200 1 @ 2 0_0402_1%
    CL_RST# <9>
    31 29 30 32 CL_DAT_R R1210 1 @ 2 0_0402_1%
    31 32 CL_DAT <9>
    1@ 1@ <11> PCIE_PRX_WLANTX_P5 33 34 CL_CK_R R1212 1 @ 2 0_0402_1%
    33 34 CL_CK <9>
    15P_0402_50V8J
    C1301

    15P_0402_50V8J
    C1302

    35 36
    <11> PCIE_PRX_WLANTX_N5 35 36
    37 38
    CLK1_PCIE_WLAN 39 37 38 40
    2 2 <12> CLK1_PCIE_WLAN 39 40
    CLK1_PCIE_WLAN# 41 42 @ R1255 1 2 0_0402_5%
    <12> CLK1_PCIE_WLAN# 41 42 SUSCLK <12,30>
    43 44 PCH_PLTRST#_EC <12,24,28,30,37,39>
    45 43 44 46 BT_RADIO_DIS#_R
    <12> CLKREQ_PCIE#1 45 46
    47 48 WLAN_WIGIG60GHZ_DIS#_R
    <37> PCIE_WAKE# 49 47 48 50
    51 49 50 52
    53 51 52 54
    55 53 54 56
    57 55 56 58
    59 57 58 60 +3VS_NGFF
    59 60
    RF Reserved.
    61 62
    63 61 62 64
    2 2
    65 63 64 66
    67 65 66
    67 1 1 EMI@

    0.1U_0402_10V7K
    C713

    15P_0402_50V8J
    C1298
    1

    22U_0603_6.3V6M~D
    C716
    69 68
    GND GND 2 2
    2

    CONCR_213AAAA32FA
    CONN@

    R07_0731: Add +3VS_NGFF discharge circuit


    for WB leakage
    +3VS_NGFF
    1

    @ R80
    +3VS 80.6_0402_1%~D
    2
    1

    @ R81
    200K_0402_1%
    3
    DMN66D0LDW-7_SOT363-6
    @ QE14B
    2

    5
    4
    6
    DMN66D0LDW-7_SOT363-6
    @ QE14A

    3 3
    2
    <33,37> AUX_EN_WOWL
    1

    4 4

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P29-WLAN / BT (M.2)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 29 of 59
    A B C D E
    5 4 3 2 1

    M.2 Slot-C Key-M (SSD)

    +3.3VDX_SSD
    D D

    RF Reserved.
    JNGFF2 EMI@ EMI@

    4.7U_0603_6.3V6K
    C719

    .1U_0402_16V7K~D
    C720

    0.01U_0402_16V7K~D
    C721

    47P_0402_50V8J~D
    C722

    15P_0402_50V8J
    C1304
    1 2 1 1 1 1 1
    3 1 2 4
    5 3 4 6
    <11> PCIE_PRX_SSDTX_N9 5 6
    7 8
    <11> PCIE_PRX_SSDTX_P9 7 8 2 2 2 2 2
    9 10
    CD39 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_N9_C 11 9 10 12
    <11> PCIE_PTX_SSDRX_N9 11 12
    CD43 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_P9_C 13 14
    <11> PCIE_PTX_SSDRX_P9 13 14
    15 16
    17 15 16 18
    <11> PCIE_PRX_SSDTX_N10 17 18
    <11> PCIE_PRX_SSDTX_P10 19 20
    21 19 20 22
    CD45 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_N10_C 23 21 22 24
    <11> PCIE_PTX_SSDRX_N10 23 24
    <11> PCIE_PTX_SSDRX_P10 CD46 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_P10_C 25 26
    27 25 26 28
    27 28
    PCIe SSD <11> PCIE_PRX_SSDTX_N11 29
    31 29 30
    30
    32
    <11> PCIE_PRX_SSDTX_P11 31 32
    33 34
    CD53 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_N11_C 35 33 34 36 @ R1376 2 1 10K_0402_5%~D
    <11> PCIE_PTX_SSDRX_N11 35 36 +3.3VDX_SSD
    CD51 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_P11_C 37 38
    <11> PCIE_PTX_SSDRX_P11 37 38 SSD_DEVSLP <11>
    39 40
    R2663 1 @ 2 0_0402_1% SATA_PRX_SSDTX_P2_C 41 39 40 42
    <11> SATA_PRX_SSDTX_P2 41 42
    R2664 1 @ 2 0_0402_1% SATA_PRX_SSDTX_N2_C 43 44
    <11> SATA_PRX_SSDTX_N2 43 44
    SATA SSD CD47 1 2 0.22U_0402_10V6K SATA_PTX_SSDRX_N2_C
    45
    47 45 46
    46
    48
    <11> SATA_PTX_SSDRX_N2 47 48
    <11> SATA_PTX_SSDRX_P2 CD44 1 2 0.22U_0402_10V6K SATA_PTX_SSDRX_P2_C 49 50
    49 50 PCH_PLTRST#_EC <12,24,28,29,37,39>
    51 52
    51 52 CLKREQ_PCIE#3 <12>
    53 54 SSD_PCIE_WAKE# R1377 1 2 10K_0402_5%~D
    <12> CLK_PCIE_SSD# 53 54 +3.3VDX_SSD
    <12> CLK_PCIE_SSD 55 56
    57 55 56 58
    57 58

    59 60 @ R2662 1 2 0_0402_5%~D
    59 60 SUSCLK <12,29>
    C +3VS R220 1 2 10K_0402_5%~D 61 62 +3.3VDX_SSD C
    +3VS 63 61 62 64
    65 63 64 66
    67 65 66
    67
    1
    @ CS44
    0.1U_0402_10V7K
    2 68 69
    GND GND
    5

    S IC TC7SZ14FU SSOP 5P CONCR_213MAAA32FA


    1 CONN@
    P

    4 NC 2 mCARD_PCIE_SATA#
    <11> SSD_IFDET Y A
    G

    @ U683
    SATA -> GND SATA -> GND
    3

    PCIe -> OC PCIe -> OC

    R2665 1 @ 2 0_0402_1%

    FAN
    B B

    +3VS +5VS
    0.1U_0402_25V6K~D

    2
    10K_0402_5%~D

    10K_0402_5%~D

    10K_0402_5%~D
    2

    C1102
    R884

    R886
    @ R1103

    1
    JFAN1
    6
    1

    5 G2
    4 G1
    3 4
    <37> FAN1_PWM 3
    2 1 2
    <37> FAN1_TACH 1 2
    D81 1
    RB751S40T1G_SOD523-2 ACES_50224-00401-001
    CONN@

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P30-SSD(M.2) / FAN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    C 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 30 of 59
    5 4 3 2 1
    A B C D E

    USB IO Port R03_0429: Change from SGA00004E10 to SGA00004E00


    +5V_USB_P2

    EMI@
    1

    15P_0402_50V8J
    .1U_0402_16V7K~D
    150U_B2_6.3VM_ESR35M
    1 1
    +

    C303

    C265
    +5VALW

    C3
    ML11 EMI@
    4 3 USB20_P2_CONN 2 2 2 +5V_USB_P2
    <11> USB20_P2
    EMI@
    1 1 1
    USB2 CONN

    15P_0402_50V8J
    10U_0603_6.3V6M~D

    .1U_0402_16V7K~D
    1 1
    1 2 USB20_N2_CONN

    C962

    C963
    <11> USB20_N2

    C2
    MCM1012B900F06BP_4P L40 close to JUSB2 JUSB2
    2 2 2 +5VALW +5V_USB_P2 1
    USB20_N2_CONN 2 VBUS
    USB20_P2_CONN 3 D-
    US2 4 D+
    1 8 USB3RN2_RC_CON 5 GND
    2 GND VOUT 7 USB3RP2_RC_CON 6 SSRX- 10
    3 VIN VOUT 6 7 SSRX+ GND 11
    ML12 USB2_EN 4 VIN VOUT 5 USB3TN2_RC_CON 8 GND GND 12
    EN OC USB_OC2# <11> SSTX- GND
    <11> USB3TP2 C623 1 2 0.1U_0402_10V7K USB3TP2_C 4 3 USB3TP2_RC_CON USB3TP2_RC_CON 9 13
    G547I1P81U_MSOP8 SSTX+ GND
    TE_C-PT13-067
    <11> USB3TN2 C621 1 2 0.1U_0402_10V7K USB3TN2_C 1 2 USB3TN2_RC_CON CONN@

    CMMI21T-670Y-N
    EMI@

    EMI@
    USB20_N2_CONN DI1
    USB20_P2_CONN USB3RN2_RC_CON 1 10 USB3RN2_RC_CON

    USB3RP2_RC_CON 2 9 USB3RP2_RC_CON

    3
    ML13 USB3TN2_RC_CON 4 7 USB3TN2_RC_CON
    <11> USB3RN2 1 2 USB3RN2_RC_CON
    DI2 USB3TP2_RC_CON 5 6 USB3TP2_RC_CON
    +3VALW
    4 3 USB3RP2_RC_CON C1289 L30ESDL5V0C3-2_SOT23-3 3
    <11> USB3RP2
    1 2
    CMMI21T-670Y-N EMI@ 8

    5
    EMI@ U699 0.1U_0402_10V7K
    1 TVWDF1004AD0_DFN9

    P
    <10> USB2_PWR_EN

    1
    INB 4 USB2_EN
    2 O
    <38> USB_VBUS_EN_L INA

    G
    2
    Hank0225: Note, PCB footprint is different from 2

    1
    MC74VHC1G32DFT2G_SC70-5~D
    TVWDF1004AD0_DFN9, but it's compatible.

    3
    R1216
    1M_0402_5%~D

    2
    USB3.0 Shielding Clip
    EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P

    H22 H20 H21

    @ @ @

    1
    EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P

    H24 H25

    @ @

    1
    3 3

    4 4

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P31-USB 3.0 IO CONN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 31 of 59
    A B C D E
    A B C D E F G H

    1 1

    Battery Gauge LED


    +5VALW

    2
    +3VALW

    LED13

    LED11

    LED10

    LED14

    LED12
    27-11-T1D-CP1Q1RY-3C_WHITE~D

    27-11-T1D-CP1Q1RY-3C_WHITE~D

    27-11-T1D-CP1Q1RY-3C_WHITE~D

    27-11-T1D-CP1Q1RY-3C_WHITE~D

    27-11-T1D-CP1Q1RY-3C_WHITE~D
    1

    1
    5
    2 2
    QH8A

    G
    <38> BATT_LED#_LV5 4 3 R916 1 2 820_0402_5%~D BAT_LED#_LV5

    D
    DMN66D0LDW-7_SOT363-6

    2
    <38> BATT_LED#_LV4
    QH8B

    G
    1 6 R913 1 2 820_0402_5%~D BAT_LED#_LV4

    D
    <38> BATT_LED#_LV3 DMN66D0LDW-7_SOT363-6

    5
    QH9A

    G
    <38> BATT_LED#_LV2
    4 3 R912 1 2 820_0402_5%~D BAT_LED#_LV3

    D
    DMN66D0LDW-7_SOT363-6
    <38> BATT_LED#_LV1

    2
    QH9B

    G
    1 6 R911 1 2 820_0402_5%~D BAT_LED#_LV2

    D
    DMN66D0LDW-7_SOT363-6
    2
    G

    3 1 R910 1 2 820_0402_5%~D BAT_LED#_LV1


    S

    Q41
    L2N7002WT1G_SC-70-3

    R04_0601: Add MOS to prevent leakage current

    3 3

    Battery Gauge Button


    SW3
    <37> BATBTN# 2 4
    1
    C2983
    0.1U_0402_10V7K
    2 1 3
    TBFD12KQR

    4 4

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P32-BAT LED
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 32 of 59
    A B C D E F G H
    5 4 3 2 1

    Touch Pad, Card Reader Load Switch Touch Screen Load Switch
    +3VALW +3VS_TP +3VS_TP +3VALW
    C1254 R1323 +3VS_TS
    1U_0402_6.3V6K~D U716 0_0603_5%
    2 1 1 14 1 @ 2 1
    2 VIN1 VOUT1 13 C1257 UZ26
    VIN1 VOUT1 1
    2200P_0402_25V7K~D C1159 C1203 2 1 1U_0402_6.3V6K~D 1 +3VS_TS
    TP_PW_EN 3 12 1 2 2 VIN1 R2671 C1208
    <38> TP_PW_EN ON1 CT1 0.1U_0402_10V7K VIN2
    2 0_0603_5% 0.1U_0402_10V7K
    4 11 C1258 7 6 1 @ 2 2
    D +5VALW VBIAS GND VIN thermal VOUT D
    2200P_0402_25V7K~D
    <13> SD_PWR_EN SD_PWR_EN 5 10 1 2 +5VALW 3
    C1256 ON2 CT2 +3VS_CR +3VS_CR VBIAS
    1U_0402_6.3V6K~D 6 9 R1343 3.3V_TS_EN 4 5
    VIN2 VOUT2 <10> 3.3V_TS_EN ON GND
    2 1 7 8 0_0603_5%
    VIN2 VOUT2 1 @ 2 1
    +3VS 15 TPS22961DNYR_WSON8
    GPAD C1264
    R1178 2 1 100K_0402_5%~D SD_PWR_EN AOZ1331_DFN_14P 0.1U_0402_10V7K R1162 2 1 100K_0402_5%~D 3.3V_TS_EN
    R1175 1 2 100K_0402_5%~D TP_PW_EN 2
    @ R1176 2 1 100K_0402_5%~D SD_PWR_EN

    R04_0615: Pull up SD_PWR_EN to meet CR spec

    Deeper Sleep, SSD Load Switch 5V_Run, 5V_Audio Load Switch


    +3VALW +3V_PCH +3V_PCH +5VALW +5VS +5VS
    C1162 R1342 C1201 R2669
    1U_0402_6.3V6K~D U717 0_0805_5% 1U_0402_6.3V6K~D U719 0_0805_5%
    2 1 1 14 1 @ 2 1 2 1 1 14 1 @ 2 1
    2 VIN1 VOUT1 13 C1163 2 VIN1 VOUT1 13 C355
    VIN1 VOUT1 1000P_0402_50V7K~D C1161 VIN1 VOUT1 2200P_0402_25V7K~D C352
    PCH_PWR_EN 3 12 1 2 0.1U_0402_10V7K <34,36,49,52> RUN_ON_P RUN_ON_P 3 12 1 2 0.1U_0402_10V7K
    ON1 CT1 2 ON1 CT1 2
    +5VALW 4 11 C1292 R04_0608: Change enable +5VALW 4 11 C1278
    SSD_PWR_EN 1 2 0_0402_5% VBIAS GND 2200P_0402_25V7K~D VBIAS GND 220P_0402_50V8K
    <13> SSD_PWR_EN pin name
    C @ R1446 5 10 1 2 AUD_PWR_EN 5 10 1 2 C
    RUN_ON_P 1 @ 2 0_0402_1% ON2 CT2 +3.3VDX_SSD +3.3VDX_SSD C1199 ON2 CT2 +5VS_AUDIO +5VS_AUDIO
    R1445 6 9 R1326 1U_0402_6.3V6K~D 6 9 R1320
    2 1 7 VIN2 VOUT2 8 0_0805_5% 2 1 7 VIN2 VOUT2 8 0_0603_5%
    R04_0608: Change enable VIN2 VOUT2 VIN2 VOUT2
    pin name C1158 1U_0402_6.3V6K~D 1 @ 2 1 1 @ 2 1
    15 +3VS 15
    GPAD C1164 GPAD C1200
    R1187 1 2 100K_0402_5%~D PCH_PWR_EN AOZ1331_DFN_14P 0.1U_0402_10V7K R1141 2 1 100K_0402_5%~D AUD_PWR_EN AOZ1331_DFN_14P 0.1U_0402_10V7K
    R1188 1 2 100K_0402_5%~D SSD_PWR_EN 2 @ R290 1 2 100K_0402_5%~D RUN_ON_P 2
    @ R1140 2 1 100K_0402_5%~D AUD_PWR_EN
    <37> PCH_ALW_ON @ R1443 1 2 0_0402_5% PCH_PWR_EN
    <12,36,37,50,51,56> SIO_SLP_SUS# R1444 1 @ 2 0_0402_1%

    WiFi, 3V_RUN Load Switch 3V_Audio, 1.8V_Audio Load Switch


    +3VALW +3VS_NGFF +3VS_NGFF +3VALW +3VS_AUDIO +3VS_AUDIO
    C1166 R1344 C1213 R1318
    1U_0402_6.3V6K~D U720 0_0805_5% 1U_0402_6.3V6K~D U664 0_0603_5%
    2 1 1 14 1 @ 2 1 2 1 1 14 1 @ 2 1
    2 VIN1 VOUT1 13 C1167 2 VIN1 VOUT1 13 C1212
    VIN1 VOUT1 2200P_0402_25V7K~D C1215 VIN1 VOUT1 1000P_0402_50V7K~D C1218
    AUX_EN_WOWL 3 12 1 2 0.1U_0402_10V7K <10> AUD_PWR_EN AUD_PWR_EN 3 12 1 2 0.1U_0402_10V7K
    <29,37> AUX_EN_WOWL ON1 CT1 2 ON1 CT1 2
    +5VALW 4 11 C1293 +5VALW 4 11 C1214
    VBIAS GND 2200P_0402_25V7K~D VBIAS GND 4700P_0402_25V7K
    R04_0608: Change enable RUN_ON_P 5 10 1 2 AUD_PWR_EN 5 10 1 2
    C1160 ON2 CT2 +3VS +3VS ON2 CT2 +1.8VS_AUDIO +1.8VS_AUDIO
    B pin name +1.8VA B
    1U_0402_6.3V6K~D 6 9 R1329 6 9 R1125
    2 1 7 VIN2 VOUT2 8 0_0805_5% C1169 7 VIN2 VOUT2 8 0_0603_5%
    VIN2 VOUT2 1 @ 2 1U_0402_6.3V6K~D VIN2 VOUT2 1 @ 2
    1 1
    15 2 1 15
    GPAD C1216 GPAD C1217
    AOZ1331_DFN_14P 0.1U_0402_10V7K AOZ1331_DFN_14P 0.1U_0402_10V7K
    R1186 1 2 100K_0402_5%~D AUX_EN_WOWL 2 2

    +LCDVDD +LCDVDD
    LCD Load Switch +3VALW
    Camera R1322
    UZ24 0_0805_5% 1
    +3VALW 5 1 1 @ 2
    QZ9 D94 IN OUT C1211
    +3VS DMG2301U-7_SOT23-3 +3VS_CAM +3VS_CAM 2 2 0.1U_0402_10V7K
    1 <37> LCD_VCC_TEST_EN GND
    R2670 2
    0_0603_5% C1168 1 ENVDD 4 3
    EN OC
    S

    3 1 1 @ 2 1 1U_0402_6.3V6K~D
    2 3 SY6288C20AAC_SOT23-5
    <37,7> ENVDD_PCH
    1 C1220
    BAT54CW-7-F_SOT323-3~D
    G

    1U_0402_6.3V6K
    2

    C1204 2
    0.1U_0402_10V7K
    2

    A 3.3V_CAM_EN# A
    3.3V_CAM_EN# <12>
    R1027 1 2 100K_0402_5%~D ENVDD

    +3VS

    3.3V_CAM_EN# R1179 1 @ 2 100K_0402_5%


    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P33-DC/DC Interface 1
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 33 of 59
    5 4 3 2 1
    A B C D E

    +1.0V_VCCST source +1.0V_VCCST


    +1.0V_VCCSTG source
    +1.0VA
    +1.0VA

    0.1U_0402_10V7K
    1
    UZ25
    1

    @ CZ78
    UZ19
    1
    2 VIN1 R1327 1 1
    VIN2 0_0603_5% 2 2 VIN1 R1325
    7 6 1 @ 2 VIN2 0_0603_5%
    1 VIN thermal VOUT +1.0V_VCCST +5VALW
    1U_0402_6.3V6K

    7 6 1 @ 2 +1.0V_VCCSTG
    VIN thermal VOUT
    CZ92

    +5VALW 3
    VBIAS 3
    2 4 5 VBIAS
    <36> VCCST_EN ON GND 1

    1U_0402_6.3V6K

    0.1U_0402_10V7K
    1 4 5
    ON GND +1.0V_VCCSTG

    CZ87

    CZ86 @
    TPS22961DNYR_WSON8
    2 TPS22961DNYR_WSON8
    2

    0.1U_0402_10V7K
    BEAVER CREEK: 1
    4.4mohm/6A BEAVER CREEK:

    @ CZ82
    TR=12.5us@Vin=1.05V 4.4mohm/6A
    2
    TR=12.5us@Vin=1.05V

    VCCSTG_EN

    +3VALW

    +VCCPLL_OC source

    5
    1

    P
    +VCCPLL_OC <12,28,56> SIO_SLP_S0# B 4 VCCSTG_EN VCCSTG_EN <56>
    2 O
    <33,36,49,52> RUN_ON_P A

    G
    +1.2V_DDR UC9

    1
    TC7SH08FU_SSOP5~D

    0.1U_0402_10V7K
    2 1 2

    100K_0402_5%
    RZ75
    UZ22
    1

    CZ83
    2 VIN1 R1333
    VIN2 0_0603_5% 2

    2
    1 7 6 1 @ 2 +VCCPLL_OC
    VIN thermal VOUT
    1U_0402_6.3V6K
    CZ89

    3
    +5VALW VBIAS S0 S0Ix S3
    2 4 5
    ON GND

    RZ76 TPS22961DNYR_WSON8
    SIO_SLP_S0# high low low
    VCCSTG_EN 1 @ 2

    0_0402_1%
    RUN_ON_EC high high low

    +1.0V_MPHYGT source TBT Power circuits


    +5VALW +1.0V_MPHYGT +3VALW +3V_TBT_PWR +3V_TBT
    3 +1.0VA 3
    UZ23
    R1335 1
    0.1U_0402_10V7K

    0.1U_0402_10V7K

    1 1 VIN1
    0_0603_5% 2
    1 2 VIN2
    @ CZ88

    @ CZ85

    @ +1.0V_MPHYGT
    7 6 1 2
    2 2 VIN thermal VOUT
    1
    0.01_0603_1%

    10U_0402_6.3V6M
    CZ91
    3
    1U_0402_6.3V6K

    1 +5VALW VBIAS 1
    CZ84

    @ RT114

    0.1U_0402_10V7K
    CZ90
    <36,49,51,52> SUS_ON_P
    4 5
    2 ON GND
    2 R04_0608: Change enable 2
    2 1 pin name TPS22961DNYR_WSON8
    MPHYP_PWR_EN <12>
    @ RH557 100K_0402_5%~D

    4 4

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P34-DC/DC Interface 2
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 34 of 59
    A B C D E
    A B C D E

    FD1
    @ FIDUCAL
    FD2
    @ FIDUCIAL
    FD3
    @ FIDUCAL
    FD4
    @ FIDUCIAL Keyboard Controller board + DMIC
    1

    1
    JKB1
    +5VALW 1
    H1 H3 H4 2 1
    +5VS
    +3VALW 3 2 Place close to JKB1
    1
    H_2P0 H_1P8N H_2P0 4 3 1
    +3VS 4 +3VALW +5VALW +3VS
    @ @ @ 5
    1

    1
    <10> KB_DET# 6 5
    <37> BC_INT#_ECE1117 6
    <37> BC_DAT_ECE1117 7
    8 7
    <37> BC_CLK_ECE1117 8
    H6 H7 H9 H10 White <37> BAT2_LED# 9
    9 1 1 1
    Amber <37> BAT1_LED#
    10
    11 10 C375 C376 C377
    <26> DMIC_DAT_CODEC 12 11
    H_3P3 H_2P0 H_2P0 H_3P3 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D
    <26> DMIC_CLK_CODEC 12 2 2 2
    @ @ @ @ 13
    1

    1
    14 13
    15 14
    15 16
    GND 17
    H11 H12 H13 H14 H15 GND
    E-T_6710K-Y15M-31L
    H_3P3 H_2P0 H_2P0 H_3P3 H_3P3 CONN@
    @ @ @ @ @
    1

    H16 H17 H18 H19 H23 H26

    H_3P3 H_3P3 H_2P0 H_2P0


    @ @ @ @
    1

    1
    @ @
    H_2P3X1P8N H_3P2X0P8

    R06_0822: Stand off screw hole change form 3.2mm to 3.3 mm.
    R06_0826: Add H26 for SSD bracket.

    2 2

    3 3

    RTC Battery With Charge Function

    RTC Battery Conn


    +RTCBATT
    +RTCBATT
    Intel recommend for EMI

    B+ B+ B+
    2

    1 EMI@ 1 EMI@ 1 EMI@


    RTCR1 1
    0.1U_0402_16V4Z

    JRTC1 C1273 C1274 C1275


    C2973

    1.3K_0402_5%~D
    1 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D
    +3VLP 20mil 2 1 2 2 2
    1

    2 2
    W=20mils
    1

    3
    G1
    D122 4
    G2 Place at trace Source, Middle and Ended point.
    BAS40-04_SOT23-3
    CONN@
    ACES_50278-00201-001
    4 4
    2

    W=20mils W=20mils

    +RTCVCC
    1 1
    CH95 EMI@
    1U_0402_6.3V6K~D C1309 DELL CONFIDENTIAL/PROPRIETARY
    2 2
    15P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
    RF Reserved. Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P35-SCREWH/KB/RTC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 35 of 59
    A B C D E
    5 4 3 2 1

    +3VALW

    5
    U729
    1 +3VALW

    G VCC
    <12,37,39> SIO_SLP_S3# B 4
    Y H_VCCST_PWRGD_P <12,15>
    2
    <37> H_VCCST_PWRGD A

    5
    3
    MC74VHC1G09DFT2G_SC70-5 SIO_SLP_S3# 1

    P
    D B D
    4
    O RUN_ON_P <33,34,49,52>
    2
    <37> RUN_ON_EC A

    G
    UC10

    1
    3
    2 1 TC7SH08FU_SSOP5~D RE99
    @ RE94 0_0402_5%~D 100K_0402_5%

    2
    R04_0604: Add VCCST enable condition for deep S3 power state & sequence 2 1
    @ RE98 0_0402_5%~D

    +3VALW

    5
    1

    P
    <12,33,37,50,51,56> SIO_SLP_SUS# B 4
    O VCCST_EN <34>
    2
    A

    G
    UC13

    1
    3
    TC7SH08FU_SSOP5~D RE103
    100K_0402_5%

    2
    +3VALW
    +3VALW

    5
    5

    SIO_SLP_S3# 1

    P
    1 B 4
    P

    <12,37> SIO_SLP_S4# B O IMVP_VR_ON_P <53,57>


    4 2
    O SUS_ON_P <34,49,51,52> <37> IMVP_VR_ON A

    G
    2 UC11
    <37> SUS_ON_EC A
    G

    1
    UC8

    3
    1

    C TC7SH08FU_SSOP5~D RE101 C
    3

    TC7SH08FU_SSOP5~D RE97 100K_0402_5%


    100K_0402_5%

    2
    2 1
    2

    2 1 @ RE100 0_0402_5%~D
    @ RE95 0_0402_5%~D

    +3VS_TP +3VS_TP
    +1.8VA Discharge
    Touchpad CONN +3VS_TP
    R04_0612: Add +1.8VA discharge circuit

    2
    +3VS_TP R1104 1 2 4.7K_0402_5%
    for rail to rail sequence
    C7
    C1225

    EMI@ QH7B

    G
    15P_0402_50V8J
    1U_0402_6.3V6K~D

    1 1
    6 1 I2C1_SDA
    B <10> I2C1_SDA_TP +1.8VA
    B

    S
    DMN66D0LDW-7_SOT363-6

    JTP1 2 2
    1 1 2
    1

    5
    I2C1_SDA 2 @ RH461 0_0402_5%~D R1105 1 2 4.7K_0402_5%
    2

    1
    I2C1_SCK 3 QH7A

    G
    4 3 3 4 I2C1_SCK R79
    4 <10> I2C1_SCK_TP B+

    S
    PTP_INT#_R 5 DMN66D0LDW-7_SOT363-6 80.6_0402_1%~D
    6 5
    <38> PTP_DIS# 7 6
    <37> DAT_TP_SIO

    2
    7

    1
    <37> CLK_TP_SIO
    8 1 2
    8 @ RH456 0_0402_5%~D R78
    9 200K_0402_1%
    GND1

    3
    DMN66D0LDW-7_SOT363-6
    10
    GND2

    2
    3

    QE13B
    ACES_50506-00841-P01
    @ MD9 @ MD10 CONN@ DAT_TP_SIO 5
    PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3
    CLK_TP_SIO

    4
    6
    DMN66D0LDW-7_SOT363-6
    680P_0402_50V7K~D
    @ C1229

    680P_0402_50V7K~D
    @ C1226

    1 1
    1

    QE13A
    SIO_SLP_SUS# 2
    2 2

    1
    +3VS_TP
    +3VS_TP
    1

    R1299
    100K_0402_5%~D
    2
    G

    <13,37> PTP_INT#_EC
    1 3 PTP_INT#_R
    D

    A A
    Q40
    L2N7002WT1G_SC-70-3

    R04_0514: Change SB00000UO00


    to SB00000ST00 for completely replace

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P36-TP/PWERGD/LID
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 36 of 59
    5 4 3 2 1
    5 4 3 2 1

    +RTCVCC
    +3VALW_5085
    RE32 1 @ 2 0_0402_1% +RTC_CELL_VBAT

    0.1U_0402_25V6
    +RTCVCC

    1
    RPE5

    CE65
    BC_DAT_ECE1117 1 8
    PTP_INT#_EC 2 7

    2
    VCI_IN3# 3 6
    +3VALW_5085 BATBTN# 4 5

    100K_0804_8P4R_5%

    0.1U_0402_25V6

    1U_0402_6.3V6K
    +3VALW_5085
    +3VALW_5085

    1
    CE63

    CE14
    RE52 1 2 2.2K_0402_5% PBAT_SMBDAT UPD_SMBDAT RE87 1 2 2.2K_0402_5%
    RE53 1 2 2.2K_0402_5% PBAT_SMBCLK +3VALW_5085 UPD_SMBCLK RE88 1 2 2.2K_0402_5%

    2
    RE3 1 2 10K_0402_5% UPD_SMBINT# PCIE_WAKE# RE86 1 2 10K_0402_5%
    USBC_MCP23017_SMBDAT RE71 1 2 2.2K_0402_5%
    RE102 1 2 100K_0402_5% ACAV_IN_NB USBC_MCP23017_SMBCLK RE73 1 2 2.2K_0402_5%
    CHARGER_SMBDAT RE55 1 2 8.2K_0402_5%
    CHARGER_SMBCLK RE56 1 2 8.2K_0402_5%

    1U_0402_6.3V6K
    THERMATRIP3# RE67 1 2 10K_0402_5%

    0.1U_0402_25V6
    1

    1
    H_VCCST_PWRGD RE93 1 2 10K_0402_5%

    CE64

    CE17
    D UE5 D

    2
    +3VS_TP B64 A10 T183 PAD~D @
    VBAT GPIO021/RC_ID1 B10 BOARD_ID MSDATA @ RE85 1 2 10K_0402_5%
    RE6 1 2 4.7K_0402_5%~D CLK_TP_SIO GPIO020/RC_ID2 B8 PCIE_WAKE# SUS_ON_EC RE68 1 2 100K_0402_5%
    +3VALW +3VALW_5085 GPIO014/GPTP-IN7/RC_ID3 PCIE_WAKE# <29>
    RE7 1 2 4.7K_0402_5%~D DAT_TP_SIO A22 B27
    H_VTR GPIO025/UART_CLK LAN_WAKE# <12>
    B44 HOST_DEBUG_TX UPD_MRESET RE90 1 2 100K_0402_5%
    PJP15 GPIO120/UART_TX/V2P_COUT_HI1 B46
    GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1 PCH_PCIE_WAKE# <12>
    1 2 A58 B26 RUNPWROK
    RE54 1 @ 2 10K_0402_5% PCH_PLTRST#_EC VTR_ADC VCC_PWRGD A25
    GPIO060/KBRST/BCM_B_INT# EN_INVPWR <25>

    10U_0603_6.3V6M

    0.1U_0402_25V6
    RE58 1 2 100K_0402_5% LCD_TST PAD-OPEN1x1m B36 SIO_SLP_S4#

    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6

    0.1U_0402_25V6
    GPIO101/ECGP_SCLK SIO_SLP_S4# <12,36>
    RE2 1 2 10K_0402_5% RESET_OUT# @ B3 B37 PTP_INT#_EC PTP_INT#_EC <13,36>
    VTR GPIO103/ECGP_MISO

    1
    A11 B38
    VTR GPIO105/ECGP_MOSI AUX_EN_WOWL <29,33>

    CE46
    CE42

    CE43

    CE38

    CE41

    CE44

    CE40
    A26 A34
    VTR GPIO102/BCM_C_INT# PCH_ALW_ON <33>
    B35 A35 SIO_SLP_S3# PCH_DPWROK 0_0402_1% 2 @ 1 RC221
    SIO_SLP_S3# <12,36,39> PCH_DPWROK_R <12>

    2
    A41 VTR GPIO104/SLP_S0# A36 PCH_DPWROK
    VTR GPIO106
    A52
    VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP
    A40 BAT1_LED# BAT1_LED# <35> Amber
    GPIO117/MSCLK/V2P_COUT_HI
    B43
    A45
    BAT2_LED# BAT2_LED# <35> White BAT1_LED# 0_0402_1% 2 @ 1 RE104 MSDATA
    GPIO127/A20M PCH_RSMRST# <12,15>
    B65 FWP#
    A5 nFWP BAT2_LED# 0_0402_1% 2 @ 1 RE105 MSCLK
    <9> SML1_SMBDAT GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
    B6
    Connect PCH <9> SML1_SMBCLK
    CLK_TP_SIO A37 GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0 B57
    <36> CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED1/GANG_DATA1 PWRBTN_LED# <24>
    DAT_TP_SIO B40 B1
    +RTCVCC
    Connect Touch Pad <36> DAT_TP_SIO
    LCD_TST A38 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED0 A55
    ME_FWP_EC <13>
    T185 PAD~D @
    <25> LCD_TST GPIO112/PS2_CLK1A GPIO153/LED2/GANG_DATA4
    PAD~D @ T188 B41 A1 SIO_SLP_S3# 2 @ 1 RUN_ON_EC
    GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 IMVP_VR_ON <36> RUN_ON_EC <36>
    R04_0624: Remove RE35 for dino2 PD FW A39 B28 0_0402_5%~D R249
    <33> LCD_VCC_TEST_EN GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 SIO_SLP_A# <12>
    1
    100K_0402_5%

    B42 B2 R07_0730: Change net name


    <44> PWR_SRC_ON GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1/32KHZ_OUT VBUS_HV_DIS# <44>
    RE31

    PBAT_SMBDAT B59 A8 RUN_ON 2 @ 1


    <45> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK <12>
    2 1 PBAT_SMBCLK A56 B9 RUN_ON 0_0402_1% R250
    <41> PWR_TB_DOCK#
    10K_0402_5% @RE35
    @RE35
    Connect Battery <45> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6 GPIO016/GPTP-IN8 A9 CV2_ON
    JTAG_TDI A51 GPIO017/GPTP-OUT8 B39 RESET_OUT# RESET_OUT# <12,15>
    2

    JTAG_TDO B55 GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT A44 H_VCCST_PWRGD


    GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY H_VCCST_PWRGD <36>
    2 1 POWER_SW_IN# JTAG_CLK B56
    <12,24> PBTN_SW# A53 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK A54 2 1
    1K_0402_5% RE33 JTAG_TMS AC_PRESENT <12> SIO_SLP_S4# @ SUS_ON_EC <36>
    GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4/GANG_DATA2
    1U_0402_6.3V6K

    JTAG_RST# B47 B58 0_0402_5%~D R252 SUS_ON_EC


    JTAG_RST# GPIO152/GPTP-OUT4 SIO_PWRBTN# <12,15>
    1

    CE49

    CE21 B22 A3 USBC_MCP23017_SMBDAT CV2_ON 2 @ 1


    <30> FAN1_TACH GPIO050/FAN_TACH1/GTACH0/GANG_START GPIO003/I2C1A_DATA USBC_MCP23017_SMBDAT <25,38,41>MCP23017
    1U_0402_6.3V6K LID_CL_SIO# A21 B4 USBC_MCP23017_SMBCLK 0_0402_1% R251
    USBC_MCP23017_SMBCLK <25,38,41>
    2

    PAD~D @ T187 B23 GPIO051/FAN_TACH2/GANG _MODE GPIO004/I2C1A_CLK A4


    @ GPIO052/FAN_TACH3/GTACH1/GANG_ERROR GPIO005/I2C1B_DATA/BCM_B_DAT UPD_MRESET <39,41>
    B24 B5
    <45> PS_ID GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK SIO_EXT_WAKE# <10>
    PAD~D @ T184 A23 B7
    B25 GPIO054/PWM1/GPWM1 GPIO012/I2C1H_DATA/I2C2D_DATA A7 SUSACK# <12> UPD_EN1_4# 0_0402_1% 2 @ 1 RE107 T197 PAD~D @
    <25> BIA_PWM_EC GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3 ENVDD_PCH <33,7>
    A24 B48 UPD_SMBDAT
    <30> FAN1_PWM GPIO056/PWM3/GPWM0 GPIO130/I2C2A_DATA/BCM_C_DAT B49 UPD_SMBCLK
    UPD_SMBDAT <41> UPD
    GPIO131/I2C2A_CLK/BCM_C_CLK UPD_SMBCLK <41>
    +3VALW_5085 A47 CHARGER_SMBDAT Charger
    GPIO132/I2C1G_DATA CHARGER_SMBDAT <46>
    B50 CHARGER_SMBCLK SIO_SLP_SUS#_R 43K_0603_1% 2 1 RC97
    GPIO140/I2C1G_CLK CHARGER_SMBCLK <46> SIO_SLP_SUS# <12,33,36,50,51,56>
    A43 B52 SIO_SLP_SUS#_R
    <13> EC_SLP_S0IX# B45 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA A49
    DE11 <12> SIO_SLP_WLAN# GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK PBAT_PRES# <45,46>
    1
    100K_0402_5%

    UPD_SMBINT# A42 B53 UPD_EN1_4#


    1 2 <41> UPD_SMBINT# B20 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA A50 2 1 RE120
    <44> DCIN_ACOK ACAV_IN_NB ACAV_IN_NB AC_DIS <44,46> PCIE_WAKE# 0_0402_1% @ TBT_PCIE_WAKE# <39>
    GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK
    RE25

    A18
    C
    <12> SIO_SLP_S5# GPIO031/GPTP-OUT2/BCM_E_DAT C
    B19 A59 1 2
    RB751S40T1G_SOD523-2 <26> BEEP GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7 SYSPWR_PRES +3VLP
    A20 RE57 1K_0402_5%
    <35> BC_CLK_ECE1117
    2

    GPIO047/LSBCM_D_CLK

    1
    100K_0402_5%
    BC_DAT_ECE1117 B21 B62 T189 PAD~D @
    <35> BC_DAT_ECE1117 GPIO046/LSBCM_D_DAT/GANG_STROBE BGP0
    A19 A64
    <35> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OVRD_IN ACAV_IN <46>

    RE63
    1 2 LID_CL_SIO# A60
    <24> LID_SW_IN# VCI_OUT ALWON <48>
    0.047U_0402_16V4Z

    10_0402_5% RE26 A6 B67 POWER_SW_IN#


    <13> SIO_EXT_SMI# GPIO011/nSMI VCI_IN0#
    A27 A63 BATBTN#
    <9> SIO_RCIN# BATBTN# <32>

    2
    GPIO061/LPCPD# VCI_IN1#
    1

    A28 B63 USB_PWR_SHR_DET_R#


    <9> IRQ_SERIRQ SER_IRQ VCI_IN2#
    CE13

    PCH_PLTRST#_EC B30 B68 VCI_IN3#


    <12,24,28,29,30,39> PCH_PLTRST#_EC LRESET# VCI_IN3#
    CLK_PCI_MEC A29
    <9> CLK_PCI_MEC
    2

    LPC_FRAME# B31 PCI_CLK B51


    <9> LPC_FRAME# LFRAME# VREF_PECI +1.0VS_VCCIO
    LPC_AD0 A30 A48 PECI_EC_R 1 2
    <9> LPC_AD0 LAD0 PECI_DAT PECI_EC <13>

    0.1U_0402_25V6
    LPC_AD1 B32 RE61 43_0402_5%
    <9> LPC_AD1 LAD1
    LPC_AD2 A31 B13 REM_DIODE1_N CE58 1 2 2200P_0402_50V7K
    <9> LPC_AD2 LAD2 DN1_DP1A/THERM

    CE50
    LPC_AD3 B33 A13 REM_DIODE1_P
    <9> LPC_AD3 LAD3 DP1_DN1A/VREF_T
    A32 B14 REM_DIODE2_N CE67 1 2 2200P_0402_50V7K
    <9> CLKRUN# CLKRUN# DN2_DP2A
    +RTCVCC A33 A14 REM_DIODE2_P
    <10> SIO_EXT_SCI#

    2
    GPIO100/NEC_SCI DP2_DN2A A15 REM_DIODE3_N CE39 1 2 2200P_0402_50V7K
    MEC_XTAL1 A61 DN3_DP3A B16 REM_DIODE3_P
    XTAL1 DP3_DN3A
    1
    100K_0402_5%

    MEC_XTAL2 2 @ 1 MEC_XTAL2_R A62 A16 REM_DIODE4_N CE60 1 2 2200P_0402_50V7K


    +3VS XTAL2 DN4_DP4A
    RE36

    RE62 0_0402_1% B17 REM_DIODE4_P


    DP4_DN4A B15
    VIN CE58, CE39, CE60, Place near UE5
    10K_0402_5%

    A17 VSET_5085
    VSET
    1

    A12 PECI_EC_R
    I_ADP <46>
    2

    VCP
    RE83

    B34 THERMATRIP2# @
    +3VALW THERMTRIP2#

    47P_0402_50V8J~D
    CE68
    2 1 USB_PWR_SHR_DET_R# A2 THERMATRIP3# 1
    <24> USB1_DET# GPIO002/THERMTRIP3# B29
    10K_0402_5% RE34 THSEL_STRAP

    VSS_ADC
    GPIO024/THSEL_STRAP

    VSS_RO
    VR_CAP
    1U_0402_6.3V6K

    A46 H_PROCHOT#_EC RE96 1 2 100_0402_5%

    H_VSS
    H_PROCHOT# <13,46,47,53>
    2

    PROCHOT_IN#/PROCHOT_IO#
    1

    AGND
    100K_0402_5%

    B61 RE64 1 2 4.7K_0402_5%


    I_BATT <46>

    VSS
    V_ISYS0 2
    1
    CE56

    CE22 RUNPWROK A57

    EP
    V_ISYS1 P_SYS <46,53>
    RE84

    1U_0402_6.3V6K
    2

    @ MEC5085-LZY

    B66

    B11

    B60

    +VR_CAP B12

    B54

    B18

    C1
    3
    DMN66D0LDW-7_SOT363-6
    2

    QE12B

    15mil
    RUN_ON# 5
    6
    DMN66D0LDW-7_SOT363-6

    4.7U_0603_6.3V6K
    4

    1
    QE12A

    CE45
    RUN_ON_EC 2

    Setting for Thermal Design

    2
    1

    ESR <2ohms
    Thermal diode mapping
    5085 Channel Location
    VSET_5085
    32 KHz Clock DP1/DN1 CPU(OTP)

    0.1U_0402_25V6

    1.5K_0402_1%
    B B

    1
    MEC_XTAL1 1 2 MEC_XTAL2 THSEL_STRAP 1 2

    RE77
    +3VALW_5085 RE78 1K_0402_5%
    DP2/DN2 BOT Skin2

    22P_0402_50V8J

    22P_0402_50V8J

    CE55
    YE1
    1 32.768KHZ 9PF 20PPM 9H03200033 1

    2
    1
    100K_0402_5%
    DN2A/DP2A BOT Skin1

    2
    CE62

    CE53
    RE65
    2 2 1: Channel 1 will provide Thermistor Readings
    DP3/DN3 DRAM
    0: Channel 1 will provide Diode Readings
    2

    R04_0609: Fine tune cap by vendor suggestion


    JTAG_RST# DP4/DN4 FAN Rest=1.5K , Tp=88 degree
    1

    CLK_PCI_MEC

    JDEG +3.3V_ALW_DEG +3VALW_5085


    1U_0402_6.3V6K

    EMI@
    REM_DIODE1_P
    1

    1
    @SHORT PADS~D
    JTAG1 CONN@

    100_0402_1%

    10_0402_5%
    RE76 REM_DIODE2_P
    1

    @ RE66

    100P_0402_50V8J
    2 1

    1
    METR3904W-G_SC70-3
    CE59

    C
    E QE11

    1
    RE80

    100P_0402_50V8J

    100P_0402_50V8J

    @ CE47
    49.9_0402_1% C 2
    2

    B
    8
    7
    6
    5

    1
    +3VALW_5085
    10K_8P4R_5%

    @ CE57

    @ CE48
    2 2 B
    2

    1
    4.7P_0402_50V8C
    EMI@
    B E QE3

    3
    C
    RPE7

    E QE4 METR3904W-G_SC70-3

    3
    METR3904W-G_SC70-3 REM_DIODE1_N
    2
    1

    1
    10K_0402_5%

    10K_0402_5%

    100K_0402_5%

    REM_DIODE2_N
    1
    2
    3
    4

    @ RE72

    @ RE75

    CE52
    JDEG1 Place QE11 close to BOT Skin1 location Place QE4 close to BOT Skin2 Place QE3 close to CPU
    RE74

    2
    1 2 JTAG_TDI CE57 should close to QE11 CE48 should close to QE4 CE47 should close to QE3
    2 3 JTAG_TMS EMI depop location
    2

    3 4 JTAG_CLK
    4 5 JTAG_TDO REM_DIODE3_P
    11 5 6 MSCLK
    Place close pin A29
    12 G1 6 7 MSDATA
    G2 7 8 HOST_DEBUG_TX +3VALW_5085
    8

    1
    QE10

    100P_0402_50V8J
    9 R07_0723: Change board ID on A00 R1.0 MB C
    9 UART0_TX <10>

    1
    @ CE66
    10 2
    10

    8.2K_0402_5%
    Pin8 5085_TXD for EC Debug B

    1
    HB_A531015-SCHR21 pin9 5048_TXD for SBIOS +3VALW_5085 +3VALW_5085 E
    RE79 CE54 REV

    3
    METR3904W-G_SC70-3

    RE69
    CONN@ debug
    REM_DIODE3_N

    240K 4700p X00


    2

    Place QE10 close to DRAM

    2
    RE79 RE81

    +3VS
    130K 4700p X01 4.3K_0402_5% 10K_0402_5% CE66 should close to QE10
    THERMATRIP2#
    JLPDE1 62K 4700p X02
    1

    +1.0VS_VCCIO

    MMST3904-7-F_SOT323-3
    1 REM_DIODE4_P
    1 33K 4700p X03

    0.1U_0402_25V6
    2 BOARD_ID FWP#
    2

    1
    100P_0402_50V8J
    3 LPC_AD0 C
    3
    4
    4 LPC_AD1 8.2K 4700p X04 1 2 2
    2

    1
    @CE51

    QE9

    CE61
    5 LPC_AD2 C RE70 2.2K_0402_5% B
    5 4.3K 4700p A00
    1

    A 11 6 LPC_AD3 CE54 2 E A

    3
    12 G1 6 7 LPC_FRAME# 4700P_0402_25V7K RE82 B
    2K 4700p

    2
    G2 7 8 PCH_PLTRST#_EC 10K_0402_5% E QE8
    2

    3
    8 9 METR3904W-G_SC70-3
    1K 4700p
    1

    9 10
    10 CLK_LPC_DEBUG <9>
    REM_DIODE4_N <13> H_THERMTRIP#
    HB_A531015-SCHR21
    CONN@ Place QE8 close to FAN location
    BOARD_ID rise time is measured from 5%~68%.
    CE51 should close to QE8

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P37-EC ENE-KB9012
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 37 of 59
    5 4 3 2 1
    5 4 3 2 1

    D D

    +3VALW +3VALW_23017

    PJP14
    1 2
    +3VALW_23017

    10U_0603_6.3V6M

    0.1U_0402_25V6

    0.1U_0402_25V6
    PAD-OPEN1x1m

    1
    @

    1
    CE4

    CE3

    CE10
    RE14 1 2 100K_0402_5% WLAN_WIGIG60GHZ_DIS#

    2
    RE13 1 2 100K_0402_5% BT_RADIO_DIS#

    2
    5
    UE4

    VDD
    C C
    4 17 USB_VBUS_EN_L USB_VBUS_EN_L RE59 1 2 10K_0402_5%
    <25> PANEL_BKEN_EC 3 GPB7 GPA0 18 USB_PWR_SHR_VBUS_EN_R USB_VBUS_EN_L <31> USB_PWR_SHR_VBUS_EN_R RE89 1 2 10K_0402_5%
    2 GPB6 GPA1 19 USB_PWR_SHR_VBUS_EN_R <24>
    <25> DBC_I2C_EN 1 GPB5 GPA2 20 USB_PWR_SHR_EN_R# <24>
    <32> BATT_LED#_LV5 GPB4 GPA3 NB_MUTE# <26,27>
    <32> BATT_LED#_LV4 28 21 PTP_DIS# <36>
    27 GPB3 GPA4 22 WLAN_WIGIG60GHZ_DIS#
    <32> BATT_LED#_LV3 GPB2 GPA5 WLAN_WIGIG60GHZ_DIS# <29>
    <32> BATT_LED#_LV2 26 23 BT_RADIO_DIS#
    GPB1 GPA6 BT_RADIO_DIS# <29>
    <32> BATT_LED#_LV1 25 24 TP_PW_EN <33>
    GPB0 GPA7

    <25,37,41> USBC_MCP23017_SMBDAT 9
    8 SDA
    <25,37,41> USBC_MCP23017_SMBCLK SCL
    16
    15 INTA
    INTB
    Device Address: RE27 1 2 10K_0402_5% 11 10
    +3VALW_23017
    b 0,1,0,0,A2,A1,A0,0 RE23 1 2 10K_0402_5% 12 A0
    A1
    NC/SO
    NC
    7
    RE22 1 2 10K_0402_5% 13
    0x42 A2
    14 6
    RESET VSS(Ground)
    +3VALW_23017 RE24 1 2 10K_0402_5%
    MCP23017T-E-ML_QFN28_6X6
    Ensure rise time within 66ms.
    (fast than 0.05V/ms)

    B B

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P38-MCP23017
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 38 of 59
    5 4 3 2 1
    5 4 3 2 1

    CPU PCIE TX

    CPU PCIE RX
    CT2 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_P1_C Y23 V23 PCIE_PRX_TBTX_P1_C CT1 2 1 0.22U_0201_6.3V6M
    +3VA_TBT_LC <11> PCIE_PTX_TBRX_P1 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_TBTX_P1 <11>
    CT4 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_N1_C Y22 V22 PCIE_PRX_TBTX_N1_C CT3 2 1 0.22U_0201_6.3V6M
    <11> PCIE_PTX_TBRX_N1 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_TBTX_N1 <11>
    CT6 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_P2_C T23 P23 PCIE_PRX_TBTX_P2_C CT5 2 1 0.22U_0201_6.3V6M
    <11> PCIE_PTX_TBRX_P2 PCIE_RX1_P PCIE_TX1_P PCIE_PRX_TBTX_P2 <11>

    PCIe GEN3
    <11> PCIE_PTX_TBRX_N2 CT8 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_N2_C T22 P22 PCIE_PRX_TBTX_N2_C CT7 2 1 0.22U_0201_6.3V6M PCIE_PRX_TBTX_N2 <11>
    PCIE_RX1_N PCIE_TX1_N
    1

    1
    10K_0201_5%

    10K_0201_5%

    10K_0201_5%

    10K_0201_5%
    RT6

    RT7

    RT8

    RT9
    M23 K23
    M22 PCIE_RX2_P PCIE_TX2_P K22
    PCIE_RX2_N PCIE_TX2_N
    JAR1 H23 F23
    2

    2
    TBT_JTAG_TDI 1 H22 PCIE_RX3_P PCIE_TX3_P F22
    TBT_JTAG_TMS 2 1 PCIE_RX3_N PCIE_TX3_N
    TBT_JTAG_TCK 3 2 V19 L4 TBT_PERST_N R104 2 @ 1 0_0402_1%
    3 <12> CLK0_PCIE_TBT PCIE_REFCLK_100_IN_P PERST_N PCH_PLTRST#_EC <12,24,28,29,30,37>
    TBT_JTAG_TDO 4 T19
    4 <12> CLK0_PCIE_TBT# PCIE_REFCLK_100_IN_N
    5 <12> CLKREQ_PCIE#0 AC5 N16 PCIe_RBIAS RT1 2 1 3.01K_0402_1%
    D
    6 G1 PCIE_CLKREQ_N PCIE_RBIAS D
    G2 CT17 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_P0_C AB7 R2
    <7> DDI1_PTX_TBRX_P0 DPSNK0_ML0_P DPSRC_ML0_P
    ACES_50224-00401-001 <7> DDI1_PTX_TBRX_N0 CT18 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_N0_C AC7 R1
    DPSNK0_ML0_N DPSRC_ML0_N
    CONN@
    <7> DDI1_PTX_TBRX_P1 CT19 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_P1_C AB9 N2
    CT20 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_N1_C AC9 DPSNK0_ML1_P DPSRC_ML1_P N1
    <7> DDI1_PTX_TBRX_N1 DPSNK0_ML1_N DPSRC_ML1_N

    SOURCE PORT 0
    SINK PORT 0
    <7> DDI1_PTX_TBRX_P2 CT21 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_P2_C AB11 L2

    CPU DDI1
    CT22 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_N2_C AC11 DPSNK0_ML2_P DPSRC_ML2_P L1
    <7> DDI1_PTX_TBRX_N2 DPSNK0_ML2_N DPSRC_ML2_N

    <7> DDI1_PTX_TBRX_P3 CT23 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_P3_C AB13 J2


    CT24 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_N3_C AC13 DPSNK0_ML3_P DPSRC_ML3_P J1
    <7> DDI1_PTX_TBRX_N3 DPSNK0_ML3_N DPSRC_ML3_N
    CT25 2 1 0.1U_0201_6.3V6K CPU_DDI1_AUXP_C Y11 W19
    <7> CPU_DDI1_AUXP DPSNK0_AUX_P DPSRC_AUX_P
    CT26 2 1 0.1U_0201_6.3V6K CPU_DDI1_AUXN_C W11 Y19
    <7> CPU_DDI1_AUXN DPSNK0_AUX_N DPSRC_AUX_N
    AA2 G1 TBT_SRC_HPD
    <7> CPU_DP1_HPD DPSNK0_HPD DPSRC_HPD TBT_RESET_N_R @ RT120 2 1 0_0201_5% TBT_RESET_N <41>
    Y5 N6 DPSRC_RBIAS RT2 2 1 14K_0402_1%
    <7> CPU_DP1_CTRL_CLK DPSNK0_DDC_CLK DPSRC_RBIAS
    <7> CPU_DP1_CTRL_DATA R4
    DPSNK0_DDC_DATA U1 TBT_I2C_DATA RT121 2 1 0_0201_5%
    GPIO_0 TBT_I2C_DATA <41> UPD_MRESET <37,41>
    <7> DDI2_PTX_TBRX_P0 CT29 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_P0_C AB15 U2 TBT_I2C_CLK TBT_I2C_CLK <41>
    CT30 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_N0_C AC15 DPSNK1_ML0_P GPIO_1 V1 TBT_ROM_WP#
    <7> DDI2_PTX_TBRX_N0

    LC GPIO
    +3V_TBT DPSNK1_ML0_N GPIO_2 V2 TBT_TMU_CLK_OUT
    CT31 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_P1_C AB17 GPIO_3 W1 TBT_PCIE_WAKE#
    <7> DDI2_PTX_TBRX_P1 DPSNK1_ML1_P GPIO_4 TBT_PCIE_WAKE# <37>
    <7> DDI2_PTX_TBRX_N1 CT32 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_N1_C AC17 W2 TBT_CIO_PLUG_EVENT# TBT_CIO_PLUG_EVENT# <13>
    DPSNK1_ML1_N GPIO_5 Y1 TBT_DDC_DATA
    RT21 1 2 10K_0201_5% CLKREQ_PCIE#0 CT33 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_P2_C AB19 GPIO_6 Y2 TBT_DDC_CLK
    <7> DDI2_PTX_TBRX_P2

    SINK PORT 1
    CPU DDI2
    CT34 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_N2_C AC19 DPSNK1_ML2_P GPIO_7 AA1 TBT_SRC_CFG1
    <7> DDI2_PTX_TBRX_N2 DPSNK1_ML2_N GPIO_8 J4 TBT_I2C_INT# TBT_I2C_INT# <41>
    @ RT33 1 2 2.2K_0201_5% TBT_DDC_CLK CT35 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_P3_C AB21 POC_GPIO_0 E2
    <7> DDI2_PTX_TBRX_P3

    POC GPIO
    @ RT34 1 2 2.2K_0201_5% TBT_DDC_DATA CT36 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_N3_C AC21 DPSNK1_ML3_P POC_GPIO_1 D4 RTD3_USB_PWR_EN
    <7> DDI2_PTX_TBRX_N3 DPSNK1_ML3_N POC_GPIO_2 H4 TBT_FORCE_PWR TBT_FORCE_PWR <13>
    @ RT51 1 2 10K_0201_5% TBT_RESET_N_R CT108 2 1 0.1U_0201_6.3V6K CPU_DDI2_AUXP_C Y12 POC_GPIO_3 F2 TBT_BATLOW#
    <7> CPU_DDI2_AUXP DPSNK1_AUX_P POC_GPIO_4
    CT107 2 1 0.1U_0201_6.3V6K CPU_DDI2_AUXN_C W12 D2 TBT_SLP_S3# RT119 2 1 0_0201_5% SIO_SLP_S3# <12,36,37>
    <7> CPU_DDI2_AUXN DPSNK1_AUX_N POC_GPIO_5
    R07_0803: Adjust RESET_N rising time F1 RTD3_CIO_PWR_EN
    POC_GPIO_6 RTD3_CIO_PWR_EN <13>
    Y6
    <7> CPU_DP2_HPD DPSNK1_HPD
    C E1 TBT_TEST_EN RT3 2 1 100_0201_1% C
    RT26 1 2 10K_0201_5% RTD3_CIO_PWR_EN Y8 TEST_EN

    Misc
    <7> CPU_DP2_CTRL_CLK DPSNK1_DDC_CLK
    RT52 1 2 10K_0201_5% RTD3_USB_PWR_EN <7> CPU_DP2_CTRL_DATA N4 AB5 TBT_TEST_PWRG RT4 2 1 100_0201_1%
    DPSNK1_DDC_DATA TEST_PWR_GOOD
    R04_0609: Change RTD3 CIO & USB PWR EN GPIO to PU 2 1 Y18 F4 TBT_RESET_N_R
    RT5 14K_0402_1% DPSNK_RBIAS RESET_N YT1
    TBT_JTAG_TDI Y4 D22 XTAL_25_IN 1 2
    +3VA_TBT TBT_JTAG_TMS V4 TDI XTAL_25_IN D23 XTAL0 GND0
    TBT_JTAG_TCK T4 TMS XTAL_25_OUT XTAL_25_OUT 0_0201_5% 2 1 RT11 XTAL_25_OUT_R 3 4
    TBT_JTAG_TDO W4 TCK AB3 TBT_ROM_DI XTAL1 GND1
    TDO MISC EE_DI
    RT35 1 2 2.2K_0201_5% TBT_I2C_DATA AC4 TBT_ROM_DO 25MHZ_10PF_7V25000014
    RT36 1 2 2.2K_0201_5% TBT_I2C_CLK TBT_RBIAS H6 EE_DO AC3 TBT_ROM_CS#
    @ RT22 1 2 10K_0201_5% TBT_PCIE_WAKE# 1 2 TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_ROM_CLK
    RT23 1 2 10K_0201_5% TBT_CIO_PLUG_EVENT# RT10 4.75K_0402_0.5% RSENSE EE_CLK
    1 1
    RT25 1 2 10K_0201_5% TBT_BATLOW# A15 B7
    <42> TBT_USB3_RX1_P PA_RX1_P PB_RX1_P
    RT47 1 2 10K_0201_5% TBT_I2C_INT# <42> TBT_USB3_RX1_N B15 A7 CT44 CT43
    PA_RX1_N PB_RX1_N 10P_0402_50V8J~D 8.2P_0402_50V8J~D
    CT37 2 1 0.22U_0201_6.3V6M TBT_USB3_TX1_P_C A17 A9 2 2
    <42> TBT_USB3_TX1_P PA_TX1_P PB_TX1_P
    RT37 1 2 100K_0201_5% TBT_TMU_CLK_OUT CT38 2 1 0.22U_0201_6.3V6M TBT_USB3_TX1_N_C B17 B9
    <42> TBT_USB3_TX1_N PA_TX1_N PB_TX1_N
    RT38 1 2 100K_0201_5% TBT_FORCE_PWR
    @ RT39 1 2 100K_0201_5% RTD3_CIO_PWR_EN <42> TBT_USB3_TX0_P CT39 2 1 0.22U_0201_6.3V6M TBT_USB3_TX0_P_C A19 A11 R04_0609: Fine tune cap by vendor suggestion
    @ RT40 1 2 100K_0201_5% RTD3_USB_PWR_EN CT40 2 1 0.22U_0201_6.3V6M TBT_USB3_TX0_N_C B19 PA_TX0_P PB_TX0_P B11
    <42> TBT_USB3_TX0_N PA_TX0_N PB_TX0_N
    RT43 1 2 100K_0201_5% TBT_HPD

    TBT PORTS
    RT44 1 2 1M_0201_1% TBT_LSTX B21 A13
    <42> TBT_USB3_RX0_P PA_RX0_P PB_RX0_P
    RT45 1 2 1M_0201_1% TBT_LSRX A21 B13

    Port A

    PORT B
    <42> TBT_USB3_RX0_N PA_RX0_N PB_RX0_N
    RT50 1 2 100K_0201_5% NC_B4
    RT48 1 2 100K_0201_5% NC_B5 CT41 2 1 0.1U_0201_6.3V6K TBT_AUX_P_C Y15 Y16
    <41> TBT_AUX_P PA_DPSRC_AUX_P PB_DPSRC_AUX_P
    RT49 1 2 100K_0201_5% NC_G2 <41> TBT_AUX_N CT42 2 1 0.1U_0201_6.3V6K TBT_AUX_N_C W15 W16
    PA_DPSRC_AUX_N PB_DPSRC_AUX_N
    E20 E19
    <41> TBT_USB2_D_P PA_USB2_D_P PB_USB2_D_P
    <41> TBT_USB2_D_N D20 D19
    PA_USB2_D_N PB_USB2_D_N
    <41> TBT_LSTX TBT_LSTX A5 B4 NC_B4
    PA_LSTX PB_LSTX

    POC
    POC
    TBT_LSRX A4 B5 NC_B5
    <41> TBT_LSRX PA_LSRX PB_LSRX
    TBT_HPD M4 G2 NC_G2
    <41> TBT_HPD PA_DPSRC_HPD PB_DPSRC_HPD
    RT12 2 1 499_0201_1% H19 F19 RT164 2 1 499_0201_1%
    PA_USB2_RBIAS PB_USB2_RBIAS
    B B
    AC23 D6
    AB23 THERMDA MONDC_SVR
    THERMDA A23
    V18 ATEST_P B23
    PCIE_ATEST ATEST_N
    AC1 DEBUG E18
    NOTE: TEST_EDM USB2_ATEST
    ASSEMBLE R297, R299 if DPSRC L15
    FUSE_VQPS_64 MONDC_DPSNK_0
    W13
    N15
    NOT IN USE FUSE_VQPS_128 W18
    C23 MONDC_DPSNK_1 AR/PPS COMMON FLASH
    TBT_SRC_CFG1 R1403 1 2 1M_0201_1% C22 MONDC_CIO_0 AB2
    MONDC_CIO_1 MONDC_DPSRC
    TBT_SRC_HPD R1405 1 2 1M_0201_1% @ UT1A
    AR-A1_BGA337

    VCC3V3_TBT_LDO VCC3V3_TBT_LDO

    0.1U_0201_6.3V6K
    1

    1
    1

    3.3K_0201_1%

    3.3K_0201_1%

    3.3K_0201_1%

    3.3K_0201_1%
    RT15

    RT18

    RT16

    RT17
    CT47
    2

    2
    UT5
    8 1 TBT_ROM_CS#
    TBT_ROM_HOLD# 7 VCC CS# 2 TBT_ROM_DO
    TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_WP#
    TBT_ROM_DI 5 CLK WP#(IO2) 4
    9 DI(IO0) GND
    thermal pad
    W25Q80DVZPIG_WSON8

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2012/07/25 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P39-AR_TBT (1/2) DP / PCIE
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-C881P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, October 13, 2015 Sheet 39 of 59
    5 4 3 2 1
    5 4 3 2 1

    +3VA_TBT

    +3V_TBT
    +VCC0V9_DP +3V_TBT +3VA_TBT +3VA_TBT_LC +3V_TBT_S0

    @ RT46 2 1 0_0402_5%~D

    1U_0201_6.3V6M
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1 1

    0.1U_0201_6.3V6K

    1U_0201_6.3V6M
    1 1 1 1 1 1 1

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    CT57
    CT50
    1 1 1 1 1
    CT62

    CT63

    CT64

    CT65

    CT66

    CT67

    CT68
    +3VALW

    CT53

    CT54

    CT55

    CT56
    2 2

    CT52
    2 2 2 2 2 2 2
    RT113 2 1 0_0402_5%~D 2 2 2 2 2

    R13
    +VCC0V9_DP

    R6

    H9
    F8
    D D
    R07_0723: Change AR Sx power from +3VALW L8 A2

    VCC3P3_S0
    VCC3P3_LC

    VCC3P3_SX

    VCC3P3A
    L11 VCC0P9_DP VCC3P3_SVR A3
    L12 VCC0P9_DP VCC3P3_SVR B3
    +VCC0V9_PCIE +VCC0V9_USB M8 VCC0P9_DP VCC3P3_SVR
    T11 VCC0P9_DP
    T12 VCC0P9_DP L9 VCC0V9_SVR
    L6 VCC0P9_DP VCC0P9_SVR M9
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
    1 1 1 1 1 1 VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
    V11 E13
    VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA
    CT80

    CT71

    CT72

    CT81

    CT93

    CT94

    CT92

    CT91

    CT83

    CT84

    CT74

    CT85

    CT86
    V12 F11
    +3VS +3V_TBT +VCC0V9_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
    2 2 2 2 2 2 RT241 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
    0_0603_5%~D M13 VCC0P9_SVR_ANA F15
    1 2 M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
    M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
    L19 VCC0P9_PCIE 0.6uH, 5A, 20m ohm by TB CRB
    N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND LT1 1 2 0.60UH +-20% MND-04ABIR60M-XGL
    L18 VCC0P9_ANA_PCIE_1 SVR_IND C2

    47U_0603_6.3V M

    47U_0603_6.3V M

    47U_0603_6.3V M
    M18 VCC0P9_ANA_PCIE_2 SVR_IND D1
    VCC0P9_ANA_PCIE_2 SVR_IND 1 1 1
    N18

    VCC
    +VCC0V9_USB VCC0P9_ANA_PCIE_2

    CT88

    CT89

    CT90
    +VCC0V9_CIO
    R15 A1
    R16 VCC0P9_USB SVR_VSS B1 2 2 2
    VCC0P9_USB SVR_VSS R04_0602: Change 47uF CPN
    B2
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    R8 SVR_VSS
    1 1 1 VCC0P9_CIO
    +VCC0V9_CIO R9
    VCC0P9_CIO
    CT101

    CT102

    CT103

    +3V_TBT R11
    +3V_TBT_S0 R12 VCC0P9_CIO F18 VCC0V9_LVR_OUT
    2 2 2 LT14 VCC0P9_CIO VCC0P9_LVR H18

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    1 2 VCC_3V3_PCIE L16 VCC0P9_LVR J11
    VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1
    J16 H11

    CT95

    CT96

    CT97

    CT98
    VCC_3V3_USB2

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    LQM18PN1R0MFHD_2P VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE
    1 1
    A6 V5
    1U_0201_6.3V6M

    47U_0603_6.3V M

    47U_0603_6.3V M
    VSS_ANA VSS_ANA 2 2 2 2

    CT99

    CT100
    1 1 1 A8 V6
    A10 VSS_ANA VSS_ANA V8
    2 2 VSS_ANA VSS_ANA
    CT163

    CT164

    CT165
    A12 V9
    A14 VSS_ANA VSS_ANA V15
    C C
    2 2 2 A16 VSS_ANA VSS_ANA V16
    A18 VSS_ANA VSS_ANA V20
    A20 VSS_ANA VSS_ANA W5
    A22 VSS_ANA VSS_ANA W6
    B6 VSS_ANA VSS_ANA W8
    B8 VSS_ANA VSS_ANA W9
    B10 VSS_ANA VSS_ANA W20
    B12 VSS_ANA VSS_ANA W22
    B14 VSS_ANA VSS_ANA W23
    B16 VSS_ANA VSS_ANA Y9
    B18 VSS_ANA VSS_ANA Y13
    B20 VSS_ANA VSS_ANA Y20
    R04_0602: Change 47uF CPN VSS_ANA VSS_ANA
    B22 AA22
    D8 VSS_ANA VSS_ANA AA23
    D9 VSS_ANA VSS_ANA AB6
    D11 VSS_ANA VSS_ANA AB8
    D12 VSS_ANA VSS_ANA AB10
    D13 VSS_ANA VSS_ANA AB12
    D15 VSS_ANA VSS_ANA AB14
    D16 VSS_ANA VSS_ANA AB16

    GND
    D18 VSS_ANA VSS_ANA AB18
    E8 VSS_ANA VSS_ANA AB20
    E9 VSS_ANA VSS_ANA AB22
    E11 VSS_ANA VSS_ANA AC6
    E15 VSS_ANA VSS_ANA AC8
    E16 VSS_ANA VSS_ANA AC10
    E22 VSS_ANA VSS_ANA AC12
    E23 VSS_ANA VSS_ANA AC14
    F9 VSS_ANA VSS_ANA AC16
    F16 VSS_ANA VSS_ANA AC18
    F20 VSS_ANA VSS_ANA AC20
    G22 VSS_ANA VSS_ANA AC22
    G23 VSS_ANA VSS_ANA D5
    H1 VSS_ANA VSS E4
    H2 VSS_ANA VSS E5
    H12 VSS_ANA VSS E6
    H13 VSS_ANA VSS F5
    B
    H15 VSS_ANA VSS F6 B
    H16 VSS_ANA VSS H5
    H20 VSS_ANA VSS H8
    J5 VSS_ANA VSS J8
    J18 VSS_ANA VSS J12
    J19 VSS_ANA VSS J13
    J20 VSS_ANA VSS J15
    J22 VSS_ANA VSS L13
    J23 VSS_ANA VSS M11
    K1 VSS_ANA VSS M12
    K2 VSS_ANA VSS N8
    L5 VSS_ANA VSS N9
    L20 VSS_ANA VSS N11
    L22 VSS_ANA VSS N12
    L23 VSS_ANA VSS N13
    M1 VSS_ANA VSS T6
    M2 VSS_ANA VSS T8
    M5 VSS_ANA VSS T9
    M19 VSS_ANA VSS T13
    M20 VSS_ANA VSS T15
    N5 VSS_ANA VSS T16
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    N20 VSS_ANA VSS T18
    N22 VSS_ANA VSS AB1
    N23 VSS_ANA VSS AC2
    VSS_ANA VSS
    @ UT1B
    P1
    P2
    R5
    R18
    R19
    R20
    R22
    R23
    T1
    T2
    T5
    T20
    U22
    U23
    AR-A1_BGA337

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2012/07/25 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P40-AR_TBT (2/2) PWR / VSS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-C881P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, October 13, 2015 Sheet 40 of 59
    5 4 3 2 1
    5 4 3 2 1

    +3V_VC TBT_VBUS VCC3V3_TBT_SX VCC3V3_TBT_LDO

    +5VALW
    1 1 1

    1
    C1354 C1353 C1345 C1346
    1U_0201_6.3V6M 1U_0603_25V6 1U_0201_6.3V6M 10U_0402_6.3V6M

    2
    2 2 2
    1 1 1 1
    C1347 C1348 C1349 C1350
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    D R07_0720: Change "VCC5V0_SYS" D
    2 2 2 2
    to "+5VALW"
    VCC1V8A_TBT_LDO VCC1V8D_TBT_LDO TBT_LDO_BMC

    1 1 1
    CT151 CT152 CT144
    4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 2.2U_0402_6.3V6M
    2 2 2

    R07_0720: Change PD to MP CPN


    U722

    +PP_HV A6 B10 PD_SENSEP <44>


    A7 PP_HV SENSEP A10
    PP_HV SENSEN PD_SENSEN <44>
    1 A8

    4.7U_0603_25V6K
    B7 PP_HV

    @ C1341
    PP_HV B9 T193 PAD~D @
    A11 HV_GATE1 A9 T194 PAD~D @ TBT_VBUS_L TBT_VBUS
    2 +5VALW PP_5V0 HV_GATE2
    C11 EMI@ LT106
    B11 PP_5V0
    D11 PP_5V0 H11 1 2
    PP_5V0 VBUS J10
    H10 VBUS J11 HCB2012KF-121T50_0805
    PP_CABLE VBUS

    2
    BAT54LPS-7
    K11
    VBUS

    D123
    B1 C1339
    VDDIO 1U_0603_25V6 EMI@ DI7

    2
    H1 H2 AZ4024-02S_SOT23-3~D
    +3V_VC VIN_3V3 VOUT_3V3 VCC3V3_TBT_SX
    G1 VCC3V3_TBT_LDO

    2
    VCC3V3_TBT_LDO LDO_3V3 K1
    VCC1V8A_TBT_LDO

    1
    D1 LDO_1V8A A2
    <39> TBT_I2C_DATA I2C_SDA1 LDO_1V8D VCC1V8D_TBT_LDO
    C R1477 1 2 3.3K_0402_1% PD_EE_CS# <39> TBT_I2C_CLK D2 E1 TBT_LDO_BMC C
    R1475 1 2 3.3K_0402_1% PD_EE_DO C1 I2C_SCL1 LDO_BMC
    <39> TBT_I2C_INT# I2C_IRQ1_N
    R1474 1 2 3.3K_0402_1% PD_EE_WP#
    R1476 1 2 3.3K_0402_1% PD_HOLD# A5
    <37> UPD_SMBDAT I2C_SDA2
    B5
    <37> UPD_SMBCLK I2C_SCL2
    <37> UPD_SMBINT# B6 L9 TBT_CC1 <42>
    I2C_IRQ2_N C_CC1 L10
    C_CC2 TBT_CC2 <42>
    PD_EE_CLK A3 K9 1 1

    220P_0402_50V8K

    220P_0402_50V8K
    PD_EE_DI B4 SPI_CLK RPD_G1 K10

    C1279

    C1280
    PD_EE_DO A4 SPI_MOSI RPD_G2
    PD_EE_CS# B3 SPI_MISO
    SPI_SS_N K6 2 2
    VCC3V3_TBT_LDO C_USB_TP TBT_USB2_T_P <42>
    L6
    C_USB_TN TBT_USB2_T_N <42>
    L5
    <39> TBT_USB2_D_P USB_RP_P
    <39> TBT_USB2_D_N K5
    USB_RP_N K7
    C_USB_BP TBT_I2C_B_P <42>
    UT6 L7 TBT_I2C_B_N <42>
    PD_EE_CS# 1 8 J1 C_USB_BN
    /CS VCC <39> TBT_AUX_P AUX_P
    PD_EE_DO 2 7 PD_HOLD# J2
    DO(IO1) /HOLD(IO3) <39> TBT_AUX_N AUX_N
    PD_EE_WP# 3 6 PD_EE_CLK K8 TBT_PD_SBU1 R1457 1 2 0_0201_5% TBT_SBU1 <42>
    DAP

    4 /WP(IO2) CLK 5 PD_EE_DI C_SBU1 L8 TBT_PD_SBU2 R1458 1 2 0_0201_5%


    GND DI(IO0) C_SBU2 TBT_SBU2 <42>
    @ TC29 G4
    @ TC25 F4 SWD_CLK
    9

    SWD_DATA B2 @ TC35
    GPIO0 C2 R1436 1 @ 2 0_0402_1%
    GPIO1 EN_PD_HV <44>
    E2 D10
    UART_TX GPIO2 PWR_SRC_ON_PC <44>
    R04_0612: Change PD ROM CPN to SA00005I940 R1471 1 20_0201_5% F2 G11 @ TC38
    UART_RX GPIO3 C10 R1437 1 @ 2 0_0402_1%
    GPIO4 TBT_HPD <39>
    TBT_LSTX_R L4 E10 @ TC36
    VCC3V3_TBT_LDO TBT_LSRX_R K4 LSTX/R2P GPIO5 G10
    LSRX/P2R GPIO6 D7 1 2 0_0402_1% PWR_SRC_LIMIT <44>
    R1439 @ SYSTEM_WAKE#
    R1454 1 2 10K_0402_5% TBT_DBG_CTL1 E4 GPIO7 H6 R1438 1 @ 2 0_0402_1%
    DEBUG_CTL1 GPIO8 TBT_USB_OC0# <11>
    R1460 1 2 10K_0402_5% TBT_DBG_CTL2 D5
    DEBUG_CTL2
    <25,37,38> USBC_MCP23017_SMBCLK R1441 1 @ 2 0_0402_1% USBC_MCP23017_SMBCLK_R L2 @ R1465 1 2 0_0201_5% UPD_MRESET <37,39>
    R1442 1 @ 2 0_0402_1% USBC_MCP23017_SMBDAT_R K2 DEBUG1 E11 R1468 1 2 100K_0402_5%
    <25,37,38> USBC_MCP23017_SMBDAT DEBUG2 MRESET
    B B
    TBT_DEBUG3 L3 F11
    DEBUG3 RESET_N TBT_RESET_N <39>
    TBT_DEBUG4 K3
    DEBUG4 F10 @ RT199 1 2 0_0402_5%
    BUSPOWER_N VCC3V3_TBT_LDO
    F1
    I2C_ADDR G2 RT201 1 2 0_0402_5%
    R_OSC VCC1V8A_TBT_LDO
    H7
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    SS
    1

    1
    100K_0201_5%

    100K_0201_5%

    0_0402_5%

    15K_0402_1%
    1

    1
    RT188

    RT187

    RT190

    0.22U_0201_6.3V6M

    0_0402_5%
    @ RT200
    1
    VCC3V3_TBT_LDO

    C618

    R1473
    TPS65982_BGA96
    A1
    D6
    E5
    E6
    E7
    F5
    G5
    H4
    H5
    B8
    D8
    E8
    F6
    F7
    F8
    G6
    G7
    G8
    H8
    L1
    L11
    2

    @ R1478 1 2 100K_0402_5% TBT_AUX_N 2

    2
    @ R1472 1 2 100K_0402_5% TBT_AUX_P +3VA_TBT

    1
    R1459 1 20_0201_5% TBT_LSTX_R R1462
    <39> TBT_LSTX
    100K_0402_5%
    <39> TBT_LSRX R1461 1 20_0201_5% TBT_LSRX_R

    2
    G
    2
    SYSTEM_WAKE# 3 1 R1440 1 @ 2 0_0402_1%
    PWR_TB_DOCK# <37>
    @ R1463 1 20_0201_5% TBT_DEBUG3

    D
    @ R1464 1 20_0201_5% TBT_DEBUG4
    QT19
    L2N7002WT1G_SC-70-3

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2012/07/25 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P41-PD CONTROL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 41 of 59
    5 4 3 2 1
    5 4 3 2 1

    TBT_VBUS

    1
    CT9
    1U_0603_25V6

    2
    D TBT_VBUS TBT_VBUS D

    R93 1 @ 2 0_0402_5%~D JUSBC1


    A1 B12
    GND GND
    DLW21HN900SQ2L_4P TBT_USB3_TX0_P A2 B11 TBT_USB3_RX0_P
    <39> TBT_USB3_TX0_P SSTXP1 SSRXP1 TBT_USB3_RX0_P <39>
    1 2 TBT_USB2_T_P_R TBT_USB3_TX0_N A3 B10 TBT_USB3_RX0_N
    <41> TBT_USB2_T_P 1 2 <39> TBT_USB3_TX0_N SSTXN1 SSRXN1 TBT_USB3_RX0_N <39>
    C397 1 2 A4 B9 2 1 C398
    4 3 TBT_USB2_T_N_R 0.47U_0402_25V6K VBUS VBUS 0.47U_0402_25V6K
    <41> TBT_USB2_T_N 4 3
    <41> TBT_CC1 TBT_CC1 A5 B8 TBT_SBU2 TBT_SBU2 <41>
    ML6 EMI@ CC1 RFU2
    TBT_USB2_T_P_R A6 B7 TBT_I2C_B_N_R
    R94 1 @ 2 0_0402_5%~D TBT_USB2_T_N_R A7 DP1 DN2 B6 TBT_I2C_B_P_R
    DN1 DP2

    Bottom
    <41> TBT_SBU1 TBT_SBU1 A8 B5 TBT_CC2 TBT_CC2 <41>
    RFU1 CC2

    TOP
    R95 1 @ 2 0_0402_5%~D C401 1 2 A9 B4 2 1 C402
    0.47U_0402_25V6K VBUS VBUS 0.47U_0402_25V6K
    TBT_USB3_RX1_N A10 B3 TBT_USB3_TX1_N
    DLW21HN900SQ2L_4P <39> TBT_USB3_RX1_N SSRXN2 SSTXN2 TBT_USB3_TX1_N <39>
    <39> TBT_USB3_RX1_P TBT_USB3_RX1_P A11 B2 TBT_USB3_TX1_P TBT_USB3_TX1_P <39>
    4 3 TBT_I2C_B_N_R SSRXP2 SSTXP2
    <41> TBT_I2C_B_N 4 3 A12 B1
    GND GND
    1 2 TBT_I2C_B_P_R
    <41> TBT_I2C_B_P 1 2 1 4
    ML7 EMI@ GND GND
    2 3
    R96 1 @ 2 0_0402_5%~D GND GND

    JAE_DX07SA24XJ2
    CONN@

    C C

    D75 EMI@ D84 EMI@

    TBT_USB3_TX0_P 1 2 TBT_USB3_RX0_P 1 2

    ESD8011MUT5G ESD8011MUT5G

    D76 EMI@ D85 EMI@

    TBT_USB3_TX0_N 1 2 TBT_USB3_RX0_N 1 2

    ESD8011MUT5G ESD8011MUT5G

    D77 EMI@ D87 EMI@

    TBT_CC1 1 2 TBT_SBU2 1 2

    ESD8011MUT5G ESD8011MUT5G

    D78 EMI@ D86 EMI@

    TBT_SBU1 1 2 TBT_CC2 1 2

    ESD8011MUT5G ESD8011MUT5G
    B B

    D79 EMI@ D89 EMI@

    TBT_USB3_RX1_N 1 2 TBT_USB3_TX1_N 1 2

    ESD8011MUT5G ESD8011MUT5G

    D80 EMI@ D88 EMI@

    TBT_USB3_RX1_P 1 2 TBT_USB3_TX1_P 1 2

    ESD8011MUT5G ESD8011MUT5G

    D82 EMI@ D90 EMI@

    TBT_USB2_T_P_R 1 2 TBT_I2C_B_N_R 1 2

    ESD8011MUT5G ESD8011MUT5G

    D83 EMI@ D91 EMI@

    TBT_USB2_T_N_R 1 2 TBT_I2C_B_P_R 1 2

    ESD8011MUT5G ESD8011MUT5G

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2012/07/25 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P42-PD USB TYPE-C
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-C881P 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, October 13, 2015 Sheet 42 of 59
    5 4 3 2 1
    5 4 3 2 1

    +3VLAW
    NVDC B+ +3VALW: TDC:5.2A / 5.5A
    DC IN CHARGER +5VALW: TDC:7.9A +5VALW
    BQ24777 SY8286BRAC/SY8288C Page 48
    Page 46
    D D

    +1.2V_DDR
    +1.2V_DDR: TDC:4.1A
    +0.6VS: TDC:0.4A +0.6VS
    SY8210AQVC Page 49

    +1.0VA: TDC:2.6A +1.0VA


    Trinity docking USB type-C PD SYX196DQNC Page 50
    USB type-C adapter TPS65982 Battery
    (2S2P)
    C +1.8VA C

    +1.8VA: TDC:0.4A
    +1.8VU: TDC:0.42A Page 51 +1.8VU
    TLV62150RGTR Page 52

    +1.0VS_VCCIO
    +1.0VS_VCCIO: TDC:2.2A
    +1.0V_PRIM_CORE: TDC:1.8A +1.0V_PRIM_CORE
    TPS62134ARGT/TPS62134DPage 56

    B
    +VCC_EDRAM B
    +VCC_EDRAM: TDC:2.5A
    +VCC_EOPIO: TDC:1.4A +VCC_EOPIO
    TPS62134CRGT Page 57

    +VCC_CORE
    +VCC_CORE: TDC: 21A
    +VCC_GT: TDC: 32A Page 54
    +VCC_GT
    ISL95857HRTZ+CSD97374CQ4M
    +VCC_SA: TDC: 5A
    +VCC_SA
    A
    ISL95857HRTZ+ Page 53 A

    (ISL95808HRZ+AON7934)
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P42-PWR_Block_Diagram
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 43 of 59
    5 4 3 2 1
    5 4 3 2 1

    Remove source back function


    B+ Power S9 S8 Barrel Adapter
    B+
    P-MOSFET
    @ PQ200
    AON2409_DFN6-8
    P-MOSFET
    @ PQ201
    AON2409_DFN6-8 +DC_IN P-MOSFET
    S1 S2
    P-MOSFET
    +SDC_IN
    7 7 @ PR200 PQ202 PQ203
    6 8 8 6 0.01_1206_1% AON2409_DFN6-8 AON2409_DFN6-8
    5 4 4 5 7 7
    2 2 1 4 8 6 6 8
    1 1 4 5 5 4

    100K_0402_5%
    1
    2 3 2 +DC_IN_SS 2

    LP2305LT1G_SOT23-3

    0.022U_0603_50V7K

    0.022U_0603_50V7K
    1 1

    @ PR201

    100K_0402_5%
    LP2305LT1G_SOT23-3
    3

    3
    1

    1
    1M_0402_1%

    1M_0402_1%

    0.022U_0603_50V7K
    1

    1
    @ PR202

    @ PC200

    PC201

    PR203

    PR204
    3

    3
    3

    1
    PQ205
    100K_0402_5%

    100K_0402_5%
    G G

    1
    2 2

    @ PQ204

    PR205

    PC202

    @ PR206
    2

    2
    D D

    2
    D D

    100K_0402_5%

    1
    1

    2
    @ PR207
    S 2 1 S

    1
    @ PR289

    1M_0402_1%

    AC_DET
    100K_0402_5%
    1
    100K_0402_1% @ PD202 PR209

    PR208
    2

    1
    1 2 SDMK0340L-7-F_SOD323-2 200K_0402_1%

    PR211
    +PP_HV

    1
    @ PR210
    100K_0402_5% PR212

    2
    +3VALW @ PR213 @ PD200 @ PR214 @ PR222 100K_0402_5%

    1
    0_0402_5% BAT54CW-7-F_SOT323-3~D 0_0402_5% 44.2_0402_1%

    100K_0402_5%
    2
    DMN66D0LDW-7_SOT363-6

    DMN66D0LDW-7_SOT363-6
    OCP setting: 3A VBUS_ACOK 1 2 2 INA199_OUT 1 2 1 2

    @ PR215
    2
    6
    D

    6
    DMN66D0LDW-7_SOT363-6

    DMN66D0LDW-7_SOT363-6

    DMN66D0LDW-7_SOT363-6
    @ PR216 1 2 D

    PQ206A
    USB type-C PD OCP 0_0402_5% G @ PR218 @ PU200 2 PR217 PR220

    PQ207A

    2
    6

    3
    1 2 3 D 0_0402_5% From EC 1 6 G 0_0402_5% D 0_0402_5% D
    REF Out

    1
    2 1 2 DCIN_ACOK 1 2 2 DCIN_ACOK# 1 2 5

    @ PQ208A

    PQ209A

    PQ209B
    S

    1M_0402_1%
    1
    G PWR_SRC_ON <37> G G

    PR219
    S

    1
    1
    @ PR290
    @ PD201 100K_0402_1% S @ PR221 S S

    4
    DMN66D0LDW-7_SOT363-6
    SDMK0340L-7-F_SOD323-2 @ PR283 0_0402_5%

    2
    1 2 100K_0402_5% @ PR223 2 5 1 2
    0_0402_5% GND IN-
    120K_0402_1%

    221K_0402_1%~D

    2
    1

    +SDC_IN
    1 2 3 4 1 2 @ PR228
    V+ IN+
    1

    3
    @ PR227 0_0402_5% D
    @ PR224

    1.8M_0402_1% INA199A1DCKR_SC70-6 @ PR225 1 2 5


    @ PR226

    PQ207B
    <37,46> AC_DIS

    1
    1 2

    DMN66D0LDW-7_SOT363-6
    @ PC203 0_0402_5% G
    0.1U_0402_25V7K
    2

    @ PR229 S
    2

    4
    3
    D 0_0402_5% From TI PD GPIO2
    8

    @ PQ208B
    to TI PD GPIO6 5 1 2
    INA199_OUT 3 G PWR_SRC_ON_PC <41>
    P

    1
    1
    2 O PWR_SRC_LIMIT <41>
    S

    4
    -
    G

    @ PR282
    @ PU201A 100K_0402_5%
    220P_0402_50V7K

    1000P_0402_50V7K
    4

    LM393DMR2G_MICRO8

    2
    1

    @ PC205
    100K_0402_1%

    1
    @ PR230

    @ PC204

    2
    2

    C
    S6 S7 C

    USB type-C Adapter


    S11 PQ210
    P-MOSFET
    PQ211
    P-MOSFET
    PQ212
    SD00000K820 to SD011000080
    PR231
    AON2409_DFN6-8 For Inrush (CTO) AON2409_DFN6-8 AON2409_DFN6-8 0_1206_5%
    7 7 7
    +3VALW 6 8 8 6 6 8 1 4
    5 4 +AC_IN 4 5 +VBUS_DC_SS 5 4
    TBT_VBUS

    LP2305LT1G_SOT23-3
    2 2 2 2 3
    S11 OVP

    100K_0402_5%
    0.022U_0603_50V7K

    1
    1 1 1

    0.022U_0603_50V7K

    1
    @ PR236

    PR235
    1M_0402_1%
    100K_0402_5%

    LP2305LT1G_SOT23-3

    0.022U_0603_50V7K
    1

    3
    0_0402_5%

    PQ214
    PR237

    PC208
    1M_0402_1%

    1M_0402_1%
    G

    3
    1
    2 1 2

    PC206

    PR232

    @ PR233

    PR234
    PD_SENSEN <41>

    1
    @ PC207
    G

    2
    2 D 1 2

    @ PQ213
    2

    1
    PD_SENSEP <41>
    1

    100K_0402_1%

    @ PD203

    2
    SDMK0340L-7-F_SOD323-2 D @ PR238
    @ PR253
    @PR253

    1
    1 2 @ PR252 @ PR239 S 0_0402_5%
    100K_0402_1% 0_0402_5%
    130K_0402_1%

    100K_0402_5%
    1

    1
    S 1 2
    2

    1
    @ PR258 PR244
    Follow berlinetta design change:
    @ PR254

    PR245
    1.8M_0402_1%

    1
    1 2 @ PR288 PR241 @ PR242 200K_0402_1% Remove PD sense
    0_0402_5% 1M_0402_1% 100K_0402_5% PR243
    2

    2
    1 2
    TBT_VBUS PD_OVP 200K_0402_1%

    2
    DMN66D0LDW-7_SOT363-6
    DMN66D0LDW-7_SOT363-6
    For Inrush (CTO)

    2
    DMN66D0LDW-7_SOT363-6

    @ PR264 @ PU201B PR287 PR248


    8

    3
    150K_0402_1% LM393DMR2G_MICRO8 @ PR265 From EC 0_0402_5% D D 0_0402_5%
    6

    PQ216B
    1 2 5 0_0402_5% D 1 2 2 PR284 5 2 1VBUS_ACOK

    PQ215A
    P

    + <37,44> VBUS_HV_DIS#

    1
    7 1 2 2 G 0_0402_5% D G
    @ PQ218A

    DMN66D0LDW-7_SOT363-6
    6 G DCIN_ACOK# 1 2 5 @ PR286
    -
    G

    S G 0_0402_5% S PR250
    0.01U_0402_25V7K

    6
    PQ215B 0_0402_5% D
    S Follow berlinetta design change:
    100K_0402_1%

    200K_0402_1%

    1200P_0402_50V7K
    100P_0402_50V8J

    1
    1

    DMN66D0LDW-7_SOT363-6 DCIN_ACOK 1 2 2
    @ PC213

    PQ217A
    S

    2
    1

    S11 control by EC @ PR249 G


    @ PR268

    @ PC211

    @ PR269

    1
    D
    0_0402_5% PR291 PR285
    @ PC212

    6
    DCIN_ACOK 1 2 2 From TI PD GPIO1 10K_0402_1% 0_0402_5% D PR251 S
    2

    1
    3
    DMN66D0LDW-7_SOT363-6
    G 1 2 1 2 2 PQ216A D 0_0402_5%
    2

    <41> EN_PD_HV

    PQ217B
    @ PQ224 S G DMN66D0LDW-7_SOT363-6 5 2 1DCIN_ACOK#

    3
    S TR 2N7002KW 1N SOT323-3 From EC G
    S

    1
    1
    VBUS_HV_DIS# 1 2 S

    4
    PR247
    OVP setting: 5.5V @ PD206 100K_0402_5%
    DMN66D0LDW-7_SOT363-6

    SDMK0340L-7-F_SOD323-2
    @ PR274

    2
    3

    B D 0_0402_5% From EC B
    @ PQ218B

    5 1 2
    G VBUS_HV_DIS# <37,44>

    S
    4

    1 3
    D

    +3VALW +3V_VC +3V_VC


    100K_0402_1%

    0.01U_0402_25V7K
    1

    PQ221
    PR275

    PC218

    Barrel_AC Detector Vbus_AC Detector


    G
    2

    LP2305LT1G_SOT23-3
    2
    2
    1

    PR276

    1
    2K_0402_1%

    100K_0402_1%

    100K_0402_1%

    100K_0402_1%
    PR255

    PR256

    PR257

    180K_0402_1%

    100K_0402_1%
    1

    1
    180K_0402_1%
    2

    1
    DMN66D0LDW-7_SOT363-6

    PR260

    PR261
    PR277
    PR259

    2
    6

    0_0402_5% D
    1 2 2 PR262 PR263
    PQ223A

    <44,48> ALW_PWRGD_3V_5V

    2
    G 1.8M_0402_1% 1.8M_0402_1%
    2

    DMN66D0LDW-7_SOT363-6
    1 2 1 2
    S
    For Inrush (CTO)
    1

    6
    D
    DCIN_ACOK# 2

    PQ219A
    PD204 G
    SDMK0340L-7-F_SOD323-2 PR266 PR267
    8

    8
    2 1 @ PR281 140K_0402_1% S 130K_0402_1%
    +DC_IN

    1
    3

    DMN66D0LDW-7_SOT363-6
    0_0402_5% 1 2 5 D 1 2 3
    P

    P
    PD205 1 2 +DC_IN_SS + 7DCIN_ACOK 5 +VBUS_DC_SS + 1 VBUS_ACOK
    PQ219B

    O O
    DCIN_OK set 17V 6 2
    SDMK0340L-7-F_SOD323-2 G
    - -
    G

    G
    2 1
    +PP_HV 3V LDO for OP +3V_LDO PQ222
    PU203B
    LM393DMR2G_MICRO8 S
    PU203A
    LM393DMR2G_MICRO8
    4

    4
    LP2305LT1G_SOT23-3
    PU202
    @ PQ220
    200K_0402_1%

    200K_0402_1%
    16.5K_0402_1%

    16.5K_0402_1%
    220P_0402_50V7K

    220P_0402_50V7K
    1200P_0402_50V7K

    1200P_0402_50V7K
    1

    1
    LDO_EN 1 5 1 3 S TR 2N7002KW 1N SOT323-3
    PR270

    PR272
    D

    VCC OUT +3V_VC


    1

    1
    D
    PC214

    PR271

    PC216

    PR273
    1

    1
    2 PR240 DCIN_ACOK 2
    PC215

    PC217
    100K_0402_1%

    GND 100K_0402_1%
    PR278

    G
    1U_0603_25V6

    G
    1U_0402_16V6K

    2
    1

    A 3 4 1 2 LDO_EN A
    PC210

    S
    2

    3
    NC EN
    1
    PC209

    2
    2

    RT9069-33GB_SOT23-5
    1

    1
    DMN66D0LDW-7_SOT363-6

    PR279
    PR246 PR280 0_0402_5%
    3

    100K_0402_1% D 0_0402_5%
    5 1 2
    PQ206B

    ALW_PWRGD_3V_5V <44,48>
    2

    DCIN_ACOK <37>
    DMN66D0LDW-7_SOT363-6

    G
    3

    S D
    4

    PQ223B

    5
    +3V_VC G

    S
    Security Classification Compal Secret Data Compal Electronics, Inc.
    4

    2014/10/17 2014/12/05 Title


    Docking Power Control(41.1), Support component(41.2) Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P44-PWR_Switch
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 44 of 59
    5 4 3 2 1
    A B C D

    EMC PL100
    HCB2012KF-121T50_0805
    1 2

    EMC PL101
    1
    HCB2012KF-121T50_0805 1

    +PBATT 1 2

    1
    EMC PC100 EMC PC101
    0.01U_0402_25V7K 1000P_0402_50V7K

    TVNST52302AB0_SOT523-3

    TVNST52302AB0_SOT523-3
    1

    1
    PBATT1 connector +3VALW
    SMART

    EMC PD100

    EMC PD101
    Battery:
    1.BATT++

    1
    2.BATT++ GND
    11
    10
    3.CLK_SMB GND PR100

    4.DAT_SMB 9 100K_0402_5%

    2
    9 8
    5.BAT_PRS
    2200P_0402_50V7K

    8 7
    7
    6.SYS_PRES 6
    6 PRP100
    1

    5 BATT_PRS 8 1
    EMC PC102

    7.BAT_ALERT 5
    4
    4 DAT_SMB 7 2 PBAT_PRES# <37,46>
    PBAT_SMBDAT <37>
    3 6 3
    8.GND
    CLK_SMB
    PBAT_SMBCLK <37>
    2

    3 2 5 4
    9.GND
    2 1 PBATT+_C
    1 100_0804_8P4R_5%
    10.GND JBATT1
    2
    11.GND FOX_GS73091-10272-7H 2

    CONN@

    +3VALW

    @ PR101
    0_0402_5%

    1
    1 2
    2.2K_0402_5%
    PR102

    EMC PL102 PR103

    2
    BLM15AG102SN1D_2P 33_0402_5%
    1 2 1 3 1 2

    S
    PS_ID <37>
    PQ100
    1

    FDV301N_G_NL_SOT23-3

    G
    2
    AZ5125-01H.R7G_SOD523-2

    PR104 PR105
    1

    100K_0402_1% 1 2
    3
    +5VALW 3

    10K_0402_1%
    PD102

    1
    C
    2 PQ101
    B MMST3904-7-F_SOT323
    E
    EMC

    3
    1
    2

    PR106
    15K_0402_1%
    2

    JP100
    7 EMC PL103 +DC_IN
    GND2 6 HCB2012KF-121T50_0805
    GND1 5 +DCIN_JACK 1 2
    5 4
    4 3 NB_PSID
    3 2 -DCIN_JACK
    2 1
    1
    ACES_88266-05001
    100P_0402_50V8J

    100P_0402_50V8J
    1000P_0603_50V7K

    1000P_0402_50V7K

    1000P_0402_50V7K

    10U_0805_25V6K

    CONN@
    4.7K_0805_5%
    1

    1
    EMC PC103

    EMC PC104

    EMC PC105

    EMC PC106

    EMC PC107

    EMC PC108

    @ PR107
    2

    4 4

    EMC PL104
    HCB2012KF-121T50_0805
    1 2
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR45_DCIN/BATT CONN
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 45 of 59
    A B C D
    A B C D

    PR300 +PWR_SRC_AC CHAGER_SRC


    0.01_1206_1% PL300 EMC
    HCB2012KF-121T50_0805
    +SDC_IN
    4 1 1 2

    3 2

    22U_0805_25V6M

    22U_0805_25V6M

    22U_0805_25V6M

    22U_0805_25V6M

    22U_0805_25V6M

    22U_0805_25V6M
    2200P_0402_50V7K
    1

    1
    EMC PC301

    PC302

    PC303

    PC304

    PC305

    PC306

    PC307
    1 1

    2
    CSSN_1
    CSSP_1
    PD301 PD300

    1
    SDMK0340L-7-F_SOD323-2 SDMK0340L-7-F_SOD323-2
    2 1 2 1 @ PR303 @ PR304
    +DC_IN_SS +PBATT
    0_0402_5% 0_0402_5%

    PD302

    2
    SDMK0340L-7-F_SOD323-2
    2 1
    +VBUS_DC_SS
    PC309 PC310 PC311
    1U_0603_25V6K
    1 2
    0.1U_0402_25V6
    1 2
    0.1U_0402_25V6
    1 2
    B+
    Near PL201

    4.02K_0402_1%
    1

    1
    294K_0402_1%
    <37,44> AC_DIS

    PR307

    PR305
    PR306 GNDA_CHG GNDA_CHG
    10_1206_1%
    PQ302 PC312

    1
    D 1U_0603_10V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    main:SB00000ST00

    0.1U_0603_25V7K

    0.1U_0603_25V7K

    0.1U_0603_25V7K
    2

    PC316 EMC

    PC319 EMC

    PC320 EMC
    2 PQ302 PC313 BQ24777_REGN 1 2
    2nd:SB00000UO00 G L2N7002WT1G_SC70-3 1U_0805_25V6K

    ACDRV

    ACP

    ACN

    1
    1 2 28

    PC314

    PC315

    PC321

    PC317
    BQ24777_REGN

    3rd:SB00000Z600 S

    3
    2
    VCC 2
    1

    5
    PR310 3 24
    100K_0402_5%

    2
    49.9K_0402_1% CMSRC REGN PR308 PC322 SIR472DP-T1-GE3_POWERPAK8-5
    PR301

    CHARGER_SMBCLK 1 2 6 2.2_0603_5% 0.047U_0603_25V7M PQ303


    ACDET 25 CHG_BTS 1 2CHG_BTS_C 1 2
    CHARGER_SMBDAT 1 2 11 BTST
    2

    pull up 10K in HW side 1 2 @ PR309 0_0402_5% SDA 4


    1 2 12 26
    SCL HIDRV
    CHG_UGATE
    +VCHGR
    1

    PC318 @ PR311 0_0402_5% PR313


    PR312 GNDA_CHG 0.1U_0402_25V6 5 PL301 0.01_1206_1%
    100K_0402_1% ACOK 27 CHG_SW 3.3UH_6.3A_20%_7X7X3_M
    <37> CHARGER_SMBDAT

    3
    2
    1
    7 PHASE 1 2 4 1
    @ PR314 IADP
    <37> CHARGER_SMBCLK
    2

    5
    0_0402_5% 8 23 CHG_LGATE 3 2
    1 2 IDCHG LODRV
    <37> ACAV_IN 9

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0603_25V7K
    PMON

    PC323 EMC
    1 2 PR316 100_0402_1%
    <37> I_ADP
    1

    @ PR315 0_0402_5% 1 2 10 22
    /PROCHOT GND

    1
    PR317 4
    154K_0402_1% 1 2
    <37> I_BATT

    1
    @ PR318 0_0402_5% PR320

    PC324

    PC325

    PC327

    PC328

    PC326

    PC329
    2

    2
    13 21 1 2 BQ24777_REGN PQ304 PR321
    2

    1 2 CMPIN NC EMC 4.7_1206_5%

    3
    2
    1
    <37,53> P_SYS @ PR319 0_0402_5% 14 10K_0402_1% SI7716ADN-T1-GE3_POWERPAK8-5
    CMPOUT 20
    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J

    2
    GNDA_CHG SRP

    20K_0402_1%
    1
    15 19
    PC332 @

    /BATPRES SRN
    1

    1
    PR323
    PR322
    BQ24777_REGN

    PC330

    PC331

    4.02K_0402_1% EMC PC333


    16 18 1 2 1000P_0603_50V7K
    2

    2
    CELL /BATDRV PC334 PC335 @ PC336
    3 3
    2

    29 17 1 2 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6


    GNDA_CHG PWPD BAT 1 2 1 2 1 2
    PR324

    1U_0603_25V6K
    PU300 10_0603_1%

    1
    BQ24777RUYR_WQFN28_4x4

    PC337
    <13,37,47,53> H_PROCHOT#
    1

    GNDA_CHG GNDA_CHG GNDA_CHG


    PR325 @ PR326 0_0402_5%

    2
    1K_0402_1% 1 2
    <37,45> PBAT_PRES#

    ,
    Q
    C
    B
    U
    U
    @ PJP300
    JUMP_43X39 GNDA_CHG
    2

    1 2
    1 2

    BATDRV#
    1

    GNDA_CHG
    TI FAE_Andrew suggest @ PR327
    Cell pin set the voltage of 121K_0402_1%

    three cell (13.5V) for OVP PQ305


    2

    SI4835DDY-T1-E3_SO8

    GNDA_CHG
    +VCHGR 1
    2
    8
    7 +PBATT
    3 6
    5

    4
    BATDRV#
    4

    Charger controller(40.1), Support component(40.2) 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P46-PWR_Charger
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 46 of 59
    A B C D
    5 4 3 2 1

    +3VALW +1.0V_VCCSTG

    PR400 +3VALW
    B+ 1M_0402_1% +3VALW +3VALW

    1
    1 2

    0.01UF_0402_25V7K
    D D

    100P_0402_50V8J
    1.91K_0402_1%

    232K_0402_1%

    10K_0402_1%
    PC402

    1
    @ PR401

    10K_0402_1%
    PC400

    PC401
    .1U_0402_16V7K

    1
    PR402

    PR404
    1 2 PR405

    2
    PR403
    100_0402_1%

    2
    @ @ 1 2
    @ H_PROCHOT# <13,37,46,53>

    2
    PQ400A

    8
    PU400B

    2
    PQ400B

    5
    5 LM393DMR2G_MICRO8 DMN66D0LDW-7_SOT363-6

    P
    + DMN66D0LDW-7_SOT363-6

    3
    7 1 6 1 D

    P
    S
    BATT_VREF 6 O B 4 5

    1000P_0402_50V7K
    - Y

    G
    2 G
    FAST_COMP_OUT A

    G
    4
    1
    PC403
    PR406 PU401 S

    4
    G
    76.8K_0402_1% M74VHC1GT00DFT2G_SC70-5

    2
    2

    1
    PC404
    +3VALW 0.47U_0603_16V7K

    2
    PC405
    .1U_0402_16V7K
    1 2
    C C

    5
    PU404_Main source
    1 PR407

    P
    PQ409A open at 3/5V_B+ below 5.73V 4 B 22.1K_0402_1%
    Y
    and 3/5V_B+ recover 6.05V PA409A close A
    2 1 2

    G
    PU402

    3
    PU404_2nd_source +3VALW +3VALW M74VHC1GT00DFT2G_SC70-5
    B+
    PQ409A open at 3/5V_B+ below 5.72V
    PR408
    and 3/5V_B+ recover 6.05V PA409A close 1M_0402_1%
    232K_0402_1%

    10K_0402_1%
    48.7K_0402_1%
    1 2
    1

    1
    PU404_3rd_source
    PR409

    PR410

    PR411
    PQ409A open at 3/5V_B+ below 5.73V +3VALW
    and 3/5V_B+ recover 6.04V PA409A close
    2

    2
    LM393DMR2G_MICRO8

    8
    PU400A
    3

    P
    + 1
    BATT_VREF 2 O
    -

    G
    1U_0603_10V6K SLOW_COMP_OUT
    4
    76.8K_0402_1%

    42.2K_0402_1%
    0.1U_0402_25V6

    B B
    1

    PC407
    1

    1
    PR412

    PR413
    PC406

    2
    2

    Component(37.1)

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P47-PWR_BATT low voltage detect
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 47 of 59
    5 4 3 2 1
    5 4 3 2 1

    @ PJP500
    JUMP_43X118
    1 2
    EMC PL500 PU500 @ PR500 PC504 +3VALWP 1 2 +3VALW
    HCB2012KF-121T50_0805 SY8286BRAC_QFN20_3X3 0_0603_5% 0.1U_0603_25V7K
    1 2 B+_3V BST_3V 1 2 1 2
    B+

    2200P_0402_50V7K

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    3VALWP

    1
    EMC PC500

    EMC PC501

    PC502

    PC503
    TDC 5.2A

    IN

    IN

    IN

    IN

    BS
    D D

    2
    LX_3V 6
    LX LX
    20 PL501 Peak Current 7.5A
    1.5UH_TMPC0518HP-1R5MG-D_6A_20%
    7 19 LX_3V 1 2 OCP Current 8.0A (fix)
    GND LX +3VALWP
    8 18 5 X 5 X 1.8
    GND GND

    4.7_1206_5%

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1

    1
    9 17

    EMC PR501
    PG LDO +3VLP

    PC505

    PC506

    PC507

    PC508

    PC526
    1
    10 16
    Non AR

    2
    NC NC PC509

    OUT
    EN2

    EN1
    21 3VALWP

    NC
    4.7U_0603_6.3V6M

    FF

    3V_SN 2
    GND
    PR502 3.3V LDO 150mA~300mA TDC 5.5A

    11

    12

    13

    14

    15
    100K_0402_5%
    +3VALWP
    1 2 Peak Current 7.5A
    Vout is 3.37V

    680P_0603_50V7K
    OCP Current 8.0A (fix)

    ENLDO_3V5V

    1
    EMC PC510
    Fsw=600KHz
    <44> ALW _PW RGD_3V_5V

    2
    Check pull up resistor of
    C @ PR503 PC511 PR504 C
    SPOK at HW side 0_0402_5% 1000P_0402_25V8J 1K_0402_5%
    1 2 3V_FB 1 2 1 2
    <37,48> ALW ON

    @ PJP501
    JUMP_43X118
    1 2
    +5VALWP 1 2 +5VALW

    @ PR512 @ PR505 PC512


    0_0805_5% PU501 0_0603_5% 0.1U_0603_25V7K
    1 2 B+_5V SY8288CRAC_QFN20_3X3 BST_5V 1 2 1 2 5VALWP
    B+ TDC 7.9A
    @ PR513
    0_0805_5% Peak Current 11.0A
    2200P_0402_50V7K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6

    1 2
    OCP Current 13.0A
    1

    1
    EMC PC513

    EMC PC514

    PC515

    PC516

    PC528

    PC529

    IN

    IN

    IN

    IN

    BS
    2

    LX_5V 6 20 PL504
    LX LX 1.5UH_PCMC063T-1R5MN_9A_20%
    7 19 LX_5V 1 2
    B
    GND LX +5VALWP B
    8 18 7 X 7 X 3
    GND GND PC517

    4.7_1206_5%

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1

    1
    ALW _PW RGD_3V_5V 1 2 9 17 1 2

    EMC PR507
    PG VCC

    PC518

    PC519

    PC520

    PC521

    PC522

    PC527
    @ PR506 10 16

    2
    0_0402_5% NC NC 4.7U_0603_6.3V6M
    OUT

    LDO
    EN2

    EN1

    PR508 21
    FF

    5V_SN 2
    499K_0402_1% GND
    1 2 ENLDO_3V5V
    B+
    11

    12

    13

    14

    15

    VL
    5V LDO 150mA~300mA Vout 5.1V

    680P_0603_50V7K
    1

    ENLDO_3V5V

    EMC PC524
    PC523
    Fsw=600KHz

    1
    PR509 4.7U_0603_6.3V6M
    499K_0402_1%
    2
    2

    @ PR510 PC525 PR511 2


    0_0402_5% 1000P_0402_25V8J 1K_0402_5%
    1 2 5V_FB 1 2 1 2
    <37,48> ALW ON

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    3V/5V controller(35.1), Support component(35.2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P48-PWR_+3VALW_+5VALW
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 48 of 59
    5 4 3 2 1
    5 4 3 2 1

    @ PR600
    100K_0402_5%
    B+ PL600
    HCB2012KF-121T50_0805
    1 2
    +3VS
    1 2 @ PR601
    100K_0402_5%

    10U_0603_25V6M

    10U_0603_25V6M

    0.1U_0402_25V6
    EMCPC602

    2200P_0402_25V7K
    EMCPC603
    1 2
    +3VS

    1
    PU600
    D D

    PC600

    PC601
    +3VALW 10 19 1.2V_DDR_OT EMCPR602 EMC PC604

    2
    IN OT 4.7_0603_5% 680P_0402_50V7K
    13
    BYP PG
    18 1.2V_DDR_PG 1 2 1 2
    +1.2V_DDRP

    1U_0402_6.3V6K
    PC605 .1U_0402_16V7K
    14 12 1 2 PL601
    VCC BS

    PC606
    TMPC0512HP-1R0MG-D_5A_20%

    1
    2.2U_0402_6.3V6M
    PC607
    4 11 LX_DDR 1 2
    VTTGND LX
    +3VALW 5 X 5 X 1.2

    330P_0402_50V7K
    9 16

    2
    PGND FB

    1
    100K_0402_1%
    1

    PC609

    PR603
    15 8 +1.2V_DDRP PC608
    SGND VDDQSNS

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    22U_0603_6.3V6M
    1
    7 1 2
    R1

    2
    VLDOIN

    1
    PC610

    PC611

    PC612

    PC613
    @ PR604
    @PR604

    2
    0_0402_5% ILMT_DDR 17 6
    ILMT VTT +0.6VSP

    2
    1 5
    2

    S5 VTTSNS

    1
    100K_0402_1%
    ILMT_DDR

    PR605
    2 3
    S3 VTTREF

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    R2
    1

    1
    1U_0402_10V6K
    PC614

    PC615

    PC616
    @ PR606
    @PR606 SY8210AQVC_QFN19_4X3

    EN_1.2V

    2
    0_0402_5%

    2
    C C

    EN_0.6V
    2

    The current limit is set to 8A, 12A or 16A when VFB=0.6V


    this pin is pull low, floating or pull high
    +1.2V_DDR OCP set 8A @PR607
    @ PR607
    Vout=0.6V* (1+R1/R2)
    0_0402_5%
    1 2
    Vout=1.2V
    <34,36,51,52> SUS_ON_P
    0.1U_0402_10V7K

    Fsw=600KHz
    1

    1
    1M_0402_1%

    @ PC617
    PR608

    2
    2

    @PR609
    @ PR609
    0_0402_5%
    1 2
    <8> SM_PG_CTRL +1.2V_DDRP +1.2V_DDR +0.6VSP +0.6VS
    0.1U_0402_10V7K

    B B
    1
    1M_0402_1%

    @ PJP600 @ PJP601
    1
    PR610

    @PC618
    @

    @ PR611 JUMP_43X118 JUMP_43X39


    0_0402_5%
    PC618

    1 2 1 2
    1 2 1 2 1 2
    <33,34,36,52> RUN_ON_P
    2
    2

    +1.2V_DDR 0.6Volt +/- 5%


    TDC 4.1A TDC 0.4A
    Mode S3 S5 VOUT VTT
    Normal H H on on Peak Current 5.8A Peak Current 0.6A
    Stadby L H on off OCP Current 8A OCP Current 2A (fix)
    Shutdown L L off off

    Note: S3 - sleep ; S5 - power off


    DDR controller(35.3), Support component(35.4)

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P49-PWR_+1.2V_DDR/0.6VS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 49 of 59
    5 4 3 2 1
    5 4 3 2 1

    D D
    +1.0VA
    PR700
    75K_0402_1%
    TDC 2.6A
    1 2
    SIO_SLP_SUS# <12,33,36,37,51,56> Peak Current 3.3A
    EN pin don't floating OCP current 6.0A

    1
    If have pull down resistor at HW side, pls delete PR501 PR701 PC700
    1M_0402_1% 0.22U_0402_10V6K

    2
    2
    @ PJP700
    JUMP_43X79
    +1.0VAP 1
    1 2
    2 +1.0VA
    EMCPR702 EMCPC701
    4.7_0603_5% 680P_0402_50V7K
    EMC PL700 1 2SNB_1.0V 1 2
    HCB2012KF-121T50_0805 PU700
    B+ 1 2 B+_1.0V 8
    IN EN
    1 @ PR703 PC703
    0_0603_5% 0.1U_0603_25V7K
    10U_0805_25V6K

    10U_0805_25V6K
    6 BST_1.0V 1 2 1 2 PL701
    2200P_0402_50V7K

    0.1U_0402_25V6

    BS
    1

    C 1 C
    EMC PC702

    PC704

    @ PC705

    PC706
    1UH_6.6A_20%_5X5X3_M
    9
    GND LX
    10 LX_1.0V 1 2 +1.0VAP
    2

    24.9K_0402_1%

    22P_0402_50V8J

    22U_0805_6.3VAM

    22U_0805_6.3VAM

    22U_0805_6.3VAM

    22U_0805_6.3VAM
    EMC

    1
    FB = 0.6V

    1
    4

    PR704

    PC707
    FB

    PC708

    PC709

    PC710

    PC711
    PR705 ILMT_1.0V 3 7
    R1
    +3VALW

    2
    10K_0402_5% ILMT BYP

    4.7U_0603_6.3V6K

    2
    +3VALW 1 2 1.0VA_PG 2 5

    4.7U_0603_6.3V6K
    PG LDO

    PC713
    1

    PC712
    SYX196DQNC_QFN10_3X3

    35.7K_0402_1%
    2

    PR707
    R2
    +3VALW

    2
    Pin 7 BYP is for CS.
    Common NB can delete +3VALW and PC514
    1

    B B
    @ PR708 VFB=0.6V
    0_0402_5%
    Vout=0.6V* (1+R1/R2)
    2

    ILMT_1.0V
    Vout=1.02V
    1

    @ PR709
    Fsw=800KHz
    0_0402_5%
    2

    The current limit is set to 6A, 8A or 12A when this pin


    is pull low, floating or pull high.
    OCP setting 6A

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    1.05V controller(35.5), Support component(35.6) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P50-PWR_+1.0VA
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 50 of 59
    5 4 3 2 1
    A B C D

    1 1

    @ PR800

    <34,36,49,52> SUS_ON_P
    0_0402_5%
    1 2 +1.8VAP
    @ PR801
    0_0402_5%
    1 2
    <12,33,36,37,50,56> SIO_SLP_SUS#

    0.1U_0402_25V6

    EN_1.8VA
    1
    @ PC800

    2
    @PJP800
    @ PJP800
    B+=NVDC 2S 1 2
    +1.8VA
    +1.8VAP

    13

    14

    15

    16

    17
    1 2
    JUMP_43X39

    EN

    PGND

    PGND
    VOS

    TP
    EMC PL800 PL801
    HCB1608KF-121T30_0603 2.2UH_1239AS-H-2R2N-P2_1.3A_30%
    +1.8VAP
    2 2
    1 2 12 1 1 2
    B+ PVIN SW
    SW_1.8VA

    412K_0402_1%

    22U_0805_6.3VAM
    1

    22P_0402_50V8J
    1

    1
    10U_0805_25V6K

    PR802
    11 2
    2200P_0402_50V7K

    PVIN SW
    0.1U_0402_25V6

    PC801

    PC802
    Rup
    1

    1
    PC803

    PC805

    PU800
    PC804

    2
    TLV62150RGTR_QFN16_3X3

    2
    10 3
    2

    AVIN SW
    EMC

    EMC

    1
    +1.8VA

    1
    SS_1.8VA 9 4 1.8VA_PWROK PR803
    SS/TR PG Rdown
    3300P_0402_50V7-K

    4.7_0603_5% TDC 0.4A

    1SNUB_1.8VA
    100K_0402_5%
    EMC PR804
    1

    1
    Peak Current 0.6A

    AGND
    324K_0402_1%

    FSW
    PC806

    DEF

    2
    @ PR805
    FB
    OCP setting 1.4A(Fix)

    2
    2

    5
    PC807

    2
    680P_0402_50V7K
    EMC VFB=0.8V

    2
    1
    0_0402_5%

    FB_1.8VA
    @ PR806

    3 Fsw=1.25MHz @ Fsw net to 3V Vout=0.8V* (1+Rup/Rdown) 3

    Css=Tss*(2.5uA/1.25V) (F) +3VS Vout=1.817V


    Tss=1.65mS
    2

    Fsw=1.25MHz
    +1.8VAP

    1.8VS controller(35.15), Support component(35.16)

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P51-PWR_+1.8VS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 51 of 59
    A B C D
    A B C D

    1 1

    @ PR900

    <34,36,49,51> SUS_ON_P
    0_0402_5%
    1 2 +1.8VUP
    @ PR901
    0_0402_5%
    1 2
    <33,34,36,49> RUN_ON_P

    0.1U_0402_25V6

    EN_1.8VU
    1
    @ PC900

    2
    @ PJP900
    B+=NVDC 2S +1.8VUP 1 2
    +1.8VU

    13

    14

    15

    16

    17
    1 2
    2
    JUMP_43X39 2

    EN

    VOS

    PGND

    PGND

    TP
    EMC PL900 PL901
    HCB1608KF-121T30_0603 2.2UH_1239AS-H-2R2N-P2_1.3A_30%

    B+ 1 2 12
    PVIN SW
    1 SW _1.8VU 1 2
    +1.8VUP

    412K_0402_1%

    22U_0805_6.3VAM
    1

    22P_0402_50V8J
    1

    1
    10U_0805_25V6K
    2200P_0402_50V7K

    11 2

    PR902
    PVIN SW
    0.1U_0402_25V6

    PC901

    PC902
    Rup
    1

    1
    PC903

    PC905

    PU900
    PC904

    2
    TLV62150RGTR_QFN16_3X3

    2
    10 3
    2

    AVIN SW

    +1.8VU
    EMC

    EMC

    1
    SS_1.8VU 9
    SS/TR PG
    4 1.8VU_PW ROK PR903
    4.7_0805_5%
    Rdown TDC 0.46A
    3300P_0402_50V7-K

    1SNUB_1.8VU
    1
    EMC PR904 Peak Current 0.66A

    100K_0402_5%
    1

    AGND
    324K_0402_1%

    FSW
    OCP setting 1.4A(Fix)

    DEF

    2
    PC906

    @ PR905
    FB

    2
    2

    2
    PC907
    680P_0402_50V7K
    EMC VFB=0.8V

    2
    1
    0_0402_5%

    FB_1.8VU
    @ PR906
    Fsw=1.25MHz @ Fsw net to 3V Vout=0.8V* (1+Rup/Rdown)
    Css=Tss*(2.5uA/1.25V) (F) +3VS Vout=1.817V
    Tss=1.65mS
    2

    3
    Fsw=1.25MHz 3

    +1.8VUP

    1.8VU controller(35.17), Support component(35.18)

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P52-PWR_+1.8VU
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 52 of 59
    A B C D
    5 4 3 2 1

    Local sense put on HW site


    +1.0V_VCCST

    @PR1080
    @ PR1080

    0.1U_0402_25V6
    1

    PC1004
    45.3_0402_1%
    0_0402_5%

    75_0402_1%

    100_0402_1%
    PR1074
    1 2

    PR1084

    @ PR1063
    +5VALW VCC_SA

    2
    @ PR1125
    @PR1066
    @ PR1066
    0_0402_5%
    TDC 5A

    2
    0_0402_5% 1 2 CPU_B+ Peak Current 5A SA_B+ B+ CPU_B+ B+
    1 2 1 2

    0.22U_0603_25V7K
    1U_0603_10V6K
    <16> VIDSCLK PR1070 49.9_0402_1% OCP current 6A

    1
    D 1 2 1 2 EMC PL1004 @ PJP1002 D
    Choke DCR 13 m ohm

    PC1007

    PC1005
    <16> VIDALERT_N @PR1024
    @ PR1024 0_0402_5% @PR1076
    @ PR1076 0_0402_5% HCB2012KF-121T50_0805 PAD-OPEN 4x4m
    1 2 1 2 1 2 1 2

    2
    <16> VIDSOUT

    100U_D_20VM_R55M

    100U_D_20VM_R55M
    @PR1025
    @ PR1025 0_0402_5% PR1028 10_0402_1%

    0.1U_0402_25V6K~D
    PC1079 EMC

    PC1076 EMC
    10U_0805_25V6K

    10U_0805_25V6K

    2200P_0402_50V7K
    <13,37,46,47> H_PROCHOT# 1 1
    PR1124 100_0402_1%

    1
    + +

    PC1066

    PC1093

    PC1073

    PC1135
    1 2 1 2

    PC1006 47P_0402_50V8J~D PR1095 1.91K_0402_1% U23@ PR1094

    2
    1 2 100K_0402_1% 2 2
    +3VS 1 2
    @PR1027
    @ PR1027 0_0402_5%
    1 2
    <12> PCH_PWROK
    PR1121
    @PR1029
    @ PR1029 0_0402_5% 48.7K_0402_1%
    PH1007 PR1072 PR1099 1 2 1 2 1 2
    <36,57> IMVP_VR_ON_P
    470K_0402_5%_ TSM0B474J4702RE 10K_0402_1% 86.6K_0402_1% PR1082 2.2_0603_5%
    1 2 1 2 1 2
    PU1305 PQ1302
    1 2 PC1131 ISL95808HRZ-TS2378_DFN8_2X2 AON7934_DFN3X3A8-10

    1
    PR1067 330P_0402_50V8J
    27.4K_0402_1% 1 2 PC1082 1 8 @ PR1059
    @PR1059

    41

    40

    39

    38

    37

    36

    35

    34

    33

    32

    31

    D1

    D1

    D1

    G1
    0.22U_0603_16V7K UGATE PHASE 0_0402_5% PL1005
    1 2 2 7 1 2 FCCM_VSA 1UH_6.6A_20%_5X5X3_M

    VR_ENABLE

    VR_READY

    VR_HOT#

    SCLK

    ALERT#

    SDA

    PROG1

    PROG2
    PAD

    VCC

    VIN
    PC1020 PR1122 BOOT FCCM 10
    D1 D2/S1
    9 1 2 +VCC_SA
    2200P_0402_50V7K 3.92K_0402_1% PWM_VSA 3 6
    1 2 1 2 @ PR1083 PWM VCC +5VS
    0_0402_5% 30 PWM_VSA 4 5

    G2
    S2

    S2

    S2
    PWM_C GND LGATE

    1
    1 2 1

    4.7_1206_5%
    PC1021

    TP
    <37,46> P_SYS PSYS 29

    EMC PR1086
    68P_0402_50V8J FCCM_VSA PR1136 PR1137

    8
    1 2 2 FCCM_C

    1U_0402_10V6K
    0_0402_5% 0_0402_5%

    9
    PC1014 PR1098 IMON_B 28
    ISUMN_C @ @

    1
    220P_0402_50V7K 1K_0402_1% 3

    PC1097

    SA_SNUB 2

    2
    1 2 1 2 NTC_B 27
    <17> VCC_GT_SENSE 4 ISUMP_C

    2
    COMP_B





    26

    3.65K_0603_1%
    @ PC1098 U23@ PR1093
    RTN_C

    1
    330P_0402_50V7K 1 2 5 PU1000
    1 2 FB_B 25

    PR1091
    FB_VSA

    680P_0603_50V7K
    2.49K_0402_1% ISL95859HRTZ-T_TQFN40_5X5
    6 FB_C
    0.082U_0402_16V7K

    C C
    RTN_B 24
    @ PC1022

    COMP_VSA
    COMP_C
    1

    EMC PC1086
    PC1095 PR1065 7

    ISUMP_VSA 2
    680P_0402_50V7K 2K_0402_1% ISUMP_B 23 IMON_VSA

    ISUMN_VSA
    PC1019 1 2 1 2 8 IMON_C
    2

    2
    0.01U_0402_50V7K ISUMN_B 22
    1 2 9 PWM_A PWM_IA <54>
    ISEN1_B 21
    10 FCCM_A FCCM_IA <54>

    ISUMN_A
    ISUMP_A
    PWM1_B

    PWM2_B

    COMP_A
    ISEN2_B

    FCCM_B

    IMON_A

    NTC_A

    RTN_A
    FB_A
    <17> VSS_GT_SENSE

    <54> ISUMP_GT

    11

    12

    13

    14

    15

    16

    17

    18

    19

    20
    1

    IMON_IA

    FB_IA
    <54> FCCM_GT

    NTC_IA

    COMP_IA
    <54> PWM1_GT
    U23@ PR1088 <54> PWM2_GT
    U23@ PC1085

    2.61K_0402_1% PC1065
    0.033U_0402_16V7K
    1

    U23@ PC1094
    11K_0402_1%

    330P_0402_50V7K
    0.1U_0402_25V6
    2

    1 2
    PR1062

    ISUMP_VSA

    7.32K_0402_1%
    1
    PR1090
    PR1071 80.6K_0402_1%
    2

    PR1087 PC1088 1 2 1 2

    2.61K_0402_1%
    2
    1

    1
    1K_0402_1% 2200P_0402_50V7K
    1 2 1 2

    2200P_0402_50V7K

    10P_0402_50V8J
    PH1005 PR1075

    PR1089
    2
    10K_0402_5%_B25/50 4250K PH1008 1.33K_0402_1%

    1
    PC1081
    U23@ PR1061 470K_0402_5%_ TSM0B474J4702RE

    10K_0402_5%_B25/50 4250K
    1 2 1 2

    2200P_0402_25V7K
    475_0402_1%

    0.047U_0402_25V7K
    2

    2
    1

    1
    1 2 1 2 1 2

    348_0402_1%

    11K_0402_1%
    2
    <54> ISUMN_GT

    1
    PC1069

    PR1085

    PC1089

    PR1058
    PR1064

    0.1U_0402_25V6
    1

    @ PC1078
    1 2 10K_0402_1% PC1068 PR1092

    PC1071
    U23@ PC1070 PR1126 2200P_0402_25V7K 1K_0402_1%

    1
    0.022U_0402_16V7K 27.4K_0402_1%

    PH1006
    1 2 ISEN1_GT

    1K_0402_1%
    PC1064 PR1123
    U23@ PC1133 2200P_0402_50V7K 5.49K_0402_1% 1 2 1 2

    1
    0.022U_0402_16V7K

    PR1068
    1 2 1 2

    2
    B B
    1 2 ISEN2_GT PR1073 PC1072
    PC1056 316_0402_1% 2200P_0402_25V7K
    .1U_0402_16V7K
    1

    68P_0402_50V8J ISUMN_VSA
    PC1084

    1 2 1 2

    330P_0402_50V7K
    PC1087
    2

    U23@ PR1069

    680P_0402_50V7K 2K_0402_1%
    84.5K_0402_1%
    PR1077 .1U_0402_16V7K

    1
    PC1080
    1.69K_0402_1% 1 2
    <54> ISEN1_GT

    PR1060
    PC1090 PR1081
    1

    1500P_0402_50V7K 316_0402_1% PC1067


    <54> ISEN2_GT 1 2 1 2
    U22@ U22@ 0.033U_0402_16V7K

    2
    PR1127 PR1128 1 2

    2
    0_0402_5% 0_0402_5%

    .1U_0402_16V7K
    1 2
    2

    1
    VSA_SEN- <18>

    PC1083

    PC1134
    680P_0402_50V7K 2K_0402_1%

    PR1079
    1

    1.37K_0402_1% PC1075 PC1074


    +5VALW

    2
    PR1096

    0.047U_0402_25V7K 0.01U_0402_50V7K
    1 2 1 2

    0.082U_0402_16V7K
    2

    @PC1077
    PC1077

    1
    PR1093 U22@ PR1088 U22@ PC1094 U22@ PC1085 U22@
    @ PC1091
    1

    PC1096

    2
    330P_0402_50V7K

    @
    PR1078
    11K_0402_1% 1 2
    <16> VCCSENSE
    2

    1 2
    SD034196180 SD000004J80 SE00000MJ00 SE00000MJ00
    1.96K_0402_1% 4.42K_0402_1% 0.047U_0402_25V7K 0.047U_0402_25V7K @ PC1132
    @PC1132
    330P_0402_50V7K PR1097 PH1009
    PR1061 U22@ 1 2 4.42K_0402_1% 10K_0402_5%_B25/50 4250K VSA_SEN+ <18>
    1 2 1 2
    0.082U_0402_16V7K
    @ PC1092

    U23 U22
    1

    PC1099
    PR1093 2.49K 1.96K ISUMN_IA <54>
    2

    SD034374080 0.01U_0402_50V7K
    374_0402_1% 1 2
    A PR1088 2.61K 4.42K PR1069 U22@
    ISUMP_IA <54> A

    PC1094 0.1U 0.047U


    <16> VSSSENSE

    PC1085 0.033U 0.047U SD034124380 Local sense put on HW site


    124K_0402_1%
    PR1061 475 374 PR1094 U22@

    PR1069 84.5K 124K


    Security Classification Compal Secret Data Compal Electronics, Inc.
    VCC_CORE controller(36.1), Drivers (36.2), Support component(36.3) Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    PR1094 100K 78.7K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P53-PWR_+VCC_SA_ISL95857
    SD034787280 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    78.7K_0402_1% 0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 53 of 59
    5 4 3 2 1
    5 4 3 2 1

    CPU_B+

    2200P_0402_50V7K
    0.1U_0402_25V6K~D
    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    1

    1
    PC1100

    PC1101

    PC1102

    EMC PC1103

    EMC PC1104

    PC1105
    D VCC_core D
    TDC 21A
    2

    2
    Peak Current 29A
    OCP current 34A
    Choke DCR 0.9 +-7%m ohm
    VCC_GT (U-line 22)
    TDC 18A
    PU1100 Peak Current 31A
    CSD97374CQ4M_SON8_3P5X4P5 PL1100
    9 0.15UH_MMD06CZER15MG_37A_20% OCP current 37A
    PC11068 PGND2 CPU_B+
    <53> PWM_IA 1 27 PW M 4 CORE_SW 1 2 Choke DCR 0.9 +-7%m ohm
    0.22U_0603_16V7K
    BOOT VSW 3
    PGND1 2
    +VCC_CORE
    1 2 6
    BOOT_R VDD

    2200P_0402_50V7K
    PR1100 5 1

    0.1U_0402_25V6K~D
    VIN SKIP#

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    2.2_0603_5%
    VCC_GT (U-line 23e) VCC_GTx

    1
    +5VS

    1
    TDC 32A TDC 5A

    PC1107

    PC1108

    PC1109

    EMC PC1112

    EMC PC1111
    1

    1
    1000P_0402_50V7K

    1U_0402_10V6K
    5.11K_0402_1%

    EMCPR1101
    10P_0402_50V8J

    Peak Current 57A Peak Current 7A


    1

    1
    0_0402_5%
    @ PR1103

    10_1206_1% PR1130 PR1131

    2
    1

    1
    PR1104

    PC1113

    PC1110

    PC1114 0_0402_5% 0_0402_5%


    OCP current 74A

    2
    @ @

    CORE_SNUB
    Choke DCR 0.9 +-7%m ohm
    2

    2
    2





    C C

    3.65K_0603_1%
    1

    PR1102
    <53> FCCM_IA

    1
    EMC PC1115
    47P_0603_50V8J

    2
    U23@ PU1101
    CSD97374CQ4M_SON8_3P5X4P5 U23@ PL1101
    9 0.15UH_MMD06CZER15MG_37A_20%
    U23@ PC11168 PGND2
    <53> PWM2_GT 1 27 PW M 4 1 2
    GT_SW2
    0.22U_0603_16V7K
    BOOT VSW 3
    PGND1 2
    +VCC_GT
    <53> ISUMP_IA <53> ISUMN_IA 1 2 6
    U23@ PR1105 5 BOOT_R VDD 1
    VIN SKIP#

    1
    2.2_0603_5% U23@
    PR1106 EMC PR1132 PR1133
    CPU_B+ +5VS 10_1206_1% 0_0402_5% 0_0402_5%

    1000P_0402_50V7K
    10P_0402_50V8J
    @ @

    1
    0_0402_5%
    U23@ PR1110

    1U_0402_10V6K
    5.11K_0402_1%

    GT_SNUB2 2

    2
    1

    1
    U23@ PR1108

    U23@ PC1117

    U23@ PC1118

    U23@ PC1119
    2200P_0402_50V7K
    0.1U_0402_25V6K~D





    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    GT2P
    2

    2
    1

    1
    PC1120

    PC1121

    PC1122

    EMC PC1123

    EMC PC1124

    GT2N

    1
    U23@
    U23@ PR1111 U23@ PR1109 PR1107
    2

    3.65K_0603_1% 100K_0402_1% 10_0402_1%


    <53,54> FCCM_GT U23@ 1 2 1 2

    1
    EMC PC1125

    2
    B 47P_0603_50V8J B
    <53> ISEN2_GT

    2
    GT1N 1 2

    @ PR1112
    100K_0402_1%

    PU1102 <53,54> ISUMP_GT <53,54> ISUMN_GT


    CSD97374CQ4M_SON8_3P5X4P5 PL1102
    9 0.15UH_MMD06CZER15MG_37A_20%
    PC1126 8 PGND2
    <53> PWM1_GT 1 2 7 PW M 4 1 2
    GT_SW1
    0.22U_0603_16V7K
    BOOT VSW 3
    PGND1 2
    +VCC_GT
    1 2 6
    PR1113 5 BOOT_R VDD 1
    VIN SKIP#
    1

    2.2_0603_5%
    PR1114 PR1134 PR1135
    +5VS 10_1206_1% 0_0402_5% 0_0402_5%
    1000P_0402_50V7K
    10P_0402_50V8J
    5.11K_0402_1%

    EMC @ @
    1

    1
    0_0402_5%
    PC1127

    @ PR1119

    1U_0402_10V6K

    2
    1

    1
    PR1117

    PC1128

    PC1129

    GT_SNUB1

    GT1P

    GT1N
    2

    1
    2

    PR1116 U23@ PR1118 PR1115


    3.65K_0603_1% 100K_0402_1% 10_0402_1%
    1 2 1 2
    2
    1

    EMC PC1130 <53> ISEN1_GT


    A 47P_0603_50V8J A
    <53,54> FCCM_GT
    VCC_CORE controller(36.1), Drivers (36.2), Support component(36.3)
    2

    GT2N 2 1

    @ PR1120
    100K_0402_1%

    ISUMP_GT <53,54> <53,54> ISUMN_GT Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P54-PWR_+VCC_CORE/GT
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 54 of 59
    5 4 3 2 1
    A
    B
    C
    D
    +VCC_CORE

    2
    1
    +
    330_B2_2.5VM_R9M 2 1 2 1

    5
    5

    2
    PC1308 1
    PC1288 PC1259 PC1200
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
    2 1 2 1

    2
    1
    2
    1
    2
    1

    +
    330_B2_2.5VM_R9M
    PC1289 PC1260 PC1230 PC1201
    PC1309
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    TOP Side.

    2 1 2 1

    2
    1
    2
    1
    Bottom Side.

    PC1290 PC1261 PC1231 PC1202


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1

    2
    1
    2
    1

    PC1291 PC1262 PC1232 PC1203


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1

    2
    1
    2
    1

    PC1292 PC1263 PC1233 PC1204


    VCC_CORE Place on CPU

    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M


    2 1 2 1 2
    1
    2
    1

    PC1293 PC1264 PC1234 PC1205


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    2
    1
    2
    1

    PC1294 PC1265 PC1235 PC1206


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    2
    1
    2
    1
    22U_0603 * 26 pcs +1U_0201*33 pcs

    PC1295 PC1266 PC1236 PC1207


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    2
    1
    2
    1

    PC1296 PC1267 PC1237 PC1208


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    2
    1
    2
    1

    4
    4

    PC1297 PC1268 PC1238 PC1209


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    2
    1
    2
    1
    330u_D2*2 pcs + 22U_0603 * 7 pcs + 1U_0201 *2

    PC1298 PC1269 PC1239 PC1210


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    2
    1
    2
    1

    PC1299 PC1270 PC1240 PC1211


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    2
    1
    2
    1

    PC1300 PC1271 PC1241 PC1212


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1

    TOP Side.
    2
    1
    2
    1

    PC1301 PC1272 PC1242 PC1213


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

    Bottom Side.
    2 1 2 1
    2
    1
    2
    1

    VCC_CORE output cap(36.4), VCC_GT output cap(36.5), VCC_SA output cap(36.6)


    PC1302 PC1273 PC1243 PC1214
    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

    22U_0603 * 2 pcs
    2 1 2 1
    2
    1
    2
    1

    PC1303 PC1274 PC1244 PC1215

    VCC_SA Place on CPU


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    2
    1
    2
    1

    PC1304 PC1275 PC1245 PC1216


    1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1

    PC1305
    1U_0201_6.3V6M

    3
    3

    22U_0603 * 10 pcs + 1U_0201*7 pcs

    Issued Date
    Security Classification
    +VCC_SA
    +VCC_GT

    2 1
    2
    1
    2
    1
    2
    1

    2 1

    2014/10/17
    2
    1

    330_B2_2.5VM_R9M
    PC1276 PC1246 PC1217
    PC1306
    PC1322 PC1310 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    1U_0201_6.3V6M 22U_0603_6.3V6M 2 1
    2
    1
    2
    1
    2
    1

    2 1
    2
    1

    330_B2_2.5VM_R9M
    PC1307 PC1277 PC1247 PC1218
    PC1323 PC1311 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    1U_0201_6.3V6M 22U_0603_6.3V6M 2 1
    2
    1
    2
    1
    2
    1

    2 1
    2
    1

    330_B2_2.5VM_R9M
    PC1278 PC1248 PC1219
    TOP Side.

    @ PC1329
    PC1324 PC1312 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    1U_0201_6.3V6M 22U_0603_6.3V6M 2 1
    2
    1
    2
    1
    2
    1

    2 1
    Bottom Side.

    2
    1

    330_B2_2.5VM_R9M
    PC1279 PC1249 PC1220
    330u_B2*4 pcs

    @ PC1355
    PC1325 PC1313 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    1U_0201_6.3V6M 22U_0603_6.3V6M 2 1 2 1
    2
    1
    2
    1

    2 1
    Compal Secret Data
    2
    1

    10U_0603_6.3V6M
    PC1280 PC1250 PC1221
    Deciphered Date

    PC1344
    PC1326 PC1314 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    1U_0201_6.3V6M 22U_0603_6.3V6M 2 1 2 1
    VCC_GT Place on CPU

    2
    2

    2
    1
    2
    1

    2 1
    2
    1

    10U_0603_6.3V6M
    PC1281 PC1251 PC1222
    PC1345
    PC1327 PC1315 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    1U_0201_6.3V6M 22U_0603_6.3V6M 2 1 2 1
    2
    1
    2
    1

    2 1
    2
    1

    10U_0603_6.3V6M
    PC1282 PC1252 PC1223
    PC1346
    PC1328 PC1316 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    1U_0201_6.3V6M 22U_0603_6.3V6M 2 1 2 1
    2
    1
    2
    1

    2014/12/05
    2
    1

    10U_0603_6.3V6M
    PC1283 PC1253 PC1224
    PC1347
    PC1317 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    22U_0603_6.3V6M 2 1 2 1
    2
    1
    2
    1

    2
    1

    10U_0603_6.3V6M
    PC1284 PC1254 PC1225
    PC1348
    PC1318 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    22U_0603_6.3V6M 2 1 2 1
    2
    1
    2
    1

    2
    1

    10U_0603_6.3V6M
    PC1285 PC1255 PC1226
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

    PC1349
    PC1319 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    22U_0603_6.3V6M 2 1 2 1
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    2
    1
    2
    1

    Size
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Title

    Date:
    2
    1

    10U_0603_6.3V6M
    PC1286 PC1256 PC1227
    PC1350
    PC1320 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    22U_0603_6.3V6M 2 1 2 1
    2
    1
    2
    1

    2
    1

    10U_0603_6.3V6M
    PC1287 PC1257 PC1228
    PC1351
    PC1321 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    22U_0603_6.3V6M 2 1 2 1
    2
    1
    2
    1
    22U_0603 * 34 pcs +10U_0603*11 pcs +1U_0201*18 pcs

    Document Number

    10U_0603_6.3V6M
    PC1338 PC1258 PC1229
    PC1352
    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    LA-C881P
    2
    1
    2
    1

    10U_0603_6.3V6M
    PC1339 PC1334 PC1330
    Tuesday, October 13, 2015

    PC1353
    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1 2 1
    2
    1
    2
    1

    1
    1

    10U_0603_6.3V6M
    PC1340 PC1335 PC1331
    PC1354
    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1
    2
    1
    2
    1

    Sheet

    PC1341 PC1336 PC1332


    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 1
    2
    1
    2
    1

    55

    PC1342 PC1337 PC1333


    1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    Compal Electronics, Inc.

    of

    2 1

    PC1343
    59

    1U_0201_6.3V6M
    P55-PWR_CPU BACK SIDE MLCC
    Rev
    0.4
    A
    B
    C
    D
    5 4 3 2 1

    +3VALW

    1
    PR1423
    @ PR1400 10K_0402_1%
    0_0402_5%

    2
    1 2
    <12,28,34,56> SIO_SLP_S0#
    @ PR1401
    0_0402_5%
    <34> VCCSTG_EN 1 2

    0.1U_0402_25V6
    1
    D D

    EN_VCCIO
    1
    @ PC1400
    @ PR1402
    0_0402_5%

    2
    2

    13

    14

    15

    16

    17
    PU1400
    Vin=6~9V

    EN

    PGND

    PGND

    TP
    LPM
    PL1400
    HCB1608KF-121T30_0603

    B+ 1 2 VIN_VCCIO 12
    PVIN VOS
    1
    +1.0VS_VCCIOP
    +3VALW PL1401
    1UH_1277AS-H-1R0N-P2_3.3A_30%
    Vout=0.95V

    10U_0603_25V6M

    10U_0603_25V6M
    1

    1
    11 2 LX_VCCIO 1 2
    +1.0VS_VCCIOP

    PC1401

    PC1402
    PVIN SW

    3.2 * 2.5 *1.2

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    2

    2
    TPS62134ARGT_QFN16_3X3

    1
    1

    1
    10 3

    PC1403

    PC1404

    @ PC1405
    2200P_0402_50V7K
    AVIN SW

    0.1U_0402_25V6
    1

    1
    PC1408

    PC1409

    2
    2

    2
    1

    4.7_0603_5%
    1

    VID0_VCCIO 9 4

    PR1403
    2

    2
    VID0 PG
    PR1404 @ PR1405

    1SNUB_VCCIO
    AGND
    10K_0402_1% 10K_0402_1%

    VID1

    2
    FBS
    Fsw=1.2MHz

    SS
    2

    VID0_VCCIO

    100_0402_1%
    8

    1
    VID1_VCCIO @ PJP1400

    680P_0402_50V7K
    JUMP_43X79

    PC1410

    @ PR1408
    1 2
    +1.0VS_VCCIOP 1 2 +1.0VS_VCCIO
    1

    VID1_VCCIO

    SS_VCCIO

    2
    @ PR1406 PR1407
    10K_0402_1% 10K_0402_1%
    C C

    470P_0402_50V7K
    2

    @ PR1409

    1
    0_0402_5%
    1 2
    VCCIO

    PC1411
    VCCIO_SENSE <18>
    TDC 2.2A

    2
    @ PR1410
    0_0402_5%
    1 2
    Peak Current 3.1 A
    VSSIO_SENSE <18>
    OCP Current 4.2 A Fix by IC

    1
    @ PR1425
    MIN:3.6A
    100_0402_1% MAX:4.9A
    +3VALW Choke DCR 48.0mohm

    2
    1
    @ PJP1401
    JUMP_43X79
    PR1424 1 2
    @ PR1411 10K_0402_1% +1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE
    0_0402_5%

    2
    1 2
    <12,28,34,56> SIO_SLP_S0#
    PR1412
    130K_0402_1%
    1 2
    <12,33,36,37,50,51> SIO_SLP_SUS# PRIM_CORE
    EN_PRIM_COREP

    TDC 1.8A
    0.1U_0402_25V6
    1

    Peak Current 2.6 A


    PC1412

    @ PR1413
    0_0402_5%
    OCP Current 4.2 A Fix by IC
    2
    2

    MIN:3.6A
    13

    14

    15

    16

    17

    B Vin=6~9V PU1401 MAX:4.9A B


    EN

    PGND

    PGND

    TP
    LPM

    PL1402 Choke DCR 48.0mohm


    HCB1608KF-121T30_0603

    B+ 1 2 VIN_PRIM 12
    PVIN VOS
    1
    +1.0V_PRIM_COREP
    +3VALW PL1403
    1UH_1277AS-H-1R0N-P2_3.3A_30%
    Vout=1.0V
    10U_0603_25V6M

    10U_0603_25V6M
    1

    11 2 LX_PRIM 1 2
    +1.0V_PRIM_COREP
    PC1413

    PC1414

    PVIN SW

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    2

    TPS62134DRGT_QFN16_3X3

    1
    1

    1
    10 3

    PC1406

    PC1415

    @ PC1416
    2200P_0402_50V7K

    AVIN SW
    0.1U_0402_25V6

    Rup
    1

    1
    PC1417

    PC1418

    2
    2

    2
    4.7_0603_5%
    1

    9 4
    PR1416
    2

    VID0 PG
    PR1414 PR1415
    AGND

    1SNUB_PRIM

    10K_0402_1% 10K_0402_1%
    VID0_PRIM_CORE

    VID1

    FBS

    Fsw=1.2MHz
    SS
    2

    VID0_PRIM_CORE
    680P_0402_50V7K
    8

    VID1_PRIM_CORE
    PC1419
    1
    1

    VID1_PRIM_CORE

    2
    SS_PRIM

    @ PR1419
    @ PR1417 @ PR1418 0_0402_5%
    10K_0402_1% 10K_0402_1% 1 2
    <19> CORE_VID0
    470P_0402_50V7K
    2
    2

    @ PR1421
    1

    @ PR1420 0_0402_5%
    0_0402_5% 1 2
    PC1420

    1 2
    <19> CORE_VID1
    2

    @ PR1422
    A 100K_0402_1% A
    2

    +1.0VS_VCCIO controller(35.21), Support component(35.22)


    +1.0V_PRIM_CORE controller(35.23), Support component(35.24) Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P56-PWR_VCCIO/PRIM_CORE
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 56 of 59
    5 4 3 2 1
    5 4 3 2 1

    +3VALW

    1
    U23@ PR1522
    @ PR1500 10K_0402_1%
    0_0402_5%

    2
    <14,57> LPM_ZVM_N 1 2

    @ PR1501
    0_0402_5%
    1 2
    <36,53,57> IMVP_VR_ON_P

    EN_VCC_EDRAM
    0.1U_0402_25V6
    1

    1
    @ PC1500
    D D
    @ PR1502
    0_0402_5%

    2
    2

    13

    14

    15

    16

    17
    Vin=6~9V

    EN

    PGND

    PGND

    TP
    LPM
    U23@ PL1500

    B+ HCB1608KF-121T30_0603
    1 2 VIN_VCC_EDRAM 12
    PVIN VOS
    1 +VCC_EDRAM_P
    U23@ PL1501
    Vout=1.0V
    +3VALW 1UH_1277AS-H-1R0N-P2_3.3A_30%

    10U_0603_25V6M

    10U_0603_25V6M
    1

    1
    11 2 LX_VCC_EDRAM 1 2 +VCC_EDRAM_P

    U23@ PC1501

    U23@ PC1502
    PVIN SW
    U23@ PU1500

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    2

    2
    TPS62134CRGT_QFN16_3X3

    U23@ PC1503

    U23@ PC1504
    1

    1
    10 3

    @ PC1505
    2200P_0402_50V7K
    AVIN SW

    0.1U_0402_25V6
    1

    1
    U23@ PC1508

    U23@ PC1509

    U23@ PR1505

    2
    4.7_0603_5%
    1SNUB_VCC_EDRAM
    1
    VID0_EDRAM_VR 9 4

    2
    VID0 PG
    1

    AGND
    U23@ PR1503 @ PR1504

    VID1

    FBS
    10K_0402_1% 10K_0402_1%
    Fsw=1.2MHz

    SS

    2
    2

    VID0_EDRAM_VR

    680P_0402_50V7K
    8

    U23@ PC1510

    1
    VID1_EDRAM_VR

    1SS_VCC_EDRAM
    U23@ PR1506
    VID1_EDRAM_VR 100_0402_1%

    2
    1

    U23@ PR1528

    2
    @ PR1507 U23@ PR1508 0_0805_5%
    10K_0402_1% 10K_0402_1% 1 2

    470P_0402_50V7K
    @ PR1509 +VCC_EDRAM_P +VCC_EDRAM

    U23@ PC1511
    C C
    2

    0_0402_5%
    1 2
    VCC_EDRAM_SENSE <16>

    2
    @ PR1510
    0_0402_5%
    1 2
    +VCC_EDRAM
    VSS_EDRAM_SENSE <16>
    TDC 1.75A

    1
    U23@ PR1526
    Peak Current 2.5 A
    100_0402_1% OCP Current 4.2 A Fix by IC
    MIN:3.6A

    2
    +3VALW MAX:4.9A
    Choke DCR 48.0mohm

    1
    U23@ PR1523
    @ PR1511 10K_0402_1%
    0_0402_5% U23@ PR1529

    2
    1 2 0_0805_5%
    <14,57> LPM_ZVM_N
    1 2
    @ PR1512 +VCC_EOPIO_P +VCC_EOPIO
    EN_1.0V_PRIM_COREP

    0_0402_5%
    <36,53,57> IMVP_VR_ON_P 1 2
    0.1U_0402_25V6
    1

    1
    @ PC1512

    @ PR1513
    +VCC_EOPIO
    0_0402_5%
    TDC 1.4A
    2

    +1.0V_VCCSTG Peak Current 2.0 A


    2

    OCP Current 4.2 A Fix by IC


    13

    14

    15

    16

    17

    B B
    Vin=6~9V U23@ EMC MIN:3.6A
    EN

    PGND

    PGND

    TP
    LPM

    PL1502
    1

    HCB1608KF-121T30_0603 MAX:4.9A
    @ PR1525
    B+ 1 2 VIN_1V_PRIM 12
    PVIN VOS
    1 +VCC_EOPIO_P
    100K_0402_1% Choke DCR 48.0mohm
    U23@ PL1503
    1UH_1277AS-H-1R0N-P2_3.3A_30%
    Vout=1.0V
    10U_0603_25V6M

    10U_0603_25V6M
    2

    @ PR1524 11 2 LX_1V_PRIM 1 2 +VCC_EOPIO_P


    U23@ PC1513

    U23@ PC1514

    0_0402_5% PVIN SW
    1 2 MSM_N <14> U23@ PU1501

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    2

    TPS62134CRGT_QFN16_3X3

    U23@ PC1506

    U23@ PC1515
    1

    1
    10 3

    @ PC1516
    2200P_0402_50V7K

    AVIN SW
    U23@ PC1517

    U23@ PC1518
    0.1U_0402_25V6
    1

    2
    EMC

    U23@ PR1516
    EMC
    1

    VID0_EOPIO_VR 9 4
    4.7_0603_5%
    2

    VID0 PG
    1SNUB_1V_PRIM

    U23@ PR1514 @ PR1515


    AGND

    10K_0402_1% 10K_0402_1%
    VID1

    FBS

    Fsw=1.2MHz
    SS
    2

    VID0_EOPIO_VR

    U23@ PR1519
    8

    1
    VID1_EOPIO_VR

    100_0402_1%
    680P_0402_50V7K
    U23@ PC1519
    SS_1V_PRIM
    1

    VID1_EOPIO_VR
    2

    @ PR1517 U23@ PR1518


    10K_0402_1% 10K_0402_1%
    @ PR1520
    470P_0402_50V7K
    2

    0_0402_5%
    U23@ PC1520
    1

    1 2
    VCC_EOPIO_SENSE <16>
    @ PR1521
    2

    0_0402_5%
    1 2
    VSS_EOPIO_SENSE <16>
    A A
    1

    U23@ PR1527
    100_0402_1%

    +VCC_EDRAM controller(35.25), Support component(35.26)


    2

    +VCC_EOPIO controller(35.27), Support component(35.28)


    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P57-PWR_VCC_EDRAM/EOPIO
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 57 of 59
    5 4 3 2 1
    5 4 3 2 1

    Version Change List ( P. I. R. List ) Page 1


    Request
    Item Page# Title Date Issue Description Solution Description Rev.
    Owner
    1 P44 PQ206A 2015/09/15 Henry Chen PQ206A change to POP
    D D

    2 P44 PU201B 2015/09/15 Henry Chen PU201B change to NC

    3 P44 PD206 2015/09/15 Henry Chen PD206 change to NC

    4 P44 PR236, PR238 2015/09/15 Henry Chen PR236, PR238 change to NC

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P58-PWR_PIR-1
    Size
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Document Number Rev
    0.4
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 58 of 59
    5 4 3 2 1
    5 4 3 2 1

    [RTC in]
    Discrete Power On Sequence
    +RTCVCC
    tPCH01 < 9ms [AC in] [Battery only, AC absent]
    PCH_RTCRST#
    ITEM Measure Point Time ITEM Measure Point Time
    Ta +DC_IN To +3V_VC
    [AC in] [Battery only, AC absent]
    Tb +DC_IN To ACAV_IN
    +DC_IN Tc +DC_IN To B+
    Ta Td ACAV_IN To ALW ON
    +3V_VC
    B+ Te ALW ON To +3VALW Te ALW ON To +3VALW
    Tb
    ACAV_IN Tm Tf ALW ON To +5VALW Tf ALW ON To +5VALW
    +3V_VC EC pay attention timing
    Tc Tg +3VALW To ALW _PW RGD_3V_5V Tg +3VALW To ALW _PW RGD_3V_5V
    B+ Ti
    +3VLP Th ALW ON To PCH_DPW ROK Th ALW ON To PCH_DPW ROK
    D Ti B+ To +3VLP Ti B+ To +3VLP D
    Ti
    +3VLP Tj POW ER_SW _IN# To POW ER_SW _IN# Tj POW ER_SW _IN# To POW ER_SW _IN#
    1ns < Tj < 4s
    EC Input POWER_SW_IN# Tk POW ER_SW _IN# To ALW ON
    Td
    EC Output ALWON Tk Tm B+ To +3V_VC
    EC Output ALWON
    Te
    +3VALW(VCCDSW) Te
    +3VALW
    Tf
    +5VALW Tf
    +5VALW
    Tg
    ALW_PWRGD_3V_5V Tg ITEM Measure Point Time
    ALW_PWRGD_3V_5V
    Th T1 +3VALW To SIO_SLP_SUS#
    EC Output PCH_DPWROK Th
    PCH_DPWROK T2 SIO_SLP_SUS# To +3V_PCH
    1ns < Tj < 4s
    EC Input POWER_SW_IN# T3 SIO_SLP_SUS# To +1.8VA
    T4 SIO_SLP_SUS# To +1.0V_PRIM_CORE
    T5 SIO_SLP_SUS# To +1.0VA
    T6 +3VALW To MPHYP_PW R_EN
    T7 MPHYP_PW R_EN To +1.0V_MPHYGT
    T8 SIO_SLP_SUS# To SUSACK#
    T9 +1.0VA To PCH_RSMRST#
    T10 PCH_RSMRST# To AC_PRESENT
    T11 PCH_RSMRST# To SIO_SLP_S5#
    T12 SIO_SLP_S5# To SIO_SLP_A#
    T13 SIO_SLP_S5# To SIO_SLP_W LAN#
    T14 SIO_SLP_W LAN# To AUX_EN_W OW L
    T15 AUX_EN_W OW L To +3VS_NGFF
    T16 SIO_SLP_S5# To SIO_SLP_S4#
    T1 T17 SIO_SLP_S4# To +1.0V_VCCST
    PCH Output SIO_SLP_SUS#
    T18 SIO_SLP_S4# To SUS_ON_EC
    T2
    +3V_PCH T19 SUS_ON_EC To +1.8VU
    T20 SUS_ON_EC To +1.2V_DDR
    SUSCLK
    T21 SIO_SLP_S4# To VCCST_PW RGD
    T3
    +1.8VA T22 SIO_SLP_S4# To SIO_SLP_S3#
    T4 T23 SIO_SLP_S3# To RUN_ON_EC
    C +1.0V_PRIM_CORE C
    T24 RUN_ON_EC To +3.3VDX_SSD
    T5
    +1.0VA T25 RUN_ON_EC To +1.0VS_VCCSTG
    T6=tPCH06 T26 RUN_ON_EC To +1.0VS_VCCIO
    PCH Output MPHYP_PWR_EN(EXT_PWR_GATE#)
    T27 RUN_ON_EC To +3VS
    T7
    +1.0V_MPHYGT T28 RUN_ON_EC To +5VS
    T29 +3VS To RUNPW ROK
    PCH Output SIO_SLP_S0#
    T30 +3VS To IMVP_VR_ON
    T8
    EC Output SUSACK# T31 IMVP_VR_ON To VCORE_PG (PCH_PW ROK)
    T9 T32 VCORE_PG (PCH_PW ROK) To +VCC_SA
    EC Output PCH_RSMRST#
    T33 IMVP_VR_ON To +VCC_EDRAM
    PCH Output ME_SUS_PWR_ACK(SUSWARN#) T34 IMVP_VR_ON To +VCC_EOPIO
    T10 T35 IMVP_VR_ON To SYS_PW ROK (RESET_OUT#)
    EC Output AC_PRESENT
    T36 PCH_PLTRST# To +VCC_CORE
    T11
    PCH Output SIO_SLP_S5# T37 PCH_PLTRST# To +VCC_GT
    T12
    PCH Output SIO_SLP_A#
    T13
    PCH Output SIO_SLP_WLAN#
    T14
    EC Output AUX_EN_WOWL
    T15
    +3VS_NGFF

    EC Output SIO_PWRBTN# 16ms < T < 4s

    Minimum duration of PWRBTN # assertion = 16mS after SUSCLK stable


    T16
    PCH Output SIO_SLP_S4#
    T17
    +1.0V_VCCST

    T18
    EC Output SUS_ON_EC
    T19
    +1.8VU
    T20
    +1.2V_DDR
    B B
    T21
    VCCST_PWRGD
    T22
    PCH Output SIO_SLP_S3#
    T23
    EC Output RUN_ON_EC
    T24
    +3.3VDX_SSD
    T25
    +1.0VS_VCCSTG
    T26
    +1.0VS_VCCIO
    T27
    +3VS
    T28
    +5VS

    T29
    EC Input RUNPWROK (ALL_SYS_PWRGD)

    PCH Output CL_RST#

    T30
    EC Output IMVP_VR_ON
    T31
    VCORE_PG (PCH_PWROK)
    T32
    +VCC_SA
    T33
    +VCC_EDRAM
    T34
    +VCC_EOPIO
    T35
    EC Output SYS_PWROK (RESET_OUT#)

    PCH Output PCH_PLTRST#


    T36
    +VCC_CORE
    T37
    +VCC_GT
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P59-Power Up Sequence
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C881P
    Date: Tuesday, October 13, 2015 Sheet 59 of 59
    5 4 3 2 1

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