Silan

Semiconductors  SC7313

DIGITAL CONTROLLED STEREO
AUDIO PROCESSOR WITH LOUDNESS

DESCRIPTION
The SC7313 is a volume, tone (bass and treble), balance (left/ SOP-28

right) and fader(front/rear) processor for quality audio applications in

car radio and Hi-Fi systems. Selectable input gain and external
loudness function are provided. Control is accomplished by serial
I2C bus microprocessor interface. The AC signal settings is obtained
by resistor networks and switches combined with operational
amplifiers. Due to the Used BIPOLAR/CMOS technology, low DIP-28
distortion, low noise and low DC stepping are obtained.

FEATURES 
* Input multiplexer: ORDERING INFORMATION
--3 stereo inputs Device Package
--Selectable input gain for optimal adaptation to different SC7313 DIP-28-600-2.54
sources SC7313S SOP-28-375-1.27
* Four speaker attenuators:
 --4 independent speakers control in 1.25dB steps for * Loudness function
balance and fader facilities * Volume control in 1.25dB steps
--Independent mute function * Treble and bass control
* All functions programmable via serial I2C Bus * Input and output for external equalizer or
noise reduction system

PIN CONFIGURATIONS
CREF 1 28 SCL
BUS
VDD 2 27 SDA
INPUTS
GND 3 26 DIG GND

L 4 25 OUT LF
TREBLE
R 5 24 OUT RF

IN(R) 6 23 OUT LR

OUT(R) 7 22 OUT RR
SC7313
LOUD R 8 21 BOUT(R)

R3 9 20 BIN(R)
RIGHT BASS
R2 10 19 BOUT(L)
INPUTS
R1 11 18 BIN(L)

LOUD L 12 17 OUT(L)

L3 13 16 IN(L)
LEFT
INPUTS L2 14 15 L1 ) LEFT INPUTS

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Semiconductors  SC7313

BLOCK DIAGRAM
OUT IN LOUDNESS B-OUT B-IN TREBLE
(L) (L) (L) (L) (L) (L)
17 16 12 19 18 4

INPUT SELECTION SPEAKER

ATT LEFT
& GAIN CONTROL
25 FRONT
MUTE OUT
15

SPEAKER
LEFT VOLUME ATT LEFT
14 BASS TREBLE
INPUTS & LOUDNESS 23 REAR
MUTE OUT
13
28 SCL

BUS
SERIAL BUS DECODER + LATCHES 27 SDA

26 DIG-GND
9
SPEAKER
ATT
RIGHT RIGHT
VOLUME 24 FRONT
INPUTS 10 BASS TREBLE
& LOUDNESS OUT
MUTE

11
SPEAKER
ATT RIGHT
CREF 1 SUPPLY 22 REAR
MUTE OUT

2 3 7 6 8 21 20 5

VDD A-GND OUT IN LOUDNESS B-OUT B-IN TREBLE

(R) (R) (R) (R) (R) (R)

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit
Supply Voltage VS 10.2 V
Operating Temperature Tamb -40 ~ +85 C
Storage Temperature Tstg -55 ~ +150 C

QUICK REFERENCE DATA

Characteristic Symbol Min. Typ. Max. Unit
Supply Voltage Vs 6 9 10 V
Maximum input signal handling VCL 2 Vrms
Total harmonic distortion ,V=1Vrms, f=1kHz THD 0.01 0.1 %
Signal to noise ratio S/N 106 dB
Channel separation, f=1kHz Sc 103 dB
Volume control, 1.25dB step -78.75 0 dB
Bass and treble control, 2dB step -14 +14 dB
Fader and balance control, 1.25dB step -38.75 0 dB
Input gain, 3.75dB step 0 11.25 dB
Mute attenuation 100 dB

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Semiconductors  SC7313

ELECTRICAL CHARACTERISTICS (Refer to the test circuit)
(Tamb=25C
VS=9.0V,RL=10kRG=600all controls flat(G=0), f=1kHz,Unless otherwise specified)
Parameter Symbol Test conditions Min Typ Max Unit
SUPPLY VOLTAGE
Operating Supply Voltage VS 6 9 10.0 V
Operating Supply Current IS 20.0 35.0 mA
Ripple rejection of Supply Voltage SVR 60 80 dB
INPUTS SELECTORS
Input resistance RII Input 1,2,3 35 50 70 k
Clipping Level VCL 2 2.5 Vrms
Input Separation (note 2) SIN 80 100 dB
Output load resistance RL Pin7,17 4 k
Minimum input Gain GIN(MIN) -1 0 1 dB
Maximum input gain GIN(MAX) 11.25 dB
Step resolution GSTEP 3.75 dB
Input noise eIN G=11.25dB 2 V
Adjacent gain steps 4 20 mV
DC steps VDC
G=18.75 to MUTE 4 mV
VOLUME CONTROL
Input resistance RIV 20 33 50 k
Control range Crange 70 75 80 dB
Minimum attenuation AV(min) -1 0 1 dB
Maximum attenuation AV(max) 70 75 80 dB
Step resolution ASTEP 0.5 1.25 1.75 dB
AV=0 to 20dB -1.25 0 1.25
Attenuation set error EA dB
AV=-20 to 60dB -3 2
Tracking error ET 2 dB
Adjacent attenuation steps 0 3 mV
DC steps VDC
From 0dB to AV max 0.5 7.5 mV
SPEAKER ATTENUATORS
Control Range Crange 35 37.5 40 dB
Step resolution SSTEP 0.5 1.25 1.75 dB
Attenuation Set error EA 1.5 dB
Output Mute Attenuation AMUTE 80 100 dB
Adjacent attenuation steps 0 3 mV
DC steps VDC
From 0dB to MUTE 1 10 mV

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Semiconductors  SC7313

(continued)
Parameter Symbol Test conditions Min Typ Max Unit
BASS CONTROL (note 1)
Control Range GB Maximum boost/cut 12 14 16 dB
Step resolution BSTEP 1 2 3 dB
Internal feedback resistance RB 34 44 58 k
TREBLE CONTROL (note 1)
Control Range Gt Maximum boost/cut 13 14 15 dB
Step resolution TSTEP 1 2 3 dB
AUDIO OUTPUTS
Clipping level VOCL THD=0.3% 2 2.5 Vrms
Output load resistance RL 4 k
Output load capacitance CL 10 nF
Output resistance ROUT 30 75 120
DC voltage level VOUT 4.2 4.5 4.8 V
GENERAL
BW=20 ~20kHz,flat 2.5 V
output muted
Output noise eNO BW=20 ~20kHz,flat 5 15 V
All gains=0dB
A curve, all gains =0 dB 3 V
Signal to noise ratio S/N All gains=0dB; Vo=1Vrms 106 dB
Av=0,VIN=10mV 0.01 0.1 %
Distortion d Av=-20dB, VIN=1Vrms 0.09 0.3 %
Av=-20dB,VIN=0.3Vrms 0.04 %
Channel separation left/right Sc 80 103 dB
AV=0 to 20 dB 0 1 dB
Total tracking error
AV=-20 to 60 dB 0 2 dB
BUS INPUTS
Input low voltage VIL 1 V
Input high voltage VIH 3 V
Input current IIN -5 +5 A
Output voltage SDA acknowledge Vo Io=1.6mA 0.4 V
NOTES:
(1) Bass and treble response see Figure 16. The center frequency and quality of the response behavior can be
chosen by the external circuitry. A standard first order bass response can realized by a standard feedback
network.
(2) The selected input is grounded through the 2.2F capacitor.

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Semiconductors  SC7313

TYPICAL CHARACTERISTICS PERFORMANCE

Fig.1 Loudness vs. Volume Fig.2 Loudness vs. Frequency vs. Fig.3 Loudness vs. External
Attention volume Attenuation Capacitors

20 20
CLOUD=100nF
-10

15 0
Loudness (dB)

Loudness (dB)

Loudness (dB)
OPEN
-20

10 -20 56nF
220nF 10nF
-30 100nF

5 -40
Shorted to VREF
-40

0 -60

0 10 20 30 40 50 100 1k 10k 10 100 1k 10k 100k

Volume Attention (dB) Frequency (Hz) Frequency (Hz)

Fig.4 Noise vs.Volume/Gain Fig.5 Signal to Noise Ratio Fig.6 Distortion & Noise vs.
settings vs.Volume settings Frequency
1
VIN=1Vrms
1V AV=0dB
All controls Flat
100k
Volume=-20dB
THD & Noise (%)

-1


10k 10
Noise (V

Noise (V

10 VIN=1V

1k
Volume=0dB
22Hz ~ 22kHz S/N=76dB -2
100 10
3 S/N=106dB
A Curve
10 VIN=316V

1 1 -3
10
-80 -60 -40 -20 0 -80 -60 -40 -20 0 20 10 100 1k 10k 100k
Volume (dB) Volume (dB) Frequency (dB)

Fig.7 Distortion & Noise vs. Fig.8 Distortion vs. Load Fig.9 Channel Separation(LR) vs.
Frequency Resistance Frequency
1 -1 110
10
VIN=250mVrms
AV=0dB
All controls Flat
Channel Separation (dB)

Volume=-20dB 100
THD & Noise (%)

-1
10
THD (%)

90
VIN=1Vrms
Volume=0dB AV=0dB
All controls Flat
-2
10 80

70
-3 -2
10 10
10 100 1k 10k 100k 0.1 1 1 2 3 4
10 10 10 10
Frequency (dB) Load Resistance (k) Frequency (Hz)



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Semiconductors  SC7313

TYPICAL CHARACTERISTICS PERFORMANCE (continued)

Fig.10 Input Separation Fig.11 Supply Voltage Rejection Fig.12 Output Clipping Level vs.
( L1L2,L3,L4) vs. Frequency vs. Frequency Supply Voltage
110 100

90 5.0

Output Clipping Level (v)

Channel Separation (dB)

Channel Separation (dB)

RL=10k
100 f=1kHz
THD=0.3%
80 4.0
VIN=1Vrms
90 AV=0dB
All controls Flat
70 3.0

80 Vsvr=0.5Vrms
All Input to GND
60 AV=0dB 2.0
All controls Flat
70
1.0
1 2 3 4 1 2 3 4 4 6 8 10 12
10 10 10 10 10 10 10 10
Frequency (Hz) Frequency (Hz) Supply Voltage (V)

Fig.13 Quiescent current vs. Supply Fig.14 Supply current vs. Fig.15 Bass resistance vs.
Voltage Temperature Temperature
9.0 50

8.5 48
Quiescent Current (mA)

Quiescent Current (mA)

Bass Resistance (k

8.0 8.0 46
Vs=9V

6.0 7.5 44

4.0 7.0 42

2.0 6.5 40
4 6 8 10 12 -60 -30 0 30 60 90 -60 -30 0 30 60 90

Supply Voltage (V)

Temperature k
( ) Temperature k
( )

Fig.16 Typical Tone Response

(with the Ext components indicated
the test circuit)
15

AV=0dB
10
Tone Response (dB)

-5

-10

-15
1 2 3 4
10 10 10 10
Frequency (Hz)

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Semiconductors  SC7313

APPLICATION NOTES

2
1. I C BUS INTERFACE
Data transmission from microprocessor to the SC7313 and viceversa takes place through the 2 wires I2C BUS
interface, consisting of the two lines SDA and SCL(pull-up resistors to positive supply voltage must be connected).

2. DATA VALIDITY
As shown in Figure 17, the data of the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the dtat line can only change when the clock signal on the SCL line is LOW.

SDA

SCL

DATA LINE CHANGE

STABLE, DATA DATA
VALID ALLOWED

Fig. 17 Data Validity on the I2C BUS

3. START AND STOP CONDITIONS

As shown in Figure 18, a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.

SCL
I 2C
//
BUS

SDA
//
start stop

Fig. 18 Timing diagram of I2C BUS

4. BYTE FORMAT
Every byte transferred on the SDA line must obtain 8 bits. Each byte must be followed by the an acknowledge
bit. The MSB is transferred first.

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Semiconductors  SC7313

5. ACKNOWLEDGE
The master(microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse(see Figure 19). The peripheral(audioprocessor) that acknowledges has to pull-down(LOW) the SDA line
during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the reception of each
byte , otherwise the SDA line remain at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.

SCL 1 2 3 7 8 9
//

SDA MSB
//
Acknowledgment
start from receiver

Fig. 19 Acknowledge on the I2C BUS

6. TRANSMISSION WITHOUT ACKNOWLEDGE

Avoiding to detect the acknowledge of the audioprocessor, the microprocessor can use a simpler transmission:
simply it waits one clock without checking the slave acknowledgig, and sends the new data.
This approach of course is less protected from mis-working and decreases the noise immunity.

SOFTWARE SPECIFICATION
1. Interface protocol
The interface protocol comprises:

 A start conditions

 A chip address byte, containing the SC7313 address(the 8 th
bit of the bytes must be 0). The SC7313
must always acknowledge at the end of each transmitted byte.

 A sequence of data(N-bytes + acknowledge)

 A stop condition (P)
SC7313 address

MSB LSB MSB LSB MSB LSB

S 1 0 0 0 1 0 0 0 ACK DATA ACK DATA ACK P

Data Transferred
ACK: Acknowledge (N-Bytes + Acknowledge)
S: Start
P: Stop
Max clock speed: 100kbits/sec

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Semiconductors  SC7313

2. Chips address

1 (MSB) 0 0 0 1 0 0 0 (LSB)

3. Data bytes
MSB LSB Function
0 0 B2 B1 B0 A2 A1 A0 Volume Control
1 1 0 B1 B0 A2 A1 A0 Speaker ATT LR
1 1 1 B1 B0 A2 A1 A0 Speaker ATT RR
1 0 0 B1 B0 A2 A1 A0 Speaker ATT LF
1 0 1 B1 B0 A2 A1 A0 Speaker ATT RF
0 1 0 G1 G0 S2 S1 S0 Audio switch
0 1 1 0 C3 C2 C1 C0 Bass control
0 1 1 1 C3 C2 C1 C0 Treble control
Note: Ax=1.25dB steps;Bx=10dB steps;Cx=2dB steps;Gx=3.75dB steps

DETAILED DESCRIPTION OF DATA BYTES

1. Volume
MSB LSB Function
0 0 B2 B1 B0 A2 A1 A0 Volume 1.25dB steps
0 0 0 0
0 0 1 -1.25
0 1 0 -2.5
0 1 1 -3.75
1 0 0 -5
1 0 1 -6.25
1 1 0 -7.5
1 1 1 -8.75
0 0 B2 B1 B0 A2 A1 A0 Volume 10dB steps
0 0 0 0
0 0 1 -10
0 1 0 -20
0 1 1 -30
1 0 0 -40
1 0 1 -50
1 1 0 -60
1 1 1 -70
For example, a volume of 45dB is given by: 00100100

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Semiconductors  SC7313

2. speaker attenuators
MSB LSB Function
1 0 0 B1 B0 A2 A1 A0 Speaker ATT LF
1 0 1 B1 B0 A2 A1 A0 Speaker ATT RF
1 1 0 B1 B0 A2 A1 A0 Speaker ATT LR
1 1 1 B1 B0 A2 A1 A0 Speaker ATT RR
0 0 0 0
0 0 1 -1.25
0 1 0 -2.5
0 1 1 -3.75
1 0 0 -5
1 0 1 -6.25
1 1 0 -7.5
1 1 1 -8.75
0 0 0
0 1 -10
1 0 -20
1 1 -30
1 1 1 1 1 MUTE
For example, attenuation of 25dB on speaker RF is given by: 10110100

4. Audio switch
MSB LSB Function
0 1 0 G1 G0 S2 S1 S0 Audio switch
0 0 Stereo 1
0 1 Stereo 2
1 0 Stereo 3
1 1 Stereo 4
0 Loudness ON
1 Loudness OFF
0 0 +11.25dB
0 1 +7.5dB
1 0 +3.75dB
1 1 0dB
For example, to select the stereo 2 input with a gain of +7.5dB Loudness ON the 8bit string is: 01001001
Note: Stereo4 is connected internally, but not available on pins.

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Semiconductors  SC7313

5.Bass and treble
MSB LSB Function
0 1 1 0 C3 C2 C1 C0 Bass
0 1 1 1 C3 C2 C1 C0 Terble
0 0 0 0 -14
0 0 0 1 -12
0 0 1 0 -10
0 0 1 1 -8
0 1 0 0 -6
0 1 0 1 -4
0 1 1 0 -2
0 1 1 1 0
1 1 1 1 0
1 1 1 0 2
1 1 0 1 4
1 1 0 0 6
1 0 1 1 8
1 0 1 0 10
1 0 0 1 12
1 0 0 0 14
C3=Sign
For Example, bass at 10dB is obtained by the following 8bit string is: 01100010.

TEST AND TYPICAL APPLICATION CIRCUIT

2.2 F 5.6k
MCU
100 100 100 2.7nF
nF nF nF
28 27 26 17 16 12 19 18 4
LOUD BOUT BIN TREBLE
DGND SDA SCL OUT(L) IN(L)

11 R1
(L) (L) (L) (L)

10 F
AM/FM F
2.2
OUT LF 25
TUNER

F
2.2
15 L1
F
10
OUT RF 24
10 R2
CD F SC7313 F
2.2
PLAYER 10
14 L2
F
2.2
OUT LR 23

TAPE F
2.2
9 R3
F
10
OUT LR 22
13 L3
F
2.2
VDD AGND CREF OUT(R) IN(R)
LOUD BOUT BIN TREBLE
(R) (R) (R) (R)
2 3 1 7 6 8 21 20 5

F
22
100
nF
100
nF
100
nF
2.7nF

VDD

2.2 F 5.6k

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Semiconductors  SC7313

PACKAGE OUTLINE
DIP-28-600-2.54 UNIT:mm

2.54

0.05
B

0.25
13.8 0.25

15.24(600)
B

37.34 B0.3 B
1.52 0.5
15 degree

3.00MIN 4.96MAX
0.5MIN

0.46B0.08 2.16MAX

SOP-28-375-1.27 UNIT:mm
9.525(375)
0.3
0.4

B B
7.6
10.2

B0.25
17.75
1.27
0.45 B0.1 B0.05
0.15
2.8 MAX

16.51



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Semiconductors  SC7313

Attach

Revision History

Data REV Description Page

2000.12.31 1.0 Original
2002.02.26 1.1 Modify the package outline 12

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Rev: 1.1 2002.02.26
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