The M68000

Processor
What we are going to learn in this
session:
M68k hardware architecture:
M68k pin assignments
Pin functions.
The M68k Microprocessor
M68000, M68k microprocessor.
Motorola Semiconductors, 1979.
16-bit processor, but can perform 32-bit
operations.
Speed: 8-12 MHz.
The M68k Microprocessor
Very advanced compared to 8-bit
processors:
16-bit
data bus, 24-bit address bus.
Can execute instructions twice as fast.

Still available today:

Simple, practical commands.
Robust: can be used for many applications.
The M68k Microprocessor
The M68k Microprocessor
Has 64 pins:
Power supply and clock (5 pins).
Processor status (3 pins).
6800 peripheral control (3 pins).
System control (3 pins).
Data bus (16 pins).
Address bus (23 + 1 pins).
Asynchronous bus control (5 pins).
Bus arbitration control (3 pins).
Interrupt control (3 pins).
 +5V

VCC VCC D0- Data Bus

M68k Pin-Out D15
CLK
A1-A23 Address Bus
*A0 is used inside 68k

AS
FC0 R/W
Processor Status FC1 UDS Asynchronous
Bus Control
FC2 68000 LDS

E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control

GND GND IPL2

Power Supply &
Clock
 +5V

VCC VCC D0- Data Bus

D15
CLK
A1-A23 Address Bus
*A0 is used inside 68k

AS
FC0 R/W
Processor Status FC1 UDS Asynchronous
Bus Control
FC2 68000 LDS

E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control

GND GND IPL2

Vcc & GND
Vcc:
Voltage supply.
Gives electrical power to 68k.
2 pins into M68k.
supplies 5V (5%) voltage.
Connected to power supply.
GND:
Ground connection.
Lower potential for current flow.
2 pins out of M68k.
CLK
Clock signal.
1 pin from timing circuit.
Used for timing of:
Circuits
connected to M68k.
Synchronous data transfer.
Asynchronous data transfer (less important).
50% duty cycle:
50% up, 50% down.
Fall-To-Rise, Rise-To-Fall = 10ns.
Slower devices use modified signal from CLK.
CLK Signal
CLK

50% up 50% down

10 ns 10 ns
Processor Status
Pins
 +5V

VCC VCC D0- Data Bus

D15
CLK
A1-A23 Address Bus
*A0 is used inside 68k

AS
FC0 R/W
Processor Status FC1 UDS Asynchronous
Bus Control
FC2 68000 LDS

E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control

GND GND IPL2

FC0, FC1, FC2
Function Code pins.
3 pins output.
Indicates type of cycle currently executing:
Operation on user program/data.
Operation on supervisor program/data.
Interrupt acknowledge.

Values assigned by M68k.

AS must be low for valid output.
Function Code Description

AS FC2 FC1 FC0 What the 68k is doing

0 0 0 0 Reserved (No meaning)
0 0 0 1 Accessing User Data
0 0 1 0 Accessing User Program
0 0 1 1 Reserved (No meaning)
0 1 0 0 Reserved (No meaning)
0 1 0 1 Accessing Supervisor Data
0 1 1 0 Accessing Supervisor Program
0 1 1 1 Acknowledging Interrupt Request
1 X X X Outputs not valid (AS is high).
FC to Protect Supervisor
Memory

Data Bus
FC2 SUPERVISOR
EN
MEMORY
SPACE
AS

Address Bus
EN USER
MEMORY
SPACE
FC to Generate Interrupt
Acknowledge Signal

AS

FC0
68000 INTACK Device
Requesting
FC1
Interrupt

FC2
6800 Peripheral
Control
 +5V

VCC VCC D0- Data Bus

D15
CLK
A1-A23 Address Bus
*A0 is used inside 68k

AS
FC0 R/W
Processor Status FC1 UDS Asynchronous
Bus Control
FC2 68000 LDS

E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control

GND GND IPL2

6800 Peripheral Control
Allows M68k to interface with devices
using older processors (M6800).
Backward-Compatible.

Three pins:
E:Clock
VMA: Valid Memory Address.
VPA: Valid Peripheral Address.
Synchronous Data Exchange
Mode where:
Data exchange performed using same timing.
Timing generated by single clock signal.
Shared by all synchronous devices.
E 6800 Timing Signal
Synchronizes data transfer M68k &
6800:
Shared timing signal for slower 6800 devices.
Generated by M68k (output).
Modified CLK signal (/10).

40% duty cycle.

40% up, 60% down.
 Timing Signals: E vs. CLK
CLK

6 CLK cycles 4 CLK cycles

After modified by M68k

*Therefore, E has 40% duty cycle

VPA Valid Peripheral Address
VPA Valid Peripheral Address.
Input pin: received from 6800 device.
Functions:
Generates confirmation response to M68k.
Tells M68k that device exists and ready.
To tell M68k to synchronize to E.
VMA Valid Memory Address
VMA Valid Memory Address.
Output pin: sent by M68k to 6800 device.
Functions:
Informs the device that M68k is ready for data
transfer.
To tell 6800 device that M68k is sync. with E.
How M68k Accesses 6800
Devices
M68k 6800 Device

M68k accesses device by

1
referring to devices memory address.

Device detects attempt,

2
responds by setting
VPA to low.

After receiving VPA, M68k knows that

3
it has addressed a valid device.
How M68k Accesses 6800
Devices
M68k 6800 Device

M68k stops synchronizing with CLK,

4
and starts synchronizing with E.

M68k activates VMA to inform Device receives VMA,

5 6
device that it has synchronized with E. knows M68k is ready.

7 Both parties begin data transfer.

How 6800 Peripheral Control Works
1. M68k outputs device address on Address Bus.
2. M68k pulls AS low.
3. Two possible outcomes:
1. If device doesnt exist, M68k begins exception
processing.
2. If device exists, device responds using VPA.
4. M68k receives signal:
1. Sync. with E
2. Pulls VMA low ready to begin transfer.
5. Data transfer begins.
System Control
 +5V

VC VC D0- Data Bus

C C D15
CLK
A1-A23 Address Bus
*A0 is used inside 68k

AS
FC R/W
0
Processor Status FC UDS Asynchronous
1 Bus Control
FC 68000 LDS
2

E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control

GND GND IPL2

System Control
Responsible for control during catastrophic
system faults.

Consists of three pins (1 input, 2 bi-directional):

RESET: Reset pin.
HALT: Halt pin.
BERR: Bus error pin.

Functions:
To receive error notifications.
Stop/reset M68k operations.
Stop/reset peripherals.
BERR Bus Error
Receives information of bus error.
From watchdog circuit.
Only informs M68k, doesnt do anything else.
One-directional: into M68k.
Possible causes:
Invalidmemory address.
Physical damage to bus.
Peripheral error.
HALT Halt Signal
Causes M68k to pause from executing instructions.

If active:
M68k stops execution after current cycle.
Waits until HALT is inactive.
Resumes execution.

Is bi-directional:
From external circuit / M68k (STOP command).
Both have same effect.
Also used to restart M68k (together with RESET).
RESET Reset Signal
Resets M68k / external circuit.
Is bi-directional:
If signal from external circuit, resets M68k
(together with HALT for 10 clock cycles).
If signal from M68k, resets external circuitry
connected to RESET pin (RESET instruction).
How M68k Manages Bus Errors

M68k Watchdog Circuit

M68k executes current
1
processing cycle. Watchdog detects problems
2
during execution, tells
M68k by activating BERR.
M68k receives BERR signal,
3
knows something is wrong.

4 M68k checks the status of HALT.

 Start exception processing
M68k Re-run current processing cycle

5 If HALT is inactive. 5 If HALT is active.

6 Cancel the problem bus cycle,

Cancel the problem bus cycle. store all address, data, & control.
6
7 Set address & data bus to
high impedance state.
7 Start bus exception processing.
8 Wait until HALT is inactive.

9 Load previous address, data &

control codes, re-run
execution of problem cycle.
Interrupt Control
 +5V

VC VC D0- Data Bus

C C D15
CLK
A1-A23 Address Bus
*A0 is used inside 68k

AS
FC R/W
0
Processor Status FC UDS Asynchronous
1 Bus Control
FC 68000 LDS
2

E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control

GND GND IPL2

Interrupt Control
Interrupt pins for M68k.
3 pins (input).
Functions:
Used by external circuit to request interrupt.
Used to prioritize M68k tasks.

Generated by external circuits:

Important tasks assigned higher interrupts.
7 levels: 0 (lowest) to 7 (highest).
Interrupt Control
IPL2 IPL1 IPL0 Interrupt level
1 1 1 0 (No Interrupt)
1 1 0 1
1 0 1 2
1 0 0 3
0 1 1 4
0 1 0 5
0 0 1 6
0 0 0 7 (Highest, Non-maskable )
Interrupt Example

M68k External Peripheral

1 M68k is executing
instructions normally.
2 External peripheral has
important task for M68k.

3 External peripheral asks for

attention by outputting
4 M68k compares interrupt interrupt on IPL0, IPL1,
level to SR. IPL2.
T S I2 I1 I0 XNZVC
 M68k

5 If external interrupt 5 If external interrupt

higher than current. lower than current.

6 Update interrupt bits, 6 Wait for higher-level

save controls, interrupt being handled.
registers into stack.

7 Handle interrupt,
restore interrupt bits.

8 Restore controls, registers,

resume normal execution.
Bus Arbitration
Control
 +5V

VC VC D0- Data Bus

C C D15
CLK
A1-A23 Address Bus
*A0 is used inside 68k

AS
FC R/W
0
Processor Status FC UDS Asynchronous
1 Bus Control
FC 68000 LDS
2

E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control

GND GND IPL2

Bus Arbitration Control
Carries signals that allow bus takeovers:
M68k releases bus control to external device.
Faster data transfer, multi-CPU architecture, less
overhead.
M68k waits, then takes back bus control.
Lets external devices become bus masters:
Device must have own microcontroller.
Accesses other peripherals as if it was CPU.

Usually for DMA.

Example: Transferring Data from HDD (CPU as Bus Master)

Interrupt
HDD Serial I/O
Circuit

System Bus

Memory CPU Timing

All components must go through CPU for to transfer data.

Example: Transferring Data from HDD (HDD C as Bus Master)

HDD

Micro- Interrupt
Serial I/O
Controller Circuit

System Bus

Memory CPU Timing

Less CPU overhead, CPU can process instructions that dont require bus.
BR Bus Request
Used by external circuit to request bus
control.
Input to M68k, 1 pin.
Connected to Bus Request output on
Alternate Bus Master (ABM).
Sends and waits for M68k response.
BG Bus Grant
Used by M68k to:
Acknowledge bus request.
Tell device that it will release bus control.

Output from M68k, 1 pin.

Connected to Bus Grant input on ABM.
Sends and waits for ABM response.
BGACK Bus Grant Acknowledge
Used by ABM to acknowledge bus control
transfer.
1 pin, input to M68k.

Before BGACK, must fulfill these conditions:

BG active: M68k has given permission.
AS inactive: M68k not using bus.
DTACK inactive: No other device using bus.
BGACK inactive: No other ABM as bus master.

BGACK active until ABM releases control.

Example of Bus Takeover

M68k
HDD

1. M68k is executing 2. HDD wants to

instructions normally. become Bus Master.

3. HDD requests to M68k

by activating BR and waits.
4. When M68k is ready to
release bus control, activates
BG.
Example of Bus Takeover

M68k
HDD

5. HDD receives BG, knows

that request granted.

6. HDD activates BGACK to

acknowledge.
7. M68k releases bus control to HDD.
8. HDD takes control of bus,
Releases BGACK when done.

9. M68k takes bus control

back, resumes execution normally.
Data & Address Bus
 +5V

VC VC D0- Data Bus

C C D15
CLK
A1-A23 Address Bus
*A0 is used inside 68k

AS
FC R/W
0
Processor Status FC UDS Asynchronous
1 Bus Control
FC 68000 LDS
2

E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control

GND GND IPL2

Data Bus
Used for general-purpose data transfer.
16-bits (D0 to D15), bi-directional.
Can transfer word or byte data.
Also used to carry vector number during
Interrupt Acknowledge Cycle.
Address Bus
Used to carry address values.
23-bits (A1 A23), one-directional.
A0 used internally, spurs UDS, LDS.
Able to address 16 MB of memory.
Asynchronous Bus
Control
 +5V

VC VC D0- Data Bus

C C D15
CLK
A1-A23 Address Bus
*A0 is used inside 68k

AS
FC R/W
0
Processor Status FC UDS Asynchronous
1 Bus Control
FC 68000 LDS
2

E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control

GND GND IPL2

Asynchronous Bus Control Group

Responsible for asynchronous data

transfer.
Most common data transfer method.
5 pins:
Regulate data transfer: AS, DTACK.
Activate device: UDS, LDS.
Type of operation: R/W.
Asynchronous Transfer
Used to perform asynchronous data
transfer:
Doesnt follow strict timing from CLK.
Transfer based on handshaking between
sender and receiver:
CLK replaced by sender-ready and receiver-ready.
Sender sends data when its ready.

Receiver sends signal when transfer completes.

AS Address Strobe
Purpose:
Indicates M68k using bus.
Valid address on address bus.

Activated when M68k wants to use bus:

Begin reading from memory.
Begin writing to memory.
Access peripherals.
R/W
Used to specify read/write operation.
1 pin, output.
Three states:
High (1): read (default).
Low (0): write.
High-impedance: when ABS is controlling bus.
DTACK Data Transfer Acknowledge

Indicates device ready to begin data transfer.

Generated by external device being accessed.
When M68k receives signal, knows data transfer
can be started, begins read/write.
During data transfer, M68k inserts wait states
until DTACK is received.
UDS/LDS
Used to activate correct memory chip
during read/write:
Datausually stored in pairs of chips.
Each chip partially connected to data bus.
LDS activates D0 to D7 (odd bytes).
UDS activates D8 to D15 (even bytes).
 How Data is Stored in Memory
$000000
Chip #1 Chip #2
$000001
$000002 Controlled $000000 Controlled $000001
by UDS. by LDS.

$000003 $000002 $000003

$000004 $000004 $000005
$000005 $000006 $000007

(even (odd

addresses) addresses)

$FFFFFE $FFFFFE $FFFFFF

$FFFFFF
 How Data is Stored in Memory
MOVE.L #$12345678,$1000
1 2 3 4 5 6 7 8

Chip #1 Chip #2
$1000 $12 $1001 $34
$1002 $56 $1003 $78
$1004 $1005
$1006 $1007
$1006 $1009
$1006 $100A
* Controlled by UDS * Controlled by LDS
 How Data is Stored in Memory
$000000
Chip #1 Chip #2 Chip #3 Chip #4
$000001
$000000 $000001 $001000 $001001
$000002 $000003 $001002 $001003
$000002 $000004 $000005 $001004 $001005
$000006 $000007 $001006 $001007
$000003
$000004 EVEN ODD EVEN ODD

$000005
$000FFE $000FFF $001FFE $001FFF

$001FFE Controlled
Controlled
by LDS.
by UDS.
$001FFF
Activating the Correct Chip
Each memory chip has:
Data pins: outputs/receives to/from M68k.
Address pins: receives address from M68k.
OE (Output Enable): Allows data to be sent
from chip.
CS (Chip Select): Enables chip for data
transfer.
WE (Write Enable) (for RAM only): Allows
data to be written to chip.
Activating the Correct Chip
Chip activated only if:
CS is enabled.
OE is enabled.

CS enabled when MAD receives unique

pattern from Address Bus, AS active.
OE enabled when UDS or LDS active.
 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

D0
Address Bus
D1

UDS OE D2

R/W WE D3

CS D4
D5
D6
D7
Memory
Address
Decoder
D0
D1
AS D2
CS D3
R/W WE D4
LDS OE D5
D6
D7
Which one gets selected?

UDS LDS CS What data to access Chip selected

1 1 0 No valid data None
0 1 0 D8-D15 (even bytes) Chip #1
1 0 0 D0-D7 (odd bytes) Chip #2
0 0 0 D0-D15 (word data) Both
X X 1 None (CS high) None
Read Cycle
 M68k Read Cycle
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

AS

LDS/UDS

R/W

DTACK

D0 D15

FC0 FC2
 Step 1: Update FC & Specify Operation

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

Read operation specified, R/W = 1.

AS

LDS/UDS

R/W
FC0 FC1 FC2 Type of bus cycle
DTACK 0 0 1 Accessing user data
0 1 0 Accessing User Program
D0 D15 1 0 1 Accessing SV Data
1 1 0 Accessing SV Program
FC0 FC2
FC0-2 informs what type of cycle is executing.
 Step 2: Load Address Bus with Memory Address

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

AS

LDS/UDS

R/W

DTACK

Just loaded, not sent yet.

D0 D15

FC0 FC2
 Step 3: Specify Byte & Activate AS

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

Indicates M68k using bus,

CLK
send address to MAD. Wait
for MAD response.
A1 A23

AS

LDS/UDS

R/W
Specifies which data to access.
DTACK
UDS LDS What data to access
1 1 No valid data
D0 D15 1 0 D8-D15 (even bytes)
0 1 D0-D7 (odd bytes)
0 0 D0-D15 (word data)
FC0 FC2

* Waits for DTACK

 Step 4: Activate DTACK

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

AS
If address exists, external device
activates DTACK.
LDS/UDS

R/W

DTACK

D0 D15

FC0 FC2
 Step 5: Get Data

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

AS

LDS/UDS

R/W
Memory puts data on data bus,
loaded into M68k.
DTACK

D0 D15

FC0 FC2
 Step 6: Complete Transfer

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

AS

LDS/UDS When M68k done,

all controls returned
to normal. New
R/W cycle starts.

DTACK

D0 D15

FC0 FC2
Write Cycle
 M68k Write Cycle
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

AS

LDS/UDS

R/W

DTACK

D0 D15

FC0 FC2
 Step 1: Specify Operation
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

AS

LDS/UDS

R/W
FC0 FC1 FC2 Type of bus cycle
DTACK 0 0 1 Accessing user data
0 1 0 Accessing User Program
D0 D15 1 0 1 Accessing SV Data
1 1 0 Accessing SV Program
FC0 FC2
FC0-2 informs what type of cycle is executing.
 Step 2: Load Address Bus
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

AS M68k loads destination

address into address bus.
LDS/UDS

R/W

DTACK

D0 D15

FC0 FC2
 Step 3: Activate AS, Specify Operation
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23 AS = 0, Tells other devices that:

- M68k using bus now.
- Valid address on bus.
AS

LDS/UDS

R/W

DTACK

D0 D15 R/W = 0, write operation.

FC0 FC2
 Step 4: Load Data Bus
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

AS

LDS/UDS

R/W

DTACK

D0 D15

Just loaded, not sent yet.

FC0 FC2
 Step 5: Load Data Bus
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK
UDS LDS What data to access
1 1 No valid data
A1 A23 1 0 D8-D15 (even bytes)
0 1 D0-D7 (odd bytes)
0 0 D0-D15 (word data)
AS

LDS/UDS 2. M68k tells which

chip to write on.
R/W

DTACK 1. Memory gives response,

address exists.
D0 D15

3. Data bus contents

FC0 FC2 written to memory.
 Step 6: Load Data Bus
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2

CLK

A1 A23

AS
When M68k done,
LDS/UDS all controls returned
to normal.

R/W

DTACK

D0 D15

FC0 FC2 New cycle starts.

Conclusion
Summary of M68k Pins

Group Function Pins

Power & Clock Provides power, clock signal. Vcc, GND, CLK

Indicates type of cycle

Processor Status FC0 FC2
being executed.
6800 Peripheral Interfaces with older 6800
VPA, VMA, E
Control devices (synchronous transfer).

System Control Error monitoring & handling. BERR, RESET, HALT

Summary of M68k Pins
Group Function Pins

Interrupt request
Interrupt Control IPL0, IPL1, IPL2
by external device.
Bus Arbitration
Allows bus takeovers by ABM. BR, BG, BGACK
Control
Asynchronous Allows asynchronous data transfer AS, R/W, UDS,
Bus Control between M68k and devices. LDS, DTACK

Address Bus Carries address from M68k. A1-A23

Data Bus Carries data from M68k & devices. D0-D15

The End

Please read:
Antonakos, pg. 238-254