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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity sandhuuu is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic);
end sandhuuu;
begin
c <= a and b ;
end Behavioral;
OR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity sandhuuu is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic);
end sandhuuu;
begin
c <= a or b ;
end Behavioral;
NOT GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dgrfdf is
Port ( a : in std_logic;
b : out std_logic);
end dgrfdf;
begin
b <= not a ;
end Behavioral;
FULL ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity add is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
bb : out std_logic);
end add;
begin
s <= a xor b xor c ;
bb <= ( a and b ) or ( b and c ) or ( c and a ) ;
end Behavioral;
HALF ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ddd is
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
end ddd;
begin
s <= a xor b ;
c <= a and b ;
end Behavioral;
AND GATE
OR GATE
NOT GATE
FULL ADDER
HALF ADDER