Test Power Case Study:

Transition Fault Testing (LOC, LOS) Power

Analysis and Reduction Techniques

Based on the paper

"Power Analysis and Reduction Techniques for Transition
Fault Testing," Asian Test Symposium (ATS), 2008.
pp.403-408 (Authors: Agarwal, K. et al)

12/1/2012 1
 Outline

Trends in TFT Power Consumption

LOC vs LOS: Detailed Power Comparisons and

Analysis

Reduction Techniques

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 Trends in TFT Power Consumption

600.00

575.00
Max power
550.00 consumption (W)
Frequency(In Mhz)

525.00

LOC - Fmax
500.00
LOS - Fmax

475.00
Fmax frequency difference
Test Module1 Module2
450.00 suspected to be due to high
switching activity in LoS
425.00 LOS 1.05 1.21
400.00
1 175 349 523 697 871 1045 1219 1393 1567 1741 1915 2089 2263 2437 2611 2785 2959 3133

Devices ordered based on LOS Fmax frequency

LOC 0.779 0.475

Fmax plot for a 90nm Results from IR

SOC (silicon data) drop analysis
12/1/2012 3
LOS Vs. LOC Capture Power
Comparison
LOC vs. LOS power
comparison done on
two example designs
Ckt1a : with clock
gates
Ckt2a : without clock
gates
Ckt1b : compression
inserted Ckt1a
Ckt2b : compression
inserted Ckt2a

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 Most Power Consuming Pattern
Comparisons
LOC LOC LOS LOS LOS launch LOS capture LOS capture
launch capture launch capture Vs Vs Vs
(mW) (mW) (mW) (mW) LOC launch LOC capture LOC launch

Ckt1a 683 520.5 1137 667 66.47% 28.14% -0.02%

Ckt2a 1025 958 1165 918 13.65% -0.04% -0.1%

Ckt1b 524 371 1025 551 95.6% 48.5% 0.05%

Ckt2b 870 748 1028 857 18.16% 14.57% -0.01%

LOS Launch > LOC Launch

LOS capture ~ LOC Launch
The difference between LOS launch power and LOC launch power is aggravated
in presence of clock-gates.
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Comparisons Across the Pattern Set
LOC vs LOS power comparison done across the complete
pattern set (first5 mid5, last5)
Clock gates present (No compression)
LOS launch power significantly higher (~66% for the
most power consuming pattern) than LOC launch
power across the pattern set
LOC vs LOS launch and capture trend across various pattern sets
(Clock gates present)

1400

1200

1000 LOC launch

Power (mW)

800 LOC capture

LOS Launch
600
LOS capture
400

200

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Patterns

12/1/2012 6
 Root Cause Analysis

Clock Comb. Seq.

Sequential power in LOS
Ckt1a power Power Power
launch is around 100%
more than LOC launch.
(mW) (mW) (mW)

Clock tree power for LOS LOC

launch is around 100% 105 407 268
launch
more than LOC launch.

This indicates that nearly

LOC
88.2 274 177
half the clocks are not capture
active in LOC launch
compared to LOS launch. LOS
205 577 515
LOC Launch 38% flops get launch
clocked
LOS
LOS Launch : 100% flops
115 347 257
capture
get clocked

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Clock Gate Hookup in Current Designs
Combo cloud
Q EN Q
CLK
FF TE FF
Scan enable
Clock gates LOC Launch : Clock to the FF through
L the functional path
Scan enable

O FF may or may not get the

CLK launch clock depending on
the functional enable (EN)
C CLK
of the clock gates
CLK

Q
Q Combo cloud EN CLK
TE
L FF
FF
Scan enable
Clock gates
LOS Launch : Clock to the FF through
O the Test path
Scan enable
FF will definitely get the
S launch Clock. Only capture
CLK
clock will depend on the
CLK functional enable (EN) of
12/1/2012 the clock gates 8
Reduction Techniques
Can be classified into two broad categories
ATPG techniques
Fill options
Low effort ATPG.

Design techniques
Clock gates TE control
Clock gates FE control
Low compression

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1. Reduction Techniques : Fill
Ckt1a : Netlist without compression
LOS launch power ~44% greater than LOC
launch power for Adjacent fill and 0 fill
techniques

Effect of fill techniques on LOS launch for non-compression inserted netlist

1400

1200

1000
adjacent fill
800
Power

random fill

600 0 fill
1 fill
400

200

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Patterns

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1. Reduction Techniques : Fill
Ckt1b : Netlist with compression
LOS launch power for the most power consuming
pattern ~90% higher than LOC launch
Effect of Fill techniques on LOS launch for compression inserted
netlist

1200

1000

800
Adjacent fill
Power

Random fill
600
0 fill

400 1 fill

200

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

patterns

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2. Reduction Techniques : Modified
LOS
100% flops get clocked during
LOS launch TEN_CG TEN CG
38% flops get clocked during
LOC launch EN
Changing the LOS clocking for
TEN CG
Launch (make it similar to LOC
clocking) EN

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 Reduction Techniques : TE control of
clock gates and adjacent fill
Ckt1a : Netlist without compression
For the most power consuming pattern LOS
launch is ~18% higher than LOC launch

Max Power for LOS launch

789 mW 900

800
18%
700

600
665 mW
Power

500
LOS Launch
400 LOC launch

300
Max Power for LOC launch
200

100

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

12/1/2012 First 5 Mid 5 Last 5 13

Reduction Techniques : TE control of
clock gates and adjacent fill
Ckt1b : Netlist with compression
For the most power consuming pattern
LOS launch is ~30% higher than LOC
launch Max Power for LOS launch

800

704 mW 700

30% 600

542 mW 500
Power

LOS launch
400
LOC launch
300

200 Max Power for LOC launch

100

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

12/1/2012 First 5 Mid 5 Last 5 14

 3. Reduction Techniques : FE control
of clock gates

TEN_CG
TE
Clk_out
ICG cell modified to include extra EN
Latch
-velevel
gate and input TE_new FE Sensitive
latch
D
FE control of clock gates controlled
ICG
during at-speed cycles
Data
If TE_new = 1 only then functional
Q COMBO D Q
D LOGIC
value propagates Clock

This enables user to activate only CLK CLK

certain groups of functional enables

to allow propagation of clocks

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 3. Reduction Techniques : FE control
of clock gates

TEN_CG
TE
Clk_out
ICG cell modified to include extra EN
Latch
-velevel
TE_new
gate and input TE_new FE Sensitive
latch
D
FE control of clock gates controlled
ICG
during at-speed cycles
Data
If TE_new = 1 only then functional
Q COMBO D Q
D LOGIC
value propagates Clock

This enables user to activate only CLK CLK

certain groups of functional enables

to allow propagation of clocks

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3. Reduction Techniques : FE control of
clock gates and adjacent fill (contd..)
Peak
Pattern switching
Activation Count activity
All four groups allowed to toggle 4400 6700
One group at a time followed by all four 5483 6364
Two groups at a time followed by all four 7608 6072
One group at a time followed by two followed
by four 8590 5905
Two groups at a time followed by three
followed by four 7890 5363
Progressive Group Activation ATPG
pass

G1
Suitable for regenerating high switching patterns,
G2 the other low power DFT/ATPG techniques
after
have
G3 been applied.
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G4
4. Low compression and low effort
ATPG

Generate patterns with TE control and

adjacent fill
Examine the power profile of patterns
Identify the high power consuming patterns
Retarget the faults covered by those patterns
with two low power alternatives
low compression
low effort ATPG
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Pattern Generation for compression
netlist with TE control and adjacent fill
First 1000 patterns
Max switching activity ~ 5700

7000
7000

6000
6000
switching activity
activity

5000
5000
Peak switching

4000
4000

3000
3000
Peak

2000
2000

1000
1000

0 0
0 0 500 5001000 1000
1500 2000
1500 250020003000 2500
3500 4000
3000 4500
3500 5000 4000 4500 5000

Patterns Patterns

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Retarget with Low compression and low
effort ATPG

Peak switching activity

~5737
7000

6000
Peak switching activity

5000

4000

3000

2000

1000

0
0 500 1000 1500 2000 2500
Patterns

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Consolidated Flow
Input Design

Pattern re
-generation:
Insert dual Low compression and
compression codec low ATPG effort

Provide TE and FE
Power Estimation
controls to clock gates
(Toggle Count)
Design
Preparation
Threshold
Prune high switching
patterns
Run ATPG
(High Compression, Adj Fill, Updated Fault DB
TE Control Enabled)
Pattern re
-generation:
Progressive enabling of
clock gate FEs
Power Estimation
(Toggle Count)

Gate-Level
Power Estimation
Threshold Prune high switching
patterns
Final Power
Profile
Updated Fault DB

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 Conclusions
LOS launch power ~95% (for the most power consuming
pattern) higher than LOC launch power.
Several techniques proposed for TFT power reduction
Adjacent Fill + TE Controls
LOS launch power ~18% higher than LOC launch
Pattern volume inflation for Ckt1a and Ckt1b was
21.8% and 52.8%, respectively.
FE controls
LOS launch power comparable to LOC launch power.
The final pattern volume inflation after applying this
technique on the reduced fault set (for the high
switching patterns) for Ckt1b was ~59%.

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