MAPUA UNIVERSITY

SCHOOL OF INFORMATION TECHNOLOGY

EXPERIMENT NO. 6
THE FLIP-FLOP

PALILEO, PRELAB 10
CHRISTINE MAE G DATA SHEET 25
GROUP NO. 1 ORGANIZATION 5
COMPLETENESS 10
IT160L / BT2 PRESENTATION 10
INTERPRETATION 25
JUNE 8, 2017 CONCLUSION 15
DATE PERFORMED
ADDITIONAL POINTS
JUNE 15, 2017
DATE SUBMITTED
TOTAL 100

_____________________________

Engr. Joel C. De Goma

SCHEMATIC DIAGRAM
WIRING DIAGRAM
SAMPLE PICTURES

PART 1

PART 2
PART 3
INTERPRETATION

In the first part of the experiment, we created the RS Latch

using the NAND Gates. The inputs go through a NAND gate before
passing through the NAND Gate Latch so the input values became
the complement. We have observed that when input S is 1, after
passing the first NAND Gate, and Input R is 0, then Q is zero,
when both inputs are 1, the value becomes invalid.

In the second part of the experiment, we added a clock to

the RS Flip-Flop. We have observed that the same output is given
as with the first experiment when the clock input is 0. When the
clock input is 1, the output becomes its complement.

In the last part of the experiment, the same logic as the first
experiments applies. The change in the outputs is triggered when
the clock input is 1. The difference is that there are no invalid
outputs.

CONCLUSION

The RS Latch using the NAND Gates is the basic Flip-Flop.

The inputs of the Flip-flop are set (S) and reset (R). The inputs are
active low, that is, the output will change when the input is pulsed
low. The basic operations of the latch are:
 The clocked RS latch circuit is very similar in operation to the
basic RS Latch. The S and R inputs are normally at logic 0, and
must be changed to logic 1 to change the state of the latch. The
output can only change state while the CLOCK input is a logic 1.
When CLOCK is a logic 0, the S and R inputs will have no effect.

The JK Flip-Flop is designed to overcome the problems of the RS

Flip-Flop, which provides an invalid output when both inputs are
0. The JK Flip Flop is basically a gated RS flip flop with the addition
of the clock input circuitry. When both the inputs S and R are
equal to logic 1, the invalid condition takes place. Thus to
prevent this invalid condition, a clock circuit is introduced. The JK
Flip Flop has four possible input combinations because of the
addition of the clocked input.
References:

http://circuitglobe.com/jk-flip-flop.html
http://hyperphysics.phy-
astr.gsu.edu/hbase/Electronic/nandlatch.html
http://www.play-
hookey.com/digital/sequential/clocked_rs_latch.html