CmpE 110

Digital Electronics
Class Notes

By
Dr. Ahmet Bindal
Revised August 2008

1
CHAPTER I. RLC NETWORKS
A. BASIC CONCEPTS ON PASSIVE ELEMENTS
Resistance:

vR(t)

R
iR(t)
vR(t) = R iR(t)

£ [vR(t)] = VR(s) = R £ [iR(t)] = R IR(s)

VR ( s )
ZR ( s ) =
IR ( s )

Capacitance:

vC(t)

C
iC(t)
dvc(t )
iC(t) = C
dt
dvc(t )
£ [iC(t)] = IC(s) = C £ [ ]
dt
∞
Laplace transform: F ( s ) = ∫ f (t )e − st dt
0

Thus:
∞ ∞
dvc(t ) dvc(t ) − st
£[ ] =∫ e dt = ∫ e− st dvc(t )
dt 0
dt 0

But,
∞ ∞ ∞

∫ e dvc(t ) = e vc(t )⏐0 - ∫ vc(t )(− s)e dt = [0- vc(0) ] + s ∫ vc(t )e dt = sVC(s) - vC(0)
− st − st ∞ − st − st

0 0 0

Then:
£ [ic(t )] = C[ sVc ( s ) − vc (0)] = sCVc ( s )
1
Thus, ZC(s) =
sC

2
Inductor:

vL (t)

L
iL(t)

diL(t)
vL(t) =
dt
diL(t)
£ [ vL(t)] = VL(s) = L £[ ] = L [sIL(s) – iL(0)] = sL IL(s)
dt
ZL(s) = sL

B. TIME-DOMAIN ANALYSIS OF PASSIVE NETWORKS

(i) RC Circuits

Integrator:
R
vout

+ i
vin C
-

Vin = Ri + vout
dvout
i=C
dt
dVin di i
=R +
dt dt C
di i 1 dVin
+ =
dt RC R dt

General Solution:
di 1
+ i=0
dt RC

3
Characteristic equation:
1 1
s+ =0⇒ s =−
RC RC
t
−
ig = Ae st = Ae RC

ip = 0
t
−
i (t ) = ig (t ) + i p (t ) = Ae RC

1 ⎛ Vin ⎞ − RCt
t t
1
vout = ∫ idt = ⎜ ⎟ ∫ e dt
C0 C⎝ R ⎠0

Vin − RCt
e ( − RC )⏐t0 = −Vin ⎢⎢e− RC −1⎥⎥
⎡ t ⎤
=
RC ⎣ ⎦

⎡ −
t
⎤
vout = Vin ⎢1 − e RC ⎥
⎣ ⎦

vout

Vin

0 t

Differentiator

C
vout
+ i
vin R
-

Vin = vc + vout
dvc di
0= +R
dt dt

4
 i di
0= +R
C dt
di 1
+ i=0
dt RC
1
But, the characteristic equation: s + =0
RC
i (t ) = ig (t ) + i p (t ) = Ae st + 0
t
−
i (t ) = Ae = Ae
st RC

t
−
vout = Ri (t ) = ARe RC

But, vc(0) = 0 ⇒ vout (0) = Vin

Vin = AR
Vin
Thus, A =
R
t
−
Thus, vout = Vine RC

vout
Vin

0 t

5
(ii) RL Circuits

V = v R + v out

v R = Ri Ohms law
di
v L (t ) = L Lorentz Law
dt
di
V = Ri + L
dt
di R V
+ i=
dt L L
To solve the general solution (the homogeneous part) use Laplace Transform:

£ ⎡⎢ dtdi + RL i⎤⎥ = 0
⎣ ⎦

R
I (s)S + I (s) = 0
L
⎡ R⎤
I (s)⎢S + ⎥ = 0
⎣ L⎦
I (s) ≠ 0
⎡ R⎤
∴ ⎢S + ⎥ = 0
⎣ L⎦
−R
S=
L
−R
t
i (t ) = Ae L

To solve the particular solution:

Look at the degree of the particular portion.
V
is a constant, so substitute i p = K into
L

6
di p R V R V
+ ip = Æ 0+ K=
dt L L L L
V
K=
R
Now put the general and particular solutions together:
−R
t V
i (t ) = Ae L +
R
Now solve for A by using the initial condition i (0) = 0 :
V −V
i ( 0) = A + =0 Æ A=
R R

V ⎛⎜ ⎞
−R −R
V V t t
⎟
∴ i (t ) = − e L = 1− e L
R R R ⎜⎝ ⎟
⎠
Use Lorentz Law to solve for v out
di
v out = L
dt
⎛V ⎛ −R
t ⎞⎞
d ⎜ ⎜ 1 − e L ⎟⎟
⎜R⎜ ⎟⎟
V ⎛⎜ t ⎛ − R ⎞⎞
−R −R
⎝ ⎝ ⎠⎠ ⎟
t
v out =L =L 0−e L ⋅⎜ ⎟ = Ve L
dt R⎝ ⎜ ⎝ L ⎠⎠ ⎟

RESULTS:

V ⎛⎜ ⎞
−R
⎟
t
i (t ) = 1− e L
R ⎜⎝ ⎟
⎠
−R
t
v out = Ve L

7
(iii) RLC Circuits
vL (t)
L
R
vout (t)

i (t)
+
vin
C
-

Vin = Ri (t ) + vL (t ) + vout (t )
di (t ) dv (t )
vL (t ) = L and i (t ) = C out
dt dt
di
Vin = Ri (t ) + L + vout (t )
dt
Differentiating both sides yields:
di d 2i dv di d 2i i
0 = R + L 2 + out = R + L 2 +
dt dt dt dt dt C
R 1
Characteristic equation: s 2 + s+ =0
L LC

R R2 4
− ± − 2
L L 2
LC R ⎛ R ⎞ 1
s1,2 = = − ± ⎜ ⎟ −
2 2L ⎝ 2L ⎠ LC
R 1
Let α = and ω0 =
2L LC
s1, 2 = −α ± α 2 − ω0
2

i (t) =A e s1t + Be s 2 t ← find A & B

At t = 0-, iL(0-) = i(0-) = 0

Since the current through the inductor cannot change suddenly, iL(0+) = i(0+) = 0

Thus, i(0) = 0 = A + B

A=-B

We need another initial condition to find A and B explicitly.

8
 di (t )
Evaluate :
dt
di (t )
= A s1 e s1t + A s2 e s 2t = A ( s1 e s1t − s2 e s 2t )
dt

However, at t = 0− vout (0-) = 0 and vR (0-) = i (0-) R = 0

When the switch is closed the voltage across the capacitor and the current through the
inductor cannot change instantaneously

Thus: vout (0+) = 0 and vR (0+) = i (0+) R = 0

di
Vin = vL ( 0+ ) = L
dt t =0+
Then:
Vin
= A( s1 − s2 )
L
Vin Vin
A= B= −
L ( s1 − s2 ) L ( s1 − s2 )

i(t) =
Vin
L ( s1 − s2 )
(e s 1t
− e s 2t )

di
vout = Vin − i R −L
dt

di Vin
where, = ( s 1 e s 1t − s 2 e s 2 t )
dt L ( s1 − s 2 )

vout = Vin −
Vin R
L ( s1 − s 2 )
(e s 1t
− e s 2t ) −
Vin
( s1 − s2 )
( s 1 e s 1t − s 2 e s 2 t )

⎡ e s 1t R e s 2t R ⎤
vout = Vin ⎢1 − ( + s 1) + ( + s 2) ⎥
⎣ ( s1 − s2 ) L ( s1 − s2 ) L ⎦

where, s1 = −α − α 2 − ω0 and s2 = −α + α 2 − ω0
2 2

s1 − s2 = −2 α 2 − ω0
2

9
 vout

w0- effect due to L

2

Vin

α - effect due to R

0 t

Case 1 is undershoot.

Case 2 is overshoot with dampening effect.

C. FREQUENCY-DOMAIN ANALYSIS OF PASSIVE NETWORKS

(i) RC Circuits

Integrator
R
Vout(s)
+ I(s)
Vin C
-

Since there is a switch in the circuit, Vin is considered a step function with respect to time
and it is valid for t > 0.
Thus, taking the Laplace transform of Vin yields:

∞ ∞
Vin
Vin ( s ) = ∫ Vin e dt = Vin ∫ e − st dt =
− st

0 0
s

10
Then, KVL dictates:

Vin ⎡
= I ( s) ⎢ R +
1 ⎤
= I ( s)
( sRC + 1)
s ⎣ ⎥
sC ⎦ sC

1 1 Vin sC
Vout ( s ) = I ( s ) =
sC sC s ( sRC + 1)
Vin 1
Vout ( s ) =
RC ⎛ 1 ⎞
s⎜s + ⎟
⎝ RC ⎠

1 A B ⎛ 1 ⎞ A
But, ≡ + A⎜ s + ⎟ + Bs ≡ 1 s ( A + B) + ≡1
⎛ 1 ⎞ s s+ 1 ⎝ RC ⎠ RC
s⎜s + ⎟
⎝ RC ⎠ RC
Thus:
A
A + B = 0 and = 1 yields
RC
A = RC and B = − RC
⎡ ⎤ ⎡ ⎤
⎢
Vin RC RC ⎥ ⎢ 1 1 ⎥
Vout ( s) = ⎢ − ⎥ = Vin ⎢ − ⎥
RC ⎢ s ⎛ 1 ⎞⎥ ⎢ s ⎛ 1 ⎞⎥
⎢⎣ ⎜s+ ⎟ ⎜s+ ⎟
⎝ RC ⎠ ⎥⎦ ⎢⎣ ⎝ RC ⎠ ⎥⎦
⎡ ⎤
⎢1 1 ⎥ ⎛ −
t
⎞
vout (t ) = Vin £ -1 ⎢ − ⎥ = Vin ⎜1 − e RC ⎟
⎢s ⎛s + 1 ⎞⎥ ⎝ ⎠
⎢⎣ ⎜ ⎟⎥
⎝ RC ⎠⎦

Differentiator
C

Vout (s)
I (s) R
+
Vin / s
-

Vin ⎡
= I ( s) ⎢ R +
1 ⎤
= I ( s )
( sRC + 1)
s ⎣ sC ⎥⎦ sC

11
 RC Vin Vin
Vout ( s ) = I ( s ) R = =
RC ⎛ 1 ⎞ ⎛ 1 ⎞
⎜s+ ⎟ ⎜s+ ⎟
⎝ RC ⎠ ⎝ RC ⎠
⎡ ⎤
⎢ 1 ⎥ −
t
vout (t ) = Vin £ -1 ⎢ =
1 ⎥
RC
V in e
⎢s + ⎥
⎣ RC ⎦

Homework:
Find vout(t) by performing frequency-domain analysis
C
Vout (s)

+
Vin / s
-

(ii) RLC Circuits

VL (s)
L
R
Vout (s)

I (s)
+
Vin / s
C
-

Assuming that vout(0) = 0 V and i(0) = 0.

Vin 1
= I ( R + sL + )
s sC
I
Vout =
sC
Vin 1
= sCVout ( R + sL + )
s sC

12
Vin
= Vout ( RCs + s 2 LC + 1)
s
1
Vout LC
=
R
Vin s ( s 2 + s + 1 )
L LC

R 1
Solving ( s 2 + s+ ) yields:
L LC
2
R ⎛ R ⎞ 1
s1,2 = − ± ⎜ ⎟ − or s1,2 = −α ± α 2 − ω0 2
2L ⎝ 2 L ⎠ LC
R 1
Where, α = and ω0 =
2L LC
1
Vout LC K M N
= ≡ + +
Vin s ( s − s1 )( s − s2 ) s ( s − s1 ) ( s − s2 )

( )
vout (t ) = K + Me s1t + Ne s2t Vin for t ≥ 0 .

s2 s − 2 s2
Where, K = 1 , M = and N = 1
s2 − s1 s2 − s1

13
(iii) STABILITY
Transfer Function

Vin(s) H(s) Vout(s)

Vout (s) = Vin (s) ⋅ H(s)

Vout (s)
H(s) =
Vin (s)
The transfer function, H(s), can be described as follows.
N(s)
H(s) =
D(s)
When N(s) = 0, the solution gives us the zeros.
When D(s) = 0, the solution gives us the poles and also tells us the stability of the circuit.

Poles

When solving for D(s) = 0, the solution should result in the following form:
s = α + ωj
where α is the real component and ω is the imaginary component. These solutions (there
could be more than one solution for s) can then be plotted real vs. imaginary.

14
Poles to the right of the imaginary axis shown as (0) and (1) are unstable causing the
resulting waveforms similar to the following:

Poles that lay on the imaginary axis shown as (2) are oscillatory causing waveforms
similar to the following:

15
Poles to the left of the imaginary axis shown as (3) and (4) are stable causing the
resulting waveforms similar to the following:

16
Example 1

We first transform the circuit with Laplace.

1
Vout (s) 1 1
H(s) = = sC = =
Vin (s) R+
1 sRC + 1 ⎛ 1 ⎞
RC ⎜ s + ⎟
sC ⎝ RC ⎠
Now, to find the pole(s).

⎛ 1 ⎞
N ( s ) = RC ⎜ s + ⎟=0
⎝ RC ⎠
−1
s=
RC

Plot this pole.

17
From the position of the pole, we know that the circuit is stable and the waveform would
look as follows:
vout

vin

0 t

Example 2

We first transform the circuit into s-domain with Laplace.

18
 1
Vout (s) sC 1
H(s) = = = 2
Vin (s) R + sL +
1 s CL + sRC + 1
sC
Now, to find the pole(s).

N ( s ) = s 2 CL + sRC + 1 = 0

2
− RC ± (RC )2 − 4CL ⎛ R ⎞
2 ⎛ 1 ⎞
− ⎜⎜ ⎟
R
s1,2 = =− ± ⎜⎜ ⎟⎟ ⎟⎟
2CL 2L ⎝ 2L ⎠ ⎜ CL
⎝ ⎠

s1 = −α 0 + α 0 − ω0
2 2

s2 = −α 0 − α 0 − ω0
2 2

where
R
α0 =
2L
1
ω0 =
LC
Assuming that L, R, and C are not zero and not negative there are three possible
solutions.
α 0 < ω0 Æ There is not imaginary part.
Plot these poles.

From the position of the pole, we know that the circuit is stable and the waveform would
look as follows:
vout

vin

0 t

19
α 0 = ω0 Æ There is not imaginary part.
Plot this pole.

From the position of the pole, we know that the circuit is stable and the waveform would
look as follows:
vout

vin

0 t
α 0 > ω0 Æ There is an imaginary part.
Plot these poles.

2 2
⎛ 1 ⎞ ⎛ R ⎞
⎜⎜ ⎟⎟ − ⎜ ⎟
⎝ CL ⎠ ⎝ 2 L ⎠

2 2
⎛ 1 ⎞ ⎛ R ⎞
− ⎜⎜ ⎟⎟ − ⎜ ⎟
⎝ CL ⎠ ⎝ 2L ⎠

20
From the position of the pole, we know that the circuit is stable and the waveform would
look as follows:

21
CHAPTER II. FUNDAMENTALS OF CMOS CIRCUITS
A. BRIEF THEORY OF SEMICONDUCTORS

INTRINSIC SEMICONDUCTOR

Si Si Si

electron

Si Si Si

Si Si Si

22
N-TYPE EXTRINSIC SEMICONDUCTOR

Si Si Si

extra
electron

Si As Si

Si Si Si

23
Si Si Si

free
positively charged electron
site (DONOR)

Si As Si

Si Si Si

24
P-TYPE EXTRINSIC SEMICONDUCTOR

Si Si Si

hole

Si B Si

Si Si Si

25
Si Si Si

negatively charged site

free electron (ACCEPTOR)

Si B Si

Si Si Si

26
 N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET)

VDS

VGS

metal gate

gate oxide
drain source

N+ N+

electron path
e e
e

bulk

27
 P-type Metal Oxide Semiconductor Field Effect Transistor (PMOSFET)

VSD

VSG

metal gate

source gate oxide drain

P+ P+

hole path
h h
h

bulk

VBS

28
B. MOSFET CHARACTERISTICS
(i) NMOSFET

ID Saturation
Quadratic

VGS
Linear

D
G ID
VDS
VDsat=VGS-VT
S

μ nCoxWn ⎡ VDS 2 ⎤
ID = ⎢(VGS − VTn ) VDS − ⎥
L ⎣ 2 ⎦

μ nCoxWn
ID ≅ ⎡⎣(VGS − VTn ) VDS ⎤⎦ linear region for small VDS
L

μ nCoxWn
ID = (VGS − VTn ) for VDS ≥ VDsat = VGS - VTn saturation region for large VDS
2

2L

(ii) PMOSFET

ID

VSG
D
G ID
VSD
S VSDsat=VSG - VT

μ pCoxWp ⎡ VSD 2 ⎤
ID = ⎢(V SG − V Tp ) V SD −
2 ⎥⎦
L ⎣
μ pCoxWp
ID ≅ ⎡⎣(VSG − VTp ) VSD ⎤⎦ linear region for small VSD
L
μ pCoxWp
ID = (VSG − VTp ) for VSD ≥ VSDsat = VGS -VTp saturation region for large VSD
2

2L

29
C. LARGE SIGNAL EQUIVALENT CIRCUIT OF MOSFETS
(i) NMOSFET LARGE SIGNAL EQUIVALENT CIRCUIT

For small VDS ⇒

VDS

Rn
ID
VDS 1
Rn = =
μ nCoxWn
ID
(VGS − VTn )
L
1 μ nCoxWn
Rn = where Kn ≅
Kn (VGS − VTn ) L

For large VDS ⇒

Kn
I Dsat = (VGS − VTn )
2

1
If VGS =VDD & VTn ≅ 0.2VDD then: Rn = & I DSAT = 0.32KnVDD 2
0.8 KnVDD

(ii) PMOSFET LARGE SIGNAL EQUIVALENT CIRCUIT

For small VSD ⇒

VSD

ID Rp
1 μ pCoxWp
Rp = where Kp =
Kp (VSG − VTp ) L

For large VSD ⇒

Kp
(VSG − VTp )
2
I DSAT =
2

30
D. Complementary MOS (CMOS) Inverter Static Characteristics

VDD
VDD - vin vin(t)
S ID
G
D
vout VDD
+ D
vin G
- S

0 t

(i) For Small values of vin (t)

ID ID

VSGp = VDD-vin

VGSn = vin
vout = VDSn VDD - vout = VSDn
Overlapping these two curves on top of each other yields:
vout = VDSn = VDD when VSDp = 0
vout = 0 when VSDp = VDD

ID

VGSp = VDD - vin

1
VGSn = vin
0 vout
VDD
1
At pfet is in linear region
nfet is in saturation region

31
 Rp
vout
IDSAT

1 1
v out = VDD - RpI DSAT where Rp = =
Kp ( VSGp -VTp ) Κp ( VDD -v in -VTp )

Kn Kn
I DSAT = (VGSn − VTn ) = ( vin − VTn )
2 2

2 2
Kn ( vin − VTn )
2

vout = VDD −
2 Kp (VDD − vin − VTp )

(ii) For some intermediate value of vin(t)

ID

VSGp = VDD - vin 2 VGSn = vin

vout

At 2 both pfet & nfet are in saturation region

ISDSAT
vout
IDSSAT

32
 Kp
(VSGp − VTp )
2
I SDSAT =
2
Kn
= (VGSn − VTn )
2
I DSSAT
2
Kp (VGSn − VTn )
2

But , I SDSAT = I DSSAT gives =

Kn (VSGp − VTp )2
Substituting VGSn = vin and VSGp = VDD - vin
Kp
=
( vin − VTn )
Kn (VDD − vin − VTp )

μ pCoxWp μ nCoxWn
We had Kp = and Kn =
L L
μ pWp vin − VTn
=
μ nWn VDD − vin − VTp

Assume that μ n ≅ 2μ p & VT = VTn = VTp

μ p Wp v −V Wp
= = in
=R T

2 μ pWn V − v − VDD
2Wn in T

vin − VT = R (VDD − vin − VT ) yields vin (1 + R ) = VT (1 − R ) + RVDD

R (VDD − VT ) + VT
vin =
1+ R
VDD
if Wp = 2Wn ⇒ R=1 ⇒ vin =
2
if Wp = Wn ⇒ R=0.71 ⇒ vin ≅ 0.41VDD

(iii) For large values of vin(t)

ID

VGSn = vin
3 VSGp = VDD-vin
0 vout

33
At 3 nfet is in linear region
pfet is in saturation region

ISDSAT
vout
Rn

v out =Rn ISDSAT

1 1
Where, Rn= =
Kn (VGSn − VTn ) Kn ( vin − VT )
Kp
(VSGp − VTp ) =
Kp
(VDD − vin − VTp )
2 2
I SDSAT =
2 2
Kp (VDD − vin − VTp )
2

v out =
2Kn ( vin − VTn )
Plotting vout in terms of vin yields:
vout

“ BELL CURVE ”

VDD/2 VDD vin

For vin < VDD/2

Kn ( vin − VTn )
2

v out = VDD −
2 Kp (VDD − vin − VTp )

Kp (VDD − vin − VTp )

2

For vin > VDD/2 v out =

2Kn ( vin − VTn )

34
 ID

VSGp VGSn
2
VSGp VGSn

3
VSGp 1 VGSn
VDD vout
As vin approaches from 0 to VDD then the quiescent point (operating point) of the the
inverter transverses the DASHED ARC from 1 to 3 through 2 in ID vs. vout curve.
As vin approaches from VDD to 0, the quiescent point of the inverter follows the
DASHED ARC from 3 to 1 .
Wp
Now, let’s plot the BELL CURVE for different values of :
Wn

Wp
Wn vin at 2
1 0.41 VDD
2 0.5 VDD
3 0.55 VDD
4 0.58 VDD
6 0.63 VDD
0.41VDD

0.63VDD
0.5VDD

Observe the following:

Wp
• When = 1 (strong nfet weak pfet) small increases in vin quickly turns the nfet
Wn
on, and vout starts decreasing towards 0.

35
 Wp
• When = 6 (strong pfet weak nfet) large increases in vin cannot turn on the nfet,
Wn
vout delays to decrease towards 0.

E. NOISE MARGIN OF THE INVERTER

Noise margin of the inverter is defined as the value of the input voltage, vin, at
dvout
= −1 .
dt

Thus, from the BELL curve:

dvout
= −1
dt

Wp/Wn=2

d v ou t
= −1
dt

VIL VIH VDD

v in
NML NMH

v out dvout
= −1
dt

Wp/W n=1

d v ou t
= −1
dt

VIL VIH VDD

v in
NML NMH
VDD
0V

Positive glitch Negative glitch

t t

36
When nfet is stronger with respect to pfet (Wp/Wn=1) in an inverter, then small input
voltages at vin can easily turn on the nfet. Therefore, the inverter with Wp/Wn=1 has low
noise margin or noise immunity for positive glitches at its input. But, the same inverter
exhibits high noise immunity for negative glitches at its input.

dvout
v out = −1
dt

Wp/W n=6

d v ou t
= −1
dt

VIL VIH VDD

vin
NML NMH
VDD
0V

Positive glitch Negative glitch

For an inverter with Wp/Wn=6, the inverter exhibits high noise immunity for positive
glitches & low noise immunity for negative glitches.

F. CMOS Inverter Dynamic Characteristics

If vin is changed from 0 to VDD without any transition time (rise time = 0 sec), the pfet is
turned OFF, and nfet is put in the linear region and shows resistive characteristics.

pfet is OFF

vout
Rn

1
When vin = VDD ⇒ Rn ≅
Kn (VDD − VTn )

37
 1
Assume VTn ≅ 0.2VDD Rn ≅
0.8KnVDD

Now, if vin is switched back from VDD to 0 without any transition time, this time nfet is
turned off and pfet is put in the linear region and shows resistive characteristics.

Rp
vout

nfet is OFF

1
when vin=0 ⇒ Rp ≅
Kp (VDD − VTp )

1
Assume VTp ≅ 0.2VDD and Rp ≅
0.8KpVDD
This analysis aids to derive the propagation delay of the inverter with a load capacitor,
CL, at its output.

VDD
VDD - vin
S ID
G
D
vout
+ D
CL
vin G
- S

When vin changes from 0 to VDD, then nfet turns ON and pfet turns OFF.

38
 Vout(0) = VDD

Rn CL
t
−
vout = VDD e RnCL

vin,vout

vin(t) is a step function

VDD

vout(t)
VDD/2 TpL

0 t
TpL

TpL
−
VDD
vout = = VDD e nCL
R
2

TpL = RnCL ln2 =0.69 RnCL (low-going propagation delay)

When vin goes from VDD to 0, then nfet is turned OFF and pfet is turned ON.

Rp
Vout (0) = 0

CL

t
−
vout = VDD (1 − e RpCL
)

39
 vin,vout

vout(t)

vin(t) VDD/2

0 t
TpH

TpH = 0.69 RpCL (high-going propagation delay)

Wp
Example: Compare TPL & TPH for = 1, 2, 4 (assume VT = VTn = VTp= 0.2VDD)
Wn
1 1
Solution: Rn = =
Kn(VDD − VT ) 0.8VDD Kn
1
Rp =
0.8VDD Kp
Where,
μ nCoxWn
Kn =
L
μ pCoxWp
Kp =
L
0.86CL 0.86CL
TPL = 0.69 RnCL = = L
VDD Kn VDD 2μ pCoxWn
0.86CL 0.86CL
TPH = = L
VDD Kp VDD μ pCoxWp

Let;
0.86CL M
M= L ⇒ TPL =
VDD μ pCox 2Wn
M
TPH =
Wp
For
Wp M M T
= 1 (strong nfet, weak pfet) ⇒ TPL = , TPH = ⇒ TPL = PH
Wn 2Wn Wn 2
Wp M M
= 2 (equal nfet and pfet) ⇒ TPL = , TPH = ⇒ TPL = TPH
Wn 2Wn 2Wn

40
Wp M M
= 4 (weak nfet, strong pfet) ⇒ TPL = , TPH = ⇒ TPL = 2TPH
Wn 2Wn 4Wn

FANOUT

Cin

Fanout of a gate (inverter in this case) is the number of identical gates at the output of this
gate.

Thus = CL =N Cin where N = fanout.

Therefore,
TPL = 0.69 RnCL = 0.69 N RnCin
TPH = 0.69 RpCL = 0.69 N RpCin

Tp
TPH = 0.69 RpCL

TPL = 0.69 RnCL

CL

IMPORTANT OBSERVATION

Tp changes linearly with CL. That means more output capacitance (fan-out) linearly
produces propagation delay.

Note that, Tp= 0 when CL =0 F. However, this is impossible because every inverter has an
intrinsic load capacitor due to source/drain contact capacitance even though the external
load capacitor, CL, may not exist. Therefore, if one assumes CL as a physical capacitance
due to gate fanout or wiring, the practical Tp vs CL will be as follows.

41
 Tp
TpL

TpH

TpL0
TpH0

CL

G. Rise Time & Fall Time

vin,vout

V DD
0.9V
DD

v (t)
in
v o ut(t)=VDD (1-e-t/Rp CL)

0.1VDD
0 t
t
1
t
2

TRise
⎛ −
t1 ⎞
⎜ RpCL ⎟
vout t =t 1
= 0.1 VDD = VDD ⎜1 − e ⎟
⎜ ⎟
⎝ ⎠
t1
−
0.1 − 1 = −e RpCL

t1 = − RpCL ln 0.9= 0.1RpCL

42
 ⎛ −
t2 ⎞
⎜ ⎟
vout t =t 2
= 0.9 VDD = VDD ⎜ 1 − e pCL
R
⎟
⎜ ⎟
⎝ ⎠
t2
−
0.9 − 1 = −e pCL
R

t2 = − RpCL ln 0.1= 2.3 RpCL

TRISE = t2 - t1 = 2.2 RpCL

v ,v
in ou t

v (t)
in

V DD

0.9VDD
v ou t(t)=VDD (e -t/R n C L)

0.1VDD
0
t 1 t 2
t
T FALL

⎛ − t1 ⎞
⎜ ⎟
vout t =t 1 = 0.9 VDD = VDD ⎜ e RnCL ⎟
⎜ ⎟
⎝ ⎠
t1 = − RnCL ln 0.9= 0.1 RnCL

⎛ − t2 ⎞
⎜ ⎟
vout t =t 2 = 0.1VDD = VDD ⎜ e RnCL ⎟
⎜ ⎟
⎝ ⎠
t2 = − RnCL ln 0.1= 2.3 RnCL

TFALL =2.2 RnCL

Wp
Example: Compare TRISE, TFALL for = 1 , 2 and 4. Assume VT ≈ 0.2VDD
Wn

43
 1 1
Solution: Rn = & Rp =
0.8VDD Kn 0.8VDD Kp

μ nC Wn 2μ pCoxWn
Kn = ox
=
L L
μ pC Wp
Kp = ox

1 1 1 1
Rn = Rp =
0.8VDD μ nCox 2Wn 0.8VDD μ pCox Wp

L P
P
Let P then Rn = & Rp =
0.8VDD μ pCox 2Wn
Wp
Wp 1 1
For = 1 then TRISE =(2.2 C L P) and TFALL =(2.2 CL P)
Wn Wn 2Wn
T
therefore TRISE = FALL
2
Wp 1 1
For = 2 then TRISE =(2.2 C L P) and TFALL =(2.2 CL P)
Wn 2Wn 2Wn
therefore TRISE = TFALL

Wp 1 1
For = 4 then TRISE =(2.2 C L P) and TFALL =(2.2 CL P)
Wn 4Wn 2Wn
therefore 2TRISE = TFALL

H. Power Consumption

vout
i (t)
CL

T
1
T ∫0
P= i (t )vout (t )dt power spent to charge CL.

dvout
i = CL
dt
Then,

44
 T
1 dv
P= ∫ CL out vout (t ) dt
T0 dt

CL vout 2 CL VDD 2
= =
VDD
0
T 2 T 2

Therefore,

Power changes LINEARLY with CL and QUADRATICALY with VDD.

If we have a periodic input waveform:

vin

VDD

0 Tperiod t
Tperiod
2
1
⎛ Tperiod ⎞ ∫0
P1 = CL vout dvout
⎜ ⎟
⎝ 2 ⎠
Tperiod
1
P2 = ∫ CL vout dvout
⎛ Tperiod ⎞ Tperiod
⎜ ⎟ 2
⎝ 2 ⎠
CL VDD 2 1
P = P 1 + P2 = = CL VDD 2 f
Tperiod 2 2

Therefore power changes LINEARLY with frequency.

vout

VDD
P1 P2

0 Tperiod/2 Tperiod/2 t

45
I. TECHNOLOGY SCALING
Example: Compare 0.5µ technology with tox=100A , 3.3V @ 100 MHz
with 0.1µ technology with tox=50A , 1V @ 5 GHz.
Wp
Keep = K the same in both technologies.
Wn

Solution:

CL = Cox (Wn + Wp ) L = Cox ( K + 1)Wn L

ε ε ( K + 1)
Cox = ox
⇒ CL = ox
Wn L
tox tox

ε ( K + 1)
For 0.1µ CL =0.1u = ox
Wn (0.1μ )
50 A0

ε ( K + 1)
0.5µ CL =0.5u = ox
5Wn (0.5μ )
100 A0

1
PL=0.1u = CL =0.1uVDD 2 L=0.1u f L=0.1u
2
1 ε ox ( K + 1)
= 0
Wn (0.1μ ) (1V) 2 (5000MHz )
2 50 A
1 ε ox ( K + 1)
PL=0.5u = 0
5Wn (0.5μ ) (3.3V) 2 (100 MHz )
2 100 A
PL=0.1u ⎛ 100 A0 ⎞ ⎛ 1 ⎞ ⎛ 0.1μ ⎞ ⎛ 1V ⎞ ⎛ 5000 MHz ⎞
2

=⎜ ⎟⎜ ⎟⎜ ⎟⎜ ⎟ ⎜ ⎟ = 0.368
PL=0.5u ⎝ 50 A0 ⎠ ⎝ 5 ⎠ ⎝ 0.5μ ⎠ ⎝ 3.3V ⎠ ⎝ 100 MHz ⎠

Therefore, there is room to increase VDD.

46
CHAPTER III. CMOS LOGIC

A. CMOS GATE STRUCTURE

in 1
Complementary
pfet tree
in k

out

nfet tree

The nfet tree is formed between the output & ground to produce a logic function at the
output. The pfet tree is formed between VDD & output to replicate the complementary
version of the nfet tree.
In a pfet tree, parallel nfet interconnects are converted into serial pfet interconnects and
serial nfet interconnects are converted into parallel pfet interconnects.

(i) 2-Input NAND Gate

A B

outNAND
A

A B outNAND Comments
0 0 1 pfetA on, pfetB on
0 1 1 pfetA on only
1 0 1 pfetA on only
1 1 0 nfetA on, nfetB on

47
(ii) 2-Input NOR Gate

B
outNOR
A B

A B outNOR Comments
0 0 1 pfetA on, pfetB on
0 1 0 nfetA on only
1 0 0 nfetA on only
1 1 0 nfetA on, nfetB on

B. Building Complex Function Gates

Example: out= D + A( B + C )

Form nfet tree first:

out

A D

B C

48
Form pfet tree second:

B A

D
out

Combine nfet & pfet Trees

B A

D
out

A D

B C

Example:

A
0
out
1
B

EN out = A.EN + B.EN

49
First obtain out = A.EN + B.EN

A EN

out
A B B EN

EN EN

out

nfet-tree pfet-tree

Now combine nfet tree, pfet tree &inverters to form out.

A EN

B EN

out

A B

EN EN

50
C. Fundamentals of Transistor Sizing

Transistor sizing is achieved by determining the maximum charge & discharge paths.

(i) Inverter

wp charge path

in

wn CL
discharge path

P P
Rn= and Rp=
2Wn Wp

TPH =0.69 RpC L (rise delay)

TPL =0.69 RnC L (fall delay)

If we want TPH=TPL (relative)

Then,
0.69 RpC L =0.69 RnC L ⇒ Rp= Rn
Or Wp=2Wn

(ii) 2- Input NAND Gate

A B charge path

Wp Wp
out
A Wn CL

discharge path
B Wn

51
From critical charge path:

TPH = 0.69 C L Rpeq (rise delay)

TPL = 0.69 C L Rneq (fall delay)

P
Rpeq = Rp =
Wp
P P
Rneq = Rn + Rn = 2 =
2Wn Wn

(i) If we want TPH = TPL ⇒ Rpeq = Rneq

P P
= ⇒ Wp = Wn
Wp Wn
Thus:

A B
Wn Wn
out
A Wn CL

B Wn

(ii) If we want TPH =2TPL ⇒ Rpeq=2Rneq

P P Wn
=2 ⇒ Wp=
Wp Wn 2

52
(iii) 3-Input NAND Gate

A B C charge path

Wp Wp Wp
out
A Wn CL

discharge path
B Wn

C Wn

TPH =0.69 CL Rpeq (rise delay)

TPL =0.69 C L Rneq (fall delay)

P
Rpeq = Rp =
Wp
P
Rneq = Rn + Rn + Rn = 3
2Wn
P 3 P
Therefore, if we want TPH = TPL ⇒ Rpeq = Rneq ⇒ =
Wp 2 Wn
2
Wp= Wn
3

(iv) 2- Input NOR Gate

A Wp

charge path
B Wp

out

CL
A B discharge path

Wn Wn

53
 TPH = 0.69 C L Rpeq (rise delay)
TPL = 0.69 C L Rneq (fall delay)

2P
Rpeq = Rp + Rp =
Wp
P
Rneq = Rn =
2Wn

TPH = TPL ⇒ Rpeq = Rneq

2P P
=
Wp 2Wn

Wp = 4Wn

(v) out = D + A ( B + C )

54
 TPH = 0.69 C L Rpeq (rise delay)
TPL = 0.69 C L Rneq (fall delay)

3P
Rpeq = Rp + Rp + Rp = 3Rp =
Wp
P P
Rneq = Rn + Rn = 2Rn = 2 =
2 Wn Wn
3P P
If we want TPH = TPL ⇒ Rpeq = Rneq ⇒ =
Wp Wn

Wp=3Wn

To find Wp2, Wn2 and Wn3 :

P P 2P
Rp2 = 2Rp = 2 ⇒ =
Wp Wp2 Wp
Wp 3
Wp2 = = Wn
2 2
Rn2 = Rn ⇒

Wn2 = Wn
P P P P
Rn3 = Rn + Rn = 2 = ⇒ =
2 Wn Wn 2Wn3 Wn
Wn
Wn3 =
2

Therefore, all the other charge and discharge paths will be equal to the critical charge and
discharge paths, respectively.

55
D. MORE ACCURATE DELAY CALCULATION, ELMORE DELAY
When we were calculating TpH & TpF earlier, we did not take the intrinsic source/drain
capacitances in the delay calculation. Elmore delay calculation considers these intrinsic
capacitances in the following manner:

nfet tree:
out

M1
CL+C1

C2
M2

C3
M3

CN

MN

TpL = 0.69{(CL + C1 ) ( Rn1 + Rn 2 + Rn 3.......... + RnN )

+C2 ( Rn 2 + Rn 3 + Rn 4.......... + RnN )
+C3 ( Rn 3 + Rn 4 + Rn 5......... + RnN )
+...........
+CN RnN}

56
pfet tree:

C0
N1

C1
N2

C2
N3

C(K-1)

NK

out
CL+CK

TpH = 0.69{0.C 0
+ Rp1C1
+ ( Rp1 + Rp 2 ) C 2
+ ( Rp1 + Rp 2 + Rp 3 ) C 3
+.........
+ ( Rp1 + Rp 2 + ....... + Rpk ) (CL + CK )}

57
Example: Determine Elmore delays for 2 NAND with intrinsic S/D capacitance, Ci.
Let Ci be the capacitance per transistor width.
For practical purposes, each transistor has a separate Ci at its source and drain junctions.

A B charge path

out
A CL+(2Wp +Wn )Ci
discharge path

B 2Wn Ci

TpH = 0.69(CL + Ci (2W p + Wn )) Rp

TpL = 0.69 ⎡⎣ (CL + Ci (2W p + Wn )) ( Rn + Rn ) + 2CW
i
⎤
n Rn ⎦

58
Example: Determine Elmore delays for 4 NAND with intrinsic S/D cap=Ci

A B C D

out
A (4Wp +W n )Ci CL

B 2W n Ci

2W n Ci
C

2W n Ci
D

TpH = 0.69(CL + (4W p + Wn )Ci ) Rp

TpL = 0.69{(CL + (4W p + Wn )Ci ) ( Rn + Rn + Rn + Rn )
+2WnCi ( Rn + Rn + Rn )
+2WnCi ( Rn + Rn )
+2WnCi Rn}
TpL = 0.69 Rn(CL + 16(W p + Wn )Ci )

If we want:

TpH = TpL ⇒ (CL + (4W p + Wn )Ci ) Rp = (CL + 16(W p + Wn )Ci ) Rn

P P
Rp = , Rn = and Wn = W
Wp 2Wn
−(8WCi + CL ) + (8WCi + CL )2 + 128WCi (CL + WCi )
Wp =
32Ci
Wn
If Ci → 0 ⇒ Wp = as expected.
2

59
Example: Determine Elmore delays for 2 NOR with intrinsic S/D cap=Ci.

A Wp

B 2Wp Ci
Wp
charge path

out
CL+ (Wp +2Wn )Ci
A B
discharge path
Wn Wn

TpH = 0.69 ⎡⎣ 2 RpW p Ci + ( Rp + Rp ) [CL + (W p + 2Wn )Ci ]⎤⎦

TpL = 0.69[CL + (W p + 2Wn )Ci ]Rn

60
Example: Determine Elmore delays for Out = D + A ( B + C )

B Wp A Wp

2Wp Ci
C Wp

3Wp Ci
D Wp
out
CL+Ci(2Wn +Wp )
A Wn D Wn

3Wn Ci

B Wn C Wn

TpH = 0.69 ⎡⎣ 2 RpWpCi + 3 ( Rp + Rp ) WpCi + ( Rp + Rp + Rp ) (CL + Ci (2Wn + W p )) ⎤⎦

TpL = 0.69 ⎡⎣( Rn + Rn ) (CL + Ci (2Wn + W p )) + 3RnWnCi ⎤⎦

61
E. INTERCONNECT DESIGN STRATEGIES TO REDUCE ELMORE
DELAYS
Consider out = ( A + B + C ) D . There are 2 ways to implement this:

B D

A
out
CL+(2Wp+Wn)Ci
D

4WnCi
A B C

Implementation #1

B D

A
out

A CL+(2Wp+3Wn)Ci
B C

4WnCi
D

Implementation #2

TPL1 = 0.69 {[CL + (2W p + Wn )Ci ]( Rn + Rn) + 4WnCi Rn}

TPL 2 = 0.69 {[CL + (2W p + 3Wn )Ci ]( Rn + Rn) + 4WnCi Rn}

Therefore, TPL1 < TPL2. Therefore, choose the implementation #1

62
CHAPTER IV. PASS-TRANSISTOR LOGIC

A. ISSUES WITH PASS TRANSISTOR LOGIC

(i) Problem with nfet
ID
VG = VDD
1
VDD VGS = V DD
VGS
2
vout(0) = 0 VGS = VDD/2
ID CL
3 VGS = VT
VDS
VT VDD /2 V DD

vout = VDD -V T v out= VDD/2 v out= 0

When VG = VDD and VD = VDD are applied to the nfet in the above circuit, the initial
voltage across the load capacitor, CL, is zero. Therefore, initially VGS = VDD and VDS =
VDD. This condition induces a maximum current through the nfet (case 1). As this
current charges the output capacitor, CL, and the output voltage rises, the current through
the nfet declines steadily (case 2). When vout = VDD - VT, the current through the nfet
reaches sub-threshold level, which is practically zero (case 3).
Therefore, a logic 1 is applied to the drain (input) of an nfet, one can never reach the full
VDD at the source (output); the maximum attainable value is always VDD - VT.

Final form:

VG = VDD
VDD
VT
vout = VDD - VT
ID= 0 CL

63
Any problem if we apply ground instead of VDD?

ID
VG = VDD
2 1
VGS VGS = VDD

vout = VDD
ID CL
3
VDS
VT VDD /2 VDD

v out = 0 v out= V DD/2 v out= V DD

With the above bias across the nfet, output capacitor is discharged completely, and vout
reaches 0 since VGS = VDD at all times. Therefore, if a logic 0 is applied to the source
(input) of an nfet, a logic zero is obtained at the drain (output).

(B) Problem with pfet

ID
VG = 0
1
VSG VSG = VDD
2
vout(0) = VDD VSG = VDD /2

ID CL
3 VSG = VT
VSD
VT V DD /2 V DD

vout = VT vout = V DD /2 vout = VDD

When VG = 0 and vout(0) = VDD are applied to the pfet in the above circuit, the initial VSG
= VDD and VSD = VDD. This condition induces a maximum current through the pfet (case
1). As this current discharges the output capacitor, CL, and the output voltage decreases,
the current through the nfet declines steadily (case 2). When vout = VT, the current
through the pfet reaches sub-threshold level, which is practically zero (case 3).
Therefore, a logic 0 is applied to the drain (input) of a pfet, one can never reach 0 at the
source (output); the minimum attainable value is always VT.

64
Any problem if we apply VDD instead of 0 ?
ID
VSG VG = 0
2 3
V SG = VDD

vout (0) = 0
ID CL
1
VSD
0 V DD /2 VDD

vout = VDD vout = VDD /2 vout = 0

With the above bias across the pfet, output capacitor gets charged completely, and vout
reaches VDD since VSG = VDD at all times. Therefore, if a logic 1 is applied to the source
(input) of a pfet, a logic 1 is obtained at the drain (output).

CONCLUSIONS:

(1)
VDD VDD
VDD
VDD - VT 0
ON ON
CL CL

result: nfet transmits logic 0 OK when it is ON.

(2)
0 0

VDD VDD
ON CL ON CL

result: pfet transmits logic 1 OK when it is ON.

Because of the level shifting problem in nfet and pfet for VDD and 0, respectively,
transmission gate is developed.

65
B. TRANSMISSION GATES
The transmission gate is the parallel combination of nfet and pfet with an inverter.

out = out =
A A
AB AB

Example: out = A ⊕ B = AB + AB

AB
A

out = A B + A B B out = A B + A B
A
B

B A
AB

What about out = ABC ?

66
 AB
A
out = A B C

B C
Even though one gets a functionally correct output, one of the biggest drawbacks of serial
transmission gate is that it generates a “slow node” at the output due to high series
resistance. The charge path:

The change path:

W peq Rp Rp
vout

CL
Rn Rn

Where,
P
Rp =
Wp
P
Rn =
2Wn
Rn R p P
=
Rn + R p W p + 2Wn
R p Rn 1 2
TRISEslow = 2.2CL ( Rpeq + 2 ) = 2.2CL P( + )
R p + Rn Wpeq W p + 2Wn

The discharge path:

Rp Rp
vout

CL
Rn Rn
W neq

1 2
TFALLslow = 2.2CL P( + )
2Wneq W p + 2Wn

67
 1
Therefore, more serial transmission gate induces more - term, which results in
W p + 2Wn
generating slower output node at vout.

To prevent the slow node formation signals need to be buffered by going to the gate of
the next transistor rather than its drain (or source):

AB
A

C out = A B C

W peq Rp W peq Rp
vab vout

Cinv+Cnox CL
Rn Rn

1 1
TRISEab = 2.2 P (Cinv + Cnox )( + ) < TRISEslow
W peq W p + 2Wn
1 1
TRISEout = 2.2 P (Cinv + Cnox )( + ) < TRISEslow
W peq W p + 2Wn
Similarly,
1 1
TFALLab = 2.2CL P( + ) < TFALLslow
2Wneq W p + 2Wn
1 1
TFALLout = 2.2CL P( + ) < TFALLslow
2Wneq W p + 2Wn

68
Example: Full adder design using transmission gates

Sum = A ⊕ B ⊕ Cin = A ⊕ B ⊕ Cin = ( A ⊕ B)Cin + ( A ⊕ B)Cin

Thus,
Sum = ( AB + AB)Cin + ( AB + AB)Cin
Cout = AB + Cin ( A ⊕ B ) = AB + Cin ( AB + AB)

A
AB+AB
B
Cin
A

SUM
A
AB+AB
B
Cin
A

Cin

Cout

69