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DATA SHEET
TDA8358J
Full bridge vertical deflection output
circuit in LVDMOS with east-west
amplifier
Product specification 1999 Dec 22
File under Integrated Circuits, IC02
Philips Semiconductors Product specification
1999 Dec 22 2
Philips Semiconductors Product specification
ORDERING INFORMATION
TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
TDA8358J DBS13P plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6
BLOCK DIAGRAM
13 11 3 9
COMP. GUARD
CIRCUIT CIRCUIT
M5
D2
D3
M2
Vi(p-p)
D1
VI(bias) 10 OUTA
INA 1
M4
0
INPUT 12
FEEDB
AND
FEEDBACK
Vi(p-p) CIRCUIT
VI(bias) INB 2 M1
4 OUTB
0
M3
TDA8358J
Ii(p-p)
II(av)
INEW 5 M6 8 OUTEW
0
6 7 MGL866
VGND EWGND
1999 Dec 22 3
Philips Semiconductors Product specification
INEW 5
Flyback supply
1999 Dec 22 4
Philips Semiconductors Product specification
Damping resistor compensation The east-west amplifier is a current driver sinking the
current of a diode modulator circuit. A feedback
HF loop stability is achieved by connecting a damping resistor REWF (see Fig.4) has to be connected between
resistor RD1 (see Fig.4) across the deflection coil. the input and output of the inverting east-west amplifier in
The current values in RD1 during scan and flyback are order to convert the east-west correction input current into
significantly different. Both the resistor current and the an output voltage. The output voltage of the east-west
deflection coil current flow into measuring resistor RM, circuit at pin OUTEW is given by:
resulting in a too low deflection coil current at the start of
the scan. Vo Ii REWF + Vi
The difference in the damping resistor current values The maximum output voltage is Vo(max) = 68 V, while the
during scan and flyback have to be externally maximum output current of the circuit is Io(max) = 750 mA.
compensated in order to achieve a short settling time.
1999 Dec 22 5
Philips Semiconductors Product specification
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VP supply voltage 18 V
VFB flyback supply voltage 68 V
VVGND-EWGND voltage difference between 0.3 V
pins VGND and EWGND
Vn DC voltage
pins OUTA and OUTEW note 1 68 V
pin OUTB VP V
pins INA, INB, INEW, GUARD, 0.5 VP V
FEEDB, and COMP
In DC current
pins OUTA and OUTB during scan (p-p) 3.2 A
pins OUTA and OUTB at flyback (peak); t 1.5 ms 1.8 A
pins INA, INB, INEW, GUARD, 20 +20 mA
FEEDB, and COMP
pin OUTEW 750 mA
Ilu latch-up current input current into any pin; +200 mA
pin voltage is 1.5 VP; Tj = 150 C
input current out of any pin; 200 mA
pin voltage is 1.5 VP; Tj = 150 C
Ves electrostatic handling voltage machine model; note 2 300 +300 V
human body model; note 3 2000 +2000 V
PEW east-west power dissipation note 4 4 W
Ptot total power dissipation 15 W
Tstg storage temperature 55 +150 C
Tamb ambient temperature 25 +75 C
Tj junction temperature note 5 150 C
Notes
1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.
2. Equivalent to 200 pF capacitance discharge through a 0 resistor.
3. Equivalent to 100 pF capacitance discharge through a 1.5 k resistor.
4. For repetitive time durations of t < 0.1 ms or a non repetitive time duration of t < 5 ms the maximum (peak) east-west
power dissipation PEW(peak) = 15 W.
5. Internally limited by thermal protection at Tj 170 C.
THERMAL CHARACTERISTICS
In accordance with IEC 747-1.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-c) thermal resistance from junction to case 4 K/W
Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W
1999 Dec 22 6
Philips Semiconductors Product specification
CHARACTERISTICS
VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb = 25 C; measured in test circuit of Fig.3; unless otherwise
specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VP operating supply voltage 7.5 12 18 V
VFB flyback supply voltage note 1 2VP 45 66 V
Iq(P)(av) average quiescent supply current during scan 10 15 mA
Iq(P) quiescent supply current no signal; no load 55 75 mA
Iq(FB)(av) average quiescent flyback supply during scan 10 mA
current
Inputs A and B
Vi(dif)(p-p) differential input voltage note 2 1000 1500 mV
(peak-to-peak value)
VI(bias) input bias voltage note 2 100 880 1600 mV
II(bias) input bias current 25 35 A
Outputs A and B
Vloss(1) voltage loss first scan part note 3
Io = 1.1 A 4.5 V
Io = 1.6 A 6.6 V
Vloss(2) voltage loss second scan part note 4
Io = 1.1 A 3.3 V
Io = 1.6 A 4.8 V
Io(p-p) output current (peak-to-peak value) 3.2 A
LE linearity error Io(p-p) = 3.2 A; notes 5 and 6
adjacent blocks 1 2 %
non adjacent blocks 1 3 %
Voffset offset voltage across RM; Vi(dif) = 0 V
VI(bias) = 200 mV 15 mV
VI(bias) = 1 V 20 mV
Voffset(T) offset voltage variation with across RM; Vi(dif) = 0 V 40 V/K
temperature
VO DC output voltage Vi(dif) = 0 V 0.5VP V
Gv(ol) open-loop voltage gain notes 7 and 8 60 dB
f3dB(h) high 3 dB cut-off frequency open-loop 1 kHz
Gv voltage gain note 9 1
Gv(T) voltage gain variation with 104 K1
temperature
PSRR power supply rejection ratio note 10 80 90 dB
1999 Dec 22 7
Philips Semiconductors Product specification
V max V min
b) LE = ------------------------------- 100% (non adjacent blocks)
V avg
1999 Dec 22 8
Philips Semiconductors Product specification
6. The linearity errors are specified for a minimum input voltage of 300 mV single-ended. Lower input voltages lead to
voltage dependent S-distortion in the input stage.
V OUTA V OUTB
7. G v ( ol ) = -------------------------------------------
-
V FEEDB V OUTB
10. VP(ripple) = 500 mV (RMS value); 50 Hz < fP(ripple) < 1 kHz; measured across RM.
11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA.
12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND.
13. Measured for REWF = 10 k; REWL = 30 ; Vo = 6 V.
a) For Io = 100 mA and a voltage of 9 V at REWL connected to the line output transformer, the east-west amplifier
input current (see Fig.4) is Ii = 300 A.
b) For Io = 500 mA and a voltage of 21 V at REWL connected to the line output transformer, the east-west amplifier
input current (see Fig.4) is Ii = 350 A.
1999 Dec 22 9
Philips Semiconductors Product specification
APPLICATION INFORMATION
COMP. GUARD
CIRCUIT CIRCUIT
M5
Vi(p-p)
D2
D3
VI(bias)
M2
0
I I(bias) D1
10 OUTA
INA 1
RCV1 M4 RL
2.2 k RS 3.2
(1%) INPUT 12 FEEDB
AND 2.7 k
I i(dif)
FEEDBACK
CIRCUIT
CM RM
I I(bias) 10 nF 0.5
INB 2 M1
RCV2 4 OUTB
2.2 k
(1%) M3
Vi(p-p)
TDA8358J
VI(bias)
Ii
INEW 5 M6 8 OUTEW
0 to line output
REWL transformer
Ii(p-p) Ii 30
6 7
1999 Dec 22 10
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1999 Dec 22
Philips Semiconductors
in LVDMOS with east-west amplifier
Full bridge vertical deflection output circuit
VP = 14 V
RGRD
2.7 H(3) RFB
5.6 k Vfb = 30 V
COMP GUARD VP VFB 10
13 11 3 9 C3 C1 C4 C2
100 47 F 100 nF 220 F
Vi(p-p) nF (100 V) (25 V)
COMP. GUARD
CIRCUIT CIRCUIT
VI(bias) M5
D1(2)
D2
0 D3
M2 RCMP
820 k
INA 1
D1
RCV1 10 OUTA
C6 2.2 k
2.2 nF (1%) M4 RD1 deflection
DEFLECTION coil
270 CD(1)
CONTROLLER RS 5 mH
INPUT 12 FEEDB 6 47 nF
AND 2.7 k (W66ESF)
FEEDBACK
RD2(1)
INB 2 CIRCUIT
RM 22
11
RCV2 0.5
M1
C7 2.2 k
2.2 nF (1%) 4 OUTB
M3
Vi(p-p) TDA8358J
VI(bias)
Ii(p-p) Ii 12
6 7
VGND EWGND
II(av) REWF
82 k
0 MGL874
Deflection circuit: fvert = 50 Hz; tFB = 640 s; II(bias) = 400 A; Ii(dif)(peak) = 290 A; Io(p-p) = 2.4 A.
Product specification
TDA8358J
East-west amplifier: Ii(B) = 290 A; Ii(T) = 510 A.
(1) Optional, component values depend on the deflection coil impedance.
(2) Extended flash over protection; BYD33D or equivalent.
(3) Optional, extended flash over protection.
Supply voltage calculation The flyback supply voltage calculated this way is about
5% to 10% higher than required.
For calculating the minimum required supply voltage,
several specific application parameter values have to be
Calculation of the power dissipation of the vertical
known. These parameters are the required
output stage
maximum (peak) deflection coil current Icoil(peak), the coil
parameters Rcoil and Lcoil, and the measuring resistance The power dissipation of the vertical output stage is given
of RM. The required maximum (peak) deflection coil by the formula:
current should also include the overscan.
PV = Psup PL
The deflection coil resistance has to be multiplied with 1.2
The power to be supplied is given by the formula:
in order to take account of hot conditions.
Chapter Characteristics supplies values for the voltage I coil ( peak )
P sup = V P -----------------------
- + V P 0.015 [A] + 0.3 [W]
losses of the vertical output stage. For the first part of the 2
scan the voltage loss is given by Vloss(1). For the second
In this formula 0.3 [W] represents the average value of the
part of the scan the voltage loss is given by Vloss(2).
losses in the flyback supply.
The voltage drop across the deflection coil during scan is
The average external load power dissipation in the
determined by the coil impedance. For the first part of the
deflection coil and the measuring resistor is given by the
scan the inductive contribution and the ohmic contribution
formula:
to the total coil voltage drop are of opposite sign, while for
the second part of the scan the inductive part and the 2
( I coil ( peak ) )
ohmic part have the same sign. P L = -------------------------------- ( R coil + R M )
3
For the vertical frequency the maximum frequency
occurring must be applied to the calculations. Example
The required power supply voltage VP for the first part of Table 1 Application values
the scan is given by:
SYMBOL VALUE UNIT
V P ( 1 ) = I coil ( peak ) ( R coil + R M )
Icoil(peak) 1.2 A
L coil 2I coil ( peak ) f vert ( max ) + V loss ( 1 )
Icoil(p-p) 2.4 A
The required power supply voltage VP for the second part Lcoil 5 mH
of the scan is given by: Rcoil 6
V P ( 2 ) = I coil ( peak ) ( R coil + R M ) RM 0.6
+ L coil 2I coil ( peak ) f vert ( max ) + V loss ( 2 ) fvert 50 Hz
tFB 640 s
The minimum required supply voltage VP shall be the
highest of the two values VP(1) and VP(2). Spread in supply
voltage and component values also has to be taken into Table 2 Calculated values
account. SYMBOL VALUE UNIT
VP 14 V
Flyback supply voltage calculation
RM + Rcoil (hot) 7.8
If the flyback time is known, the required flyback supply
tvert 0.02 s
voltage can be calculated by the simplified formula:
x 0.000641
R coil + R M VFB 30 V
V FB = I coil ( p p ) --------------------------
t FB x
-
1e Psup 8.91 W
PL 3.74 W
where:
PV 5.17 W
L coil
x = --------------------------
-
R coil + R M
1999 Dec 22 12
Philips Semiconductors Product specification
Power dissipation calculation for the east-west stage The required heatsink thermal resistance is given by:
In general the shape of the east-west output wave form is T j T amb
a parabola. The output voltage will be higher at the - ( R th ( j c ) + R th ( c h ) )
R th ( h a ) = ------------------------
P EW + P V
beginning and end of the vertical scan compared to the
voltage at the scan middle, while the output current will be When we use the values known we find:
higher at the scan middle. This results in an almost uniform
power dissipation distribution during scan. Therefore the 130 40
R th ( h a ) = ---------------------- ( 4 + 1 ) = 5 K/W
power dissipation can be calculated by multiplying the 3+6
average values of the output voltage and the output
The heatsink temperature will be:
current of pin OUTEW.
Th = Tamb + Rth(h-a) Ptot = 40 + 5 9 = 85 C
When verifying the dissipation also the start-up and stop
dissipation should be taken into account. Power
Equivalent thermal resistance network
dissipation during start-up can be 3 to 5 times higher than
during normal operation. The TDA8358J has two independent power dissipating
systems, the vertical output circuit and the east-west
Heatsink calculation circuit.
The value of the heatsink can be calculated in a standard It is recommended to verify the individual maximum (peak)
way with a method based on average temperatures. junction temperatures of both circuits. Therefore the
The required thermal resistance of the heatsink is maximum (peak) power dissipations of the circuits and
determined by the maximum die temperature of 150 C. also the heatsink temperature should be measured.
In general we recommend to design for an average die The maximum (peak) junction temperatures can be
temperature not exceeding 130 C. It should be noted calculated by using an equivalent thermal network
that the heatsink thermal resistance Rth(h-a) found by (see Fig.5).
performing a standard calculation will be lower then
The network does only consist the contribution of the
normally found for a vertical deflection stand alone device,
maximum (peak) power dissipation PTRv(peak), being the
due to the contribution of the EW power dissipation to this
dissipation of the most critical transistor internally
value.
connected to pins OUTB and VGND. The model assumes
equivalent maximum (peak) power dissipations during the
EXAMPLE
different vertical scan stages for all the functionally paired
Measured or known values: transistors. The calculated maximum (peak) junction
temperatures should not exceed Tj = 150 C.
PEW = 3 W; PV = 6 W; Tamb = 40 C; Tj = 130 C;
Rth(j-c) = 4 K/W; Rth(c-h) = 1 K/W.
1999 Dec 22 13
Philips Semiconductors Product specification
EXAMPLE
Measured or known values:
The east-west power dissipation: PEW = 3 W
The vertical power dissipation: PV = 6 W
The maximum (peak) power dissipation of the most
handbook, halfpage TEW(M) TTRv(M) critical transistor: PTRv(peak) = 5 W
The case temperature: Tc = 85 C.
Rth(EW-P1) Rth(TRv-P1)
10.5 K/W 5.2 K/W
The IC total power dissipation is:
PEW TP1(M) PTRv(M) Ptot = PEW + PV = 6 + 3 = 9 W
It should be noted that the allowed IC total power
Rth(P1-c)
2.2 K/W
dissipation is Ptot = 15 W (maximum value).
Ptot The maximum (peak) temperature TP1(peak) is given by:
Tc MGL872 TP1(peak) = Tc + (PEW + PTRv(peak)) Rth(P1-c)
= 85 + (3 + 5) 2.2 = 102.6 C
The maximum (peak) junction temperatures for the output
circuits are given by:
Tj(EW)(peak) = TP1(peak) + Rth(EW-P1) PEW
= 102.6 + 10.5 3 = 134.1 C
Fig.5 Equivalent thermal resistance network. Tj(TRv)(peak) = TP1(peak) + Rth(TRv-P1) PTRv(peak)
= 102.6 + 5.2 5 = 128.6 C
1999 Dec 22 14
Philips Semiconductors Product specification
300
1
MBL100
2 INB
300
2
MBL102
3 VP
9
4 OUTB
6 VGND
9 VFB
3
10 OUTA
10
6
MGL869
5 INEW
300
7 EWGND 5
8 OUTEW
8
MGL868
1999 Dec 22 15
Philips Semiconductors Product specification
MGL870
12 FEEDB 300
12
MGL871
13 COMP
300
13
MGL875
1999 Dec 22 16
Philips Semiconductors Product specification
PACKAGE OUTLINE
DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6
non-concave
Dh
x
Eh
d A2
j E
L3
L Q
c v M
1 13
Z e1 w M m e2
bp
e
0 5 10 mm
scale
17.0 4.6 0.75 0.48 24.0 20.0 12.2 6 3.4 12.4 2.4 2.1 2.00
mm 10 3.4 1.7 5.08 4.3 0.8 0.25 0.03
15.5 4.4 0.60 0.38 23.6 19.6 11.8 3.1 11.0 1.6 1.8 1.45
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
97-12-16
SOT141-6
99-12-17
1999 Dec 22 17
Philips Semiconductors Product specification
SOLDERING The total contact time of successive solder waves must not
exceed 5 seconds.
Introduction to soldering through-hole mount
packages The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
This text gives a brief insight to wave, dip and manual
specified maximum storage temperature (Tstg(max)). If the
soldering. A more in-depth account of soldering ICs can be
printed-circuit board has been pre-heated, forced cooling
found in our Data Handbook IC26; Integrated Circuit
may be necessary immediately after soldering to keep the
Packages (document order number 9398 652 90011).
temperature within the permissible limit.
Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit Manual soldering
board.
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
Soldering by dipping or by solder wave
2 mm above it. If the temperature of the soldering iron bit
The maximum permissible temperature of the solder is is less than 300 C it may remain in contact for up to
260 C; solder at this temperature must not be in contact 10 seconds. If the bit temperature is between
with the joints for more than 5 seconds. 300 and 400 C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods
SOLDERING METHOD
PACKAGE
DIPPING WAVE
DBS, DIP, HDIP, SDIP, SIL suitable suitable(1)
Note
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
DEFINITIONS
1999 Dec 22 18
Philips Semiconductors Product specification
NOTES
1999 Dec 22 19
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Printed in The Netherlands 545004/100/01/pp20 Date of release: 1999 Dec 22 Document order number: 9397 750 06197