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Outline

Power and Energy


Dynamic Power
Static Power

Lecture 7:
Power

7: Power CMOS VLSI Design 4th Ed. 2

Power and Energy Power in Circuit Elements


Power is drawn from a voltage source attached to
PVDD ( t ) = I DD ( t ) VDD
the VDD p
pin(s)
( ) of a chip.
p

Instantaneous Power: P(t ) = I (t )V (t )


VR2 ( t )
T PR ( t ) = = I R2 ( t ) R
Energy: E = P (t )dt R
0

T dV
Average Power: E 1 EC = I ( t )V ( t ) dt = C V ( t ) dt
T T 0
Pavg = = P (t )dt 0 0
dt
VC

= C V ( t )dV = 12 CVC2
0

7: Power CMOS VLSI Design 4th Ed. 3 7: Power CMOS VLSI Design 4th Ed. 4

1
Charging a Capacitor Switching Waveforms
When the gate output rises Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz
Energy stored in capacitor is
EC = 12 CLVDD
2

But energy drawn from the supply is



dV
EVDD = I ( t )VDD dt = CL VDD dt
0 0
dt
VDD

= CLVDD dV = C V
2
L DD
0

Half the energy from VDD is dissipated in the pMOS


transistor as heat
heat, other half stored in capacitor
When the gate output falls
Energy in capacitor is dumped to GND
Dissipated as heat in the nMOS transistor

7: Power CMOS VLSI Design 4th Ed. 5 7: Power CMOS VLSI Design 4th Ed. 6

Switching Power Activity Factor


T Suppose the system clock frequency = f
1
Pswitching
it hi = iDD (t )VDD dt Let fsw = f, where = activity factor
T 0
If the signal is a clock, = 1
T
VDD If the signal switches once per cycle, =
T 0
= iDD (t ) dt

VDD Dynamic power:


= [Tfsw CVDD ] VDD
Pswitching = CVDD 2 f
T iDD(t)
fsw

= CVDD 2 f sw
C

7: Power CMOS VLSI Design 4th Ed. 7 7: Power CMOS VLSI Design 4th Ed. 8

2
Short Circuit Current Power Dissipation Sources
When transistors switch, both nMOS and pMOS Ptotal = Pdynamic + Pstatic
networks may y be momentarilyy ON at once Dynamic power: Pdynamic = Pswitching + Pshortcircuit
Leads to a blip of short circuit current. Switching load capacitances
< 10% of dynamic power if rise/fall times are Short-circuit current
comparable for input and output Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
We will generally ignore this component Subthreshold leakage
Gate leakage
Junction leakage
Contention current

7: Power CMOS VLSI Design 4th Ed. 9 7: Power CMOS VLSI Design 4th Ed. 10

Dynamic Power Example Solution


1 billion transistor chip Clogic = ( 50 106 ) (12 )( 0.025 m / )(1.8 fF / m ) = 27 nF
50M logicg transistors
Average width: 12 Cmem = ( 950 106 ) ( 4 )( 0.025 m / )(1.8 fF / m ) = 171 nF
Activity factor = 0.1 Pdynamic = 0.1Clogic + 0.02Cmem (1.0 ) (1.0 GHz ) = 6.1 W
2

950M memory transistors


Average width: 4
Activity factor = 0.02
1.0
1 0 V 65 nm process
C = 1 fF/m (gate) + 0.8 fF/m (diffusion)
Estimate dynamic power consumption @ 1 GHz.
Neglect wire capacitance and short-circuit current.

7: Power CMOS VLSI Design 4th Ed. 11 7: Power CMOS VLSI Design 4th Ed. 12

3
Dynamic Power Reduction Activity Factor Estimation
Let Pi = Prob(node i = 1)
Pswitchingg = CVDD f
2
Pi = 11-P
Pi
Try to minimize: i = Pi * Pi
Activity factor Completely random data has P = 0.5 and = 0.25
Capacitance Data is often not completely random
Supply voltage e.g. upper bits of 64-bit words representing bank
Frequency account balances are usually 0
Data propagating through ANDs and ORs has lower
activity factor
Depends on design, but typically 0.1

7: Power CMOS VLSI Design 4th Ed. 13 7: Power CMOS VLSI Design 4th Ed. 14

Switching Probability Example


A 4-input AND is built out of two levels of gates
Estimate the activity factor at each node if the inputs
have P = 0.5

7: Power CMOS VLSI Design 4th Ed. 15 7: Power CMOS VLSI Design 4th Ed. 16

4
Clock Gating Capacitance
The best way to reduce the activity is to turn off the Gate capacitance
clock to registers
g in unused blocks Fewer stages of logic
Saves clock activity ( = 1) Small gate sizes
Eliminates all switching activity in the block Wire capacitance
Requires determining if block will be used Good floorplanning to keep communicating
blocks close to each other
Drive long wires with inverters or buffers rather
than
h complex l gates

7: Power CMOS VLSI Design 4th Ed. 17 7: Power CMOS VLSI Design 4th Ed. 18

Voltage / Frequency Static Power


Run each block at the lowest possible voltage and Static power is consumed even when chip is
frequency that meets performance requirements q
quiescent.
Voltage Domains Leakage draws power from nominally OFF
Provide separate supplies to different blocks devices
Level converters required when crossing Ratioed circuits burn power in fight between ON
from low to high VDD domains transistors

Dynamic Voltage Scaling


Adjust VDD and f according to
workload

7: Power CMOS VLSI Design 4th Ed. 19 7: Power CMOS VLSI Design 4th Ed. 20

5
Static Power Example Solution
Revisit power estimation for 1 billion transistor chip
Wnormal-Vt = ( 50 106 ) (12 )( 0.025 m / )( 0.05 ) = 0.75 106 m
Estimate static power consumption
Whigh-Vt = ( 50 106 ) (12 )( 0.95 ) + ( 950 106 ) ( 4 ) ( 0.025 m / ) = 109.25 106 m
Subthreshold leakage
I sub = Wnormal-Vt 100 nA/ m+Whigh-Vt 10 nA/ m / 2 = 584 mA
Normal Vt: 100 nA/m
High Vt: 10 nA/m (
)
I gate = Wnormal-Vt + Whigh-Vt 5 nA/ m / 2 = 275 mA
Pstatic = ( 584 mA + 275 mA )(1.0 V ) = 859 mW
High Vt used in all memories and in 95% of
logic gates
Gate leakage 5 nA/m
Junction leakage negligible

7: Power CMOS VLSI Design 4th Ed. 21 7: Power CMOS VLSI Design 4th Ed. 22

Subthreshold Leakage Stack Effect


For Vds > 50 mV Typical values in 65 nm Series OFF transistors have less leakage
Vgs + (Vds VDD ) k Vsb Ioff = 100 nA/m @ Vt = 0.3 V Vx > 0, so N2 has negative
g Vgs
I sub I off 10 S Ioff = 10 nA/m @ Vt = 0.4 V
Ioff = 1 nA/m @ Vt = 0.5 V (Vx VDD ) Vx + ( (VDD Vx ) VDD ) k Vx

= 0.1 I sub = I off 10 S = I off 10 S

Ioff = leakage at Vgs = 0, Vds = VDD 14 4244 3 1444 424444


3
k = 0.1 N1 N2

S = 100 mV/decade VDD


Vx =
1 + 2 + k
1+ + k
VDD
1+ 2 + k VDD

I sub = I off 10 S
I off 10 S

Leakage through 2-stack reduces ~10x


Leakage through 3-stack reduces further

7: Power CMOS VLSI Design 4th Ed. 23 7: Power CMOS VLSI Design 4th Ed. 24

6
Leakage Control Gate Leakage
Leakage and delay trade off Extremely strong function of tox and Vgs
Aim for low leakage
g in sleep p and low delay
y in Negligible for older processes
active mode
Approaches subthreshold leakage at 65 nm and
To reduce leakage: below in some processes
Increase Vt: multiple Vt
An order of magnitude less for pMOS than nMOS
Use low Vt only in critical circuits
Control leakage in the process using tox > 10.5
Increase Vs: stack effect
Input
put vector
ecto co t o in s
control sleep
eep High-k gate dielectrics help
Decrease Vb Some processes provide multiple tox
Reverse body bias in sleep e.g. thicker oxide for 3.3 V I/O transistors
Or forward body bias in active mode Control leakage in circuits by limiting VDD

7: Power CMOS VLSI Design 4th Ed. 25 7: Power CMOS VLSI Design 4th Ed. 26

Power Gating
Turn OFF power to blocks when they are idle to
save leakage
Use virtual VDD (VDDV)
Gate outputs to prevent
invalid logic levels to next block

Voltage drop across sleep transistor degrades


performance during normal operation
Size the transistor wide enough to minimize
impact
Switching wide sleep transistor costs dynamic power
Only justified when circuit sleeps long enough
7: Power CMOS VLSI Design 4th Ed. 27