Microprocessor and Interfacing

EEE 319

Lecture 7 (8086 Arithmetic Logic Unit)

Abdullah Bin Shams

Lecturer
EEE, BUBT
shams@bubt.edu.bd
Section I Arithmetic Logic Unit (ALU)

An arithmetic logic unit (ALU) is a digital electronic circuit that performs

arithmetic and bitwise logical operations on integer binary numbers. It is a
fundamental building block of the central processing unit (CPU).

The inputs to an ALU are the data (to be operated on called operands) and a code
indicating the operation to be performed. The output of the ALU is the result of the
performed operation.

The ALU also exchanges additional information with a status/flag register, which
relates to the result of the current or previous operations.

Figure: Arithmetic Logic Unit (ALU)

Data

A basic ALU has three parallel data buses consisting of two input operands (A and
B) and a result output (Y). Each data bus is a group of signals that conveys one
binary integer number.
Opcode

The opcode input is a parallel bus that conveys to the ALU an operation selection
code, which specifies the desired arithmetic or logic operation to be performed by
the ALU on the operands.

Status

The status various individual signals that convey supplemental information about
the result of an ALU operation. These outputs are usually stored in registers so
they can be used in future ALU operations or for controlling conditional branching.

Section II Arithmetic instructions

Operand types:

REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.
SREG: DS, ES, SS, and only as second operand: CS.
Memory: [BX], [BX+SI+7], variable, etc.
Immediate: 5, -24, 3Fh, 10001101b, etc.

Instruction Operands Description

REG, memory
memory, REG
copy value of one operand to another operand
REG, REG
memory, immediate
operand1 = operand2
MOV REG, immediate
SREG, memory
MOV DS, AX ; copy value of AX to DS
memory, SREG
MOV CL, 'A' ; CL = 41h (ASCII code)
REG, SREG
SREG, REG
 REG, memory
operand1 = operand1 + operand2
memory, REG
ADD REG, REG
MOV AL, 5 ; AL = 5
memory, immediate
ADD AL, -3 ; AL = 2
REG, immediate

Add with Carry

REG, memory
memory, REG operand1 = operand1 + operand2 + CF
ADC REG, REG
memory, immediate STC ; set CF = 1
REG, immediate MOV AL, 5 ; AL = 5
ADC AL, 1 ; AL = 7

REG, memory Subtract

memory, REG
SUB REG, REG operand1 = operand1 - operand2
memory, immediate MOV AL, 5
REG, immediate SUB AL, 1 ; AL = 4

Subtract with Borrow

REG, memory
memory, REG operand1 = operand1 operand2 CF
SBB REG, REG
memory, immediate STC
REG, immediate MOV AL, 5
SBB AL, 3 ; AL = 5 3 1 = 1

operand = operand + 1
REG
INC
Memory MOV AL, 4
INC AL ; AL = 5
 operand = operand 1
REG
DEC
Memory MOV AL, 255 ; AL = 0FFh (255 or -1)
DEC AL ; AL = 0FEh (254 or -2)

Makes operand negative (two's complement)

Invert all bits of the operand

REG Add 1 to inverted operand
NEG
Memory
MOV AL, 5 ; AL = 05h
NEG AL ; AL = 0FBh (5)
NEG AL ; AL = 05h (5)
Section III Logical operations (Bit wise operation)

Instruction Operands Description

REG, memory
memory, REG
MOV AL, 'a' ; AL = 01100001b
AND REG, REG
AND AL, 11011111b ; AL = 01000001b ('A')
memory, immediate
REG, immediate

REG, memory
memory, REG
MOV AL, 'A' ; AL = 01000001b
OR REG, REG
OR AL, 00100000b ; AL = 01100001b ('a')
memory, immediate
REG, immediate

1 XOR 1 = 0
REG, memory 1 XOR 0 = 1
memory, REG 0 XOR 1 = 1
XOR REG, REG 0 XOR 0 = 0
memory, immediate
REG, immediate MOV AL, 00000111b
XOR AL, 00000010b ; AL = 00000101b

REG MOV AL, 00011011b

NOT
Memory NOT AL ; AL = 11100100b
Section IV Shift operation

Instruction Operands Description

Rotate operand1 left. The number of rotates is

set by operand2.

Shift all bits left, the bit that goes off is set to
memory, immediate
CF and the same bit is inserted to the right
REG, immediate
ROL most position.
memory, CL
REG, CL
MOV AL, 1Ch ; AL = 00011100b
ROL AL, 1 ; AL = 00111000b, CF=0

OF=0 if first operand keeps original sign

Rotate operand1 right. The number of rotates

is set by operand2.

Shift all bits right, the bit that goes off is set
memory, immediate
to CF and the same bit is inserted to the left
REG, immediate
ROR most position.
memory, CL
REG, CL
MOV AL, 1Ch ; AL = 00011100b
ROR AL, 1 ; AL = 00001110b, CF=0

OF=0 if first operand keeps original sign

Rotate operand1 left through Carry Flag. The

memory, immediate
number of rotates is set by operand2.
REG, immediate
RCL
memory, CL
Shift all bits left, the bit that goes off is set to
REG, CL
CF and previous value of CF is inserted to the
right most position.
 STC ; set carry (CF=1).
MOV AL, 1Ch ; AL = 00011100b
RCL AL, 1 ; AL = 00111001b, CF=0

OF=0 if first operand keeps original sign.

Rotate operand1 right through Carry Flag.

The number of rotates is set by operand2.

Shift all bits right, the bit that goes off is set
memory, immediate to CF and previous value of CF is inserted to
REG, immediate the leftmost position.
RCR
memory, CL
REG, CL STC ; set carry (CF=1)
MOV AL, 1Ch ; AL = 00011100b
RCR AL, 1 ; AL = 10001110b, CF=0

OF=0 if first operand keeps original sign.

Section V Instructions effecting the flags

Instructions Affect Flags

MOV None
XCHG None
ADD All
SUB All
INC All except CF
DEC All except CF

All (Carry Flag = 1 unless result is 0,

NEG Overflow Flag = 1 if word operand is
8000h, or byte operand is 80h)
Example 1

MOV AX , 0FFFFh
MOV BX , 0FFFFh

ADD AX, BX

Solution:
Actual Result = 1 FFFEh
Result stored in AX = FFFEh

Flags:
SF = 1 because the MSB is 1
PF = 0 because there are 7 (odd number) of 1s in the low byte of the result.
ZF = 0 because nonzero result
CF = 1 because there is a carry out of the MSB on addition
OF = 0 because the sign of the stored result is the same as that of the
numbers being added (in binary addition, there is a carry into the MSB and
carry out from MSB also)

Example 2

MOV AL , 80h
MOV BL , 80h

ADD AL, BL where AL contains 80h, BL contains 80h

Solution:
Actual Result = 100h
Result in AL = 00h

Flags:
SF = 0 because MSB is 0
PF = 1 because all bits in result are 0
ZF = 1 because result is 0
CF = 1 because there is a carry out from MSB
OF = 1 because the numbers being added are both negative but the MSB in
result is 0 (in binary addition, there is a no carry into the MSB but there is
carry out from MSB.
Example 3

MOV AX , 8000h
MOV BX , 0001h

SUB AX , BX

Solution:
Actual Result = 7FFFh
Result in AX = 7FFFh

Flags:
SF = 0 because MSB is 0
PF = 1 because there are 8 one bits in the low byte of the result
ZF = 0 because result is nonzero
CF = 0 because a smaller unsigned number is being subtracted from a larger
one
OF =1 because we are subtracting a positive number from a negative number
but the result is positive (wrong sign of result)

Example 4

MOV AL , 0FFh

INC AL where AL contains FFh

Solution:
Actual Result = 100h
Result stored in AL = 00h

Flags:
SF = 0
PF = 1
ZF = 1
CF = 0 because CF is unaffected by INC
OF = 0 because number of unlike sign are being added (there is a carry into
the MSB and also carry out from the MSB)
Example 5

MOV AX, -5

Solution:
Result in AX = -5 = FFFBh

Flags:
None of the flags are affected by MOV

Example 6

MOV AX , 8000h

NEG AX where AX contains 8000h

Solution:
Result in AX = 8000h (2s complement)

Flags:
SF = 1
PF = 1, in low byte of result, number of 1 bits is 0.
ZF = 0
CF = 1 because for NEG, CF is always 1 unless the result is zero
OF = 1 because there is no sign change

Practice problem

Write the status of the flags (CF, AF, ZF, PF, SF) after each instruction is
executed.

MOV AX, 4000h ; AX = 4000h

ADD AX, AX ; AX = 8000h
SUB AX, 0FFFFh ; AX = 8001h
NEG AX ; AX = 7FFFh
INC AX ; AX = 8000h
MOV AH, 4Ch
INT 21H