Directed Study on Research

Topics

PWM Schemes for the Three Level

NPC Converter
Submitted by:
Jose Titus
EE14D022
 PWM Schemes for the Three
Level NPC Converter
Aim
To simulate the V/f control of induction motor using a Three Level Neu-
tral Point Clamped Converter (NPC) with SPWM and SVPWM modulation
schemes and to calculate the power loss for a 1 MW drive operated with this
converter.

Structure of the Three Level NPC Converter

The operation of the three level NPC converter can be understood by con-
sidering a single leg of the converter. The schematic of a single leg of the
three level NPC converter is as shown in Fig.1.

S1
D1
Vdc / 2
S2
D5 D2

m r
S1
D6 D3

Vdc / 2
S2
D4

Figure 1: A single leg of the 3-level NPC converter

There are 2 pairs of complementary switches, each consisting of an IGBT

and an anti-parallel diode, and two clamping diodes in each leg of the con-
verter. The pole voltage Vrm at any instant can have 3 different levels depend-
ing on which of the switches are conducting. These levels and the devices
conducting for a specified direction of current, ir flowing out of the leg is

1
 Switches Switches Devices Conducting Pole Switching
ON OFF ir > 0 ir < 0 Voltage State
0 0
S1, S2 S1 ,S2 S1, S2 D1, D2 Vdc /2 1
0 0 0 0
S1 , S2 S1, S2 D3, D4 S1 , S2 -Vdc /2 -1
0 0 0
S1 , S2 S1,S2 D5, S2 S1 , D6 0 0

Table 1: Switching states of the Three Level NPC

given in Table 1. The following points about the operation of the converter
should be noted.

Considering the OFF state voltages across the switches in each state,
it can be observed that each device should be rated to block a voltage
of Vdc /2.

Also, it can be seen that the topmost and bottommost switches conduct
only in states 1 and -1 respectively while the 2 middle switches conduct
during the 0 state also. Thus switches of different ratings may be used
in an optimal design.

The capacitors in the converter carry load current and hence unequal
loading can cause the neutral point fluctuation problems.

SPWM for the 3 Level NPC

Several variations of SPWM for the 3 level NPC are available in literature.
In this work, a unipolar modulation scheme using two carrier signals and
a single reference signal is used for controlling the switches. The two high
frequency carrier signals are chosen to be in phase. This is shown in Fig.2.

1
v t1
vr
0

v t2
1

Figure 2: In Phase SPWM using multiple carriers

2
 The same carrier signals are used for all the three legs while the modulat-
ing signals are shifted from each other by 120 to obtain the 3 phase output.
The switching state of a leg is decided by comparing the modulating signal
for that leg with the carrier signals. This is given as

+1 ,
if vr > vt1 and vr > vt2
State = 0, if vr < vt1 and vr > vt2

1 , if vr < vt1 and vr < vt2

For this scheme, the modulation index m, is the peak value of the reference
voltage. For m=1, the fundamental component of the output voltage is
maximum. With the switching scheme mentioned above, the switching occurs
between +1 and 0 states during the positive half cycle of the reference voltage,
and between 0 and -1 during the negative half cycle. Thus it can be seen that
0
S1 is switched only during the positive half cycle and S2 is switched only
during the negative half cycle. Similarly S2 remains ON during the entire
0
positive half cycle and S1 remains ON during the entire negative half cycle.
Thus the average switching frequency for the switches is only half that of the
carrier frequency.
The major disadvantages of a simple switching scheme as above, are the
problem of neutral point fluctuations and narrow pulse width during switch-
ing occurring near zero.

Simulation Results The above scheme of SPWM was simulated using

MATLAB/Simulink and PLECS environment. The inverter was used for

Figure 3: Switching states with SPWM

3
driving an induction motor load with a V/f control. The resulting waveforms
obtained are given in this section.

Figure 4: Phase voltage profile with SPWM

Space Vector Modulation

The voltage space vector is defined as
2 4
V~s (t) = vr0 (t) + vy0 (t) ej 3 + vb0 (t) ej 3 (1)

where vr0 , vy0 and vb0 are the phase to neutral voltages when the inverter
is connected to a balanced three phase star connected winding. The voltage
space vector can also be written as

V~s = v + jv (2)

where
1 1
v = vrm vym vbm (3)
2 2
3 3
v = vym vbm (4)
2 2
where vrm , vym and vbm are the pole voltages of the R, Y and B phases
respectively. Each leg has 3 states and hence there are a total of 27 different
vectors out of which 3 are zero vectors. Some of the vectors have redundancy

4
 V15 V8 V14

V3 V2
V9 V7

V4 V1
V16 V13
V0

V10 V5 V6 V12

V17 V11 V18

Figure 5: Space vector locations

in locations giving a total of 19 space vector locations. The space vector

diagram with the position of the various vectors marked is shown in Fig.5.
The following points may be noted.

The zero vector is denoted by V0 , has zero magnitude and is at the

centre of the hexagon.

There are 6 small vector locations of magnitude Vdc /2 labelled V1 to

V6 that correspond to 12 switching combinations. Half of these occur
when any two legs are clamped to the midpoint while the other half
occurs when any two legs are clamped to the negative or positive rail
with the other leg clamped to the midpoint.

There
are 6 medium vectors labelled V7 to V12 with a magnitude of
3
V
2 dc
. These occur when all the 3 legs are in different states.

6 large vectors with magnitude Vdc occur when none of the legs are in
zero state.

The idea behind the space vector modulation is that the reference voltage
vector at any instant can be synthesised in an average sense over a sampling
period by the three nearest voltage vectors. For this the time durations or
dwell times of each vector needs to be calculated. The sequence of switching is

5
then decided upon so as to minimise switching losses and to have a symmetric
PWM waveform. In this work, the space vector modulation is done for the
3 level inverter by using a 2 level algorithm for calculating the dwell times.

SVPWM based on a 2-level algorithm

From the space vector diagram it can be observed that there are six sub-
hexagons within the main hexagon, with centres located at the vector loca-
tions V1 to V6 . This is shown in Fig.6. Each of these sub-hexagonal centers

Hexagon 1 Hexagon 2 Hexagon 3

Hexagon 4 Hexagon 5 Hexagon 6

Figure 6: Sub-hexagon locations within the main hexagon

can be shifted to the centre of the main hexagon by subtracting a suitable

mapping vector from the sub-hexagons. This effectively makes the reference
vector to lie within a single hexagon and then a simple 2 level algorithm can
be applied to calculate the dwell times. The original vectors are then recal-
culated by adding the mapping vector to the 2 level vectors. This technique
is also called centre aligned space vector PWM.
Thus the first step is to identify the sub-hexagon to which the reference
vector belongs to. This is easily done by calculating the alpha and beta com-
ponents of the reference vector to obtain the angle. Once the sub-hexagon is
identified the reference vector is mapped to the inner hexagon. For eg. if the
vector lies in sub-hexagon 1, then the mapping vector is V~1 . Thus the new

6
reference vector for 2 level SVPWM is calculated as
0
V~ref = V~ref V~map (5)

Now, a conventional two level algorithm is used to identify the vectors and
0
their dwell times required for synthesising Vref . Thus, if the dwell times are
0 0 0
T1 , T2 and T0 for vectors V1 , V2 and V0 then
0 0 0 0
V1 T1 + V2 T2 + V0 T0 = Vref Ts (6)
T1 + T2 + T0 = Ts (7)

It should be noted that there is an overlap between the various hexagons

and hence the sector identification is done such that ambiguity is avoided by
allocating the overlapping region as belonging to only one of the overlapping
hexagons.

Simulation Results Simulations were done to implement the center aligned

space vector PWM for the 3 level inverter. The sampling frequency was cho-
sen as 5kHz. The results of these are given below.

Figure 7: Phase voltages with SVPWM

7
V/f Control with the 3-level NPC
A V/f controlled drive is simulated using the 3-level NPC controlled using
SPWM as well as using SVPWM, and a 4.5MW, 4160V, 4 pole squirrel cage
induction machine. A DC bus voltage of 7000 volts was used in the for the
converter. The machine speed was ramped up from 5 Hz till 2 seconds to 50
Hz in 15 seconds. The results obtained are as shown below.

Figure 8: Speed and Torque response

Figure 9: Line voltages at steady state

8
 Figure 10: Line currents at steady state

Power loss calculation for the drive

PLECS platform provides all the losses in the converter separately. For this
a look up table of the turn on and turn off losses is to be input to PLECS.
The voltage across the switches during turn on and turn off is constant and
hence the turn on and turn off losses are calculated by using a lookup table.
The table is loaded with values of energy dissipated during turn on and turn
off for different values of current. These are obtained from the manufacturer
datasheets. In this simulation, loss data is taken from the datasheets of an
IXYS make 6.5kV, 600A IGBT. The value of loss for a particular value of
current is then obtained by interpolation. These values are saved for a single
cycle of the fundamental and added up to get the total energy loss over a
cycle. The conduction losses are obtained by calculating the rms value of
the current through the switches over a cycle. The on state resistance of the
switches and the on state voltage drop is obtained from the manufacturer
datasheet and used for calculation.

9
Conclusion
The operation and control of the 3 level Neutral Point Clamped Converter
has been studied and simulated. The performance of the converter used in a
V/f drive for a high voltage machine is also studied by simulation.

References
[1] A.R. Beig, G. Narayanan, and V.T. Ranganathan. Modified svpwm algo-
rithm for three level vsi with synchronized and symmetrical waveforms.
Industrial Electronics, IEEE Transactions on, 54(1):486494, Feb 2007.

[2] Bin Wu High Power Converters and AC drives. IEEE Press, Wiley
Interscience, 2006.

[3] A. R. Beig. Application of three level Voltage Source Inverters to voltage

fed and current fed high power induction motor drives. -Ph.D Thesis of
Electrical Engineering, IISc Bangalore, April 2004.

10
 Directed Study on Research
Topics

Multilevel Converters and Neutral

Point Control Schemes for the Three
Level NPC Converter
Submitted by:
Jose Titus
EE14D022
 Multilevel Converters
Aim
To study the topology of the flying capacitor and neutral point clamped
converter (NPC) for multilevel inverters and to simulate a scheme for space
vector based neutral point balancing in the 3-level NPC converter. The
common mode voltage of this inverter will also be studied along with the
issues like bearing currents and shaft voltages in PWM inverter fed drives.

Structure of the Three Level Flying Capacitor Con-

verter
The operation of the three level NPC converter can be understood by con-
sidering a single leg of the converter. The schematic of a single leg of the
three level flying capacitor converter is as shown in Fig.1.

S1
D1

Vdc / 2
S2
D2

m Vdc / 2 r

S2
D3

Vdc / 2

S1
D4

Figure 1: A single leg of the 3-level Flying capacitor converter

There are 2 pairs of complementary switches, each consisting of an IGBT

and an anti-parallel diode, and a clamping capacitor in each leg of the con-
verter. The pole voltage Vrm at any instant can have 3 different levels depend-
ing on which of the switches are conducting. These levels and the devices
conducting for a specified direction of current, ir flowing out of the leg is

1
 Switches Switches Devices Conducting Pole Switching
ON OFF ir > 0 ir < 0 Voltage State
0 0
S1, S2 S1 ,S2 S1, S2 D1, D2 Vdc /2 1
0 0 0 0
S1 , S2 S1, S2 D3, D4 S1 , S2 -Vdc /2 -1
0 0 0
S1 , S2 S1,S2 D4, S2 D2, S1 0 0
0 0 0
S1,S2 S1 , S2 D3, S1 D1, S2 0 0

Table 1: Switching states of the Three Level NPC

given in Table 1. The following points about the operation of the converter
should be noted.
There are two different switch combinations that can be used to realise
the zero state of the inverter. This gives certain flexibility in designing
switching sequences for this converter.
During operation, the capacitor carries the load current and hence these
are bulky in nature for large values of capacitance.
With small values of capacitors, the voltage change due to load current
can be large. These can cause increased device stress.
Due to the large number of capacitors for higher levels, the bus bar de-
sign can be quite difficult. Also the capacitors require complex voltage
balancing schemes.

Neutral Point Voltage Control for the Three Level NPC

A scheme for controlling the neutral point voltage of a 3 level NPC converter
is simulated. In this scheme, a SVPWM technique is used to control the
converter. The control is done by varying the dwell times of the inner vectors
which affect the neutral point voltage. If a fall in neutral point voltage is
detected, then the dwell time of one the small vector state which causes the
neutral point voltage to rise is increased and the dwell time of the other state
which causes the neutral point voltage to fall is decreased by a small amount
such that the total dwell time remains the same. The results obtained from
simulation are discussed below.
Fig.2 shows the variation of neutral point voltage when a resistive load
is connected in parallel to one of the capacitors. The control is kept OFF
initially. The neutral point voltage starts falling and keeps drifting continu-
ously. When the control is switched ON at t=0.48 seconds, it is immediately
restored.

2
 1500
Signal
1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Figure 2: Neutral point Voltage variation

Fig.3 shows the current variation during the above operation. Fourier
analysis of the current waveform during the drift shows a strong second
harmonic component which is indicative of the neutral point variation.

1800
Signal:1
1600 Signal:2
Signal:3
1400

1200

1000

800

600

400

200

-200

-400

-600

-800

-1000

-1200

-1400

-1600
0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70

Figure 3: Load current waveform

3
 It should be noted that the mode of operation of the drive affects the
control action. The vectors which cause neutral point voltage rise during
motoring mode will cause neutral point voltage fall during regenerative mode.
Therefore the control should take into account the mode of operation to
decide upon the vector to be applied.

Five Level NPC Converter

Figure 4: Five Level NPC Converter

A schematic diagram of the 5 level NPC converter is as shown in Fig.4.

The pole voltage waveform of this converter contains 5 distinct levels- 4E,
3E, 2E, E and 0. There are 8 devices and 6 clamping diodes per leg of the
inverter. At any time, 4 switches are conducting. The blocking voltages of
the clamping diodes are different. If diodes of equal blocking voltage, E are
used then the converter will require 36 clamping diodes. In general, an N
level converter will require 3(N-1)(N-2) clamping diodes. This is the main
reason why higher level NPC are rarely used.

4
Bearing Currents and Shaft Voltages
In an electric machine, there are 3 prominent mechanisms which cause high
frequency bearing currents.

Circulating currents The capacitance from winding to stator frame causes

a net capacitive current flow from winding to stator along the circumference.
This causes a high frequency voltage between the shaft ends, which if high
enough will breakdown the insulation of the bearing and cause a circulating
current.

Shaft grounding current The current leaking into the stator flows back
to the inverter through the reference ground. Any route to the ground con-
tains impedance, and increases the voltage of the frame. If the shaft is
earthed via the driven machinery, this increase in frame voltage is seen across
the bearings and can cause bearing currents.

Capacitive discharge/EDM currents The internal voltage division of

the common mode voltage over the internal stray capacitances of the motor
can cause shaft voltages. This will result in charging the bearing capaci-
tances. If this voltage is sufficient to breakdown the insulation of the bear-
ings, then it will result in a discharging of the bearing capacitance by an arc
which will erode the material. This type of material erosion causes pitting in
the bearing and sustained pitting will lead to fluting damage to the bearing,
ultimately making it useless.

Analysis of line current ripple using error vectors

The stator flux ripple and hence the ripple in line current can be analysed by
considering the instantaneous voltage vectors applied to the machine. The
error vector is defined as the difference between the actual applied vector
and the desired reference vector. Thus the error vectors account for any
harmonics in the voltage and current. The ripple in stator flux is obtained
as the integral of the error vectors. The analysis is done in a dq reference
frame fixed to the reference voltage vector. Since the average error vector
over a sub-cycle is zero, the net movement of the tip of the stator flux vector
due to the error vectors is zero. However the peak values of the d and q axes
ripple can be calculated. The instantaneous torque ripple is due to the q axis
stator flux ripple. Thus the switching sequences can be analysed to find out
the sequence with the minimum q axis ripple.

5
References
[1] A.R. Beig, G. Narayanan, and V.T. Ranganathan. Modified svpwm algo-
rithm for three level vsi with synchronized and symmetrical waveforms.
Industrial Electronics, IEEE Transactions on, 54(1):486494, Feb 2007.

[2] Bin Wu High Power Converters and AC drives. IEEE Press, Wiley
Interscience, 2006.

[3] A. R. Beig. Application of three level Voltage Source Inverters to voltage

fed and current fed high power induction motor drives. -Ph.D Thesis of
Electrical Engineering, IISc Bangalore, April 2004.

6
Directed Study on Research
Topics

The Active NPC Converter

Submitted by:
Jose Titus
EE14D022
 Loss Balancing Control of
the Active NPC Converter
Aim
To study and simulate the active NPC converter topology and its loss bal-
ancing control.

Loss distribution in a conventional NPC

A single leg of the conventional NPC converter is as shown in Fig. 1. The

S1
D1

Vdc / 2

S2
D5 D2

m ia
r

S1
D6 D3

Vdc / 2

S2
D4

Figure 1: Single leg of the NPC converter

losses occurring in the individual devices depend on the operating point and
the type of modulation scheme used. Two cases with the conventional SVM
are considered.
Case A (mf = 1.15, cos = 1) Under this condition the phase current
and the voltage reference are in phase. Thus for ia > 0, the converter switches
between the states 1 and 0. S1 commutates with D5 , while S2 conducts for
the entire half wave. It can be seen that S1 conducts for nearly the same

1
time as S2 and additionally experiences switching losses. Thus S1 is clearly
the most stressed device.
Case B (mf = 1.15, cos = 1) Under this condition the phase current
and the voltage reference are 180 out of phase. Thus for ia > 0, the converter
switches between 0 and -1. Current commutates from D3 and D4 to D5 and
S2 . Since S3 is always ON, D3 does not experience much losses. S2 is stressed
with switching losses, but conducts for lesser time. Thus D4 is identified as
the most stressed device.

The active NPC converter

The structure of a single leg of the three level active NPC is shown in Fig. 2.
Here, the clamping diodes of the conventional NPC are replaced with active
switches. Thus current may be conducted in either directions through S5
and S6 . If the upper device is utilised for conduction, then S4 can be either

S1

C1
S2
S5

ia

S6
S3
C2

S4

Figure 2: One leg of the ANPC converter

in ON or in OFF state. This is also true for S1 during the conduction of the
lower path. In the +1 state, S6 should be turned on to ensure equal voltage
sharing between S3 and S4 . Similarly in the -1 state, S5 should be turned
on to ensure equal static voltage sharing. The valid states for the three level
ANPC are given in Table I.

2
 State S1 S2 S3 S4 S5 S6
(+) 1 1 0 0 0 1
0U2 0 1 0 0 1 0
0U1 0 1 0 1 1 0
0L1 1 0 1 0 0 1
0L2 0 0 1 0 0 1
(-) 0 0 1 1 1 0

Table 1: Switching states of the Three Level NPC

Loss Distribution in the Active NPC

The commutations from the additional switching states of the active NPC
determine the distribution of losses in the converter. It should be noted that
even when more than two devices are turning ON or OFF, only one switch
and one diode experiences switching losses, while the other device undergoes
soft turn on or off.
Consider the commutation from (+) to 0 in a normal NPC converter.
Assuming a positive phase current and positive output voltage, S1 is the most
stressed device. S1 is turned OFF and S3 is turned ON after a dead time.
Current commutates from S1 to D5 . Now consider the possible commutations
from (+) to 0 in an active NPC converter. The following possibilities exist.

(+) to 0U2 : S6 is turned OFF and then S1 is turned OFF. S5 is turned

ON after a deadtime. As in conventional commutation, S1 experiences
losses.

(+) to 0U1 : This commutation differs from the previous only in the
additional lossless turn ON of S4 after turn ON of S5 . Thus this is
identical to the previous commutation from a loss point of view.

(+) to 0L2 : S1 is turned OFF and S3 is turned ON after a dead

time. Since S6 is already ON, current commutates to both upper and
lower path. S1 experiences turn OFF losses. S2 is turned OFF slightly
delayed to S1 at zero voltage, to force the entire current to the lower
path. However, the turn OFF of S2 does experience any significant loss
as it is turned OFF at zero voltage.

(+) to 0L1 : S1 remains ON. S2 is turned OFF and S3 is turned ON

after a dead time. S2 experiences turn OFF losses.

3
Thus it can be seen that the loss associated with switching from one state
to another is different for different commutations, and also the device that is
stressed is different. This fact can be made use of for designing a switching
scheme for choosing from the possible commutations such that the losses get
distributed equally among the devices.

Loss balancing control scheme

The block diagram for loss balancing control of the active NPC converter is
as shown in Fig. 3.

Figure 3: Loss balancing control scheme[1]

Conclusion
The operation of the active NPC converter and the distribution of losses in
the devices are studied and compared with that of the conventional NPC. It
is seen that a loss balancing control can be implemented for the active NPC
so as to distribute the losses evenly. This is especially useful for drives when
operating at low speeds of operation.

4
References
[1] T. Bruckner, S. Bernet, and H. Guldner. The active NPC converter and
its loss-balancing control. Industrial Electronics, IEEE Transactions on,
52(3):855868, June 2005.

[2] J. Rodriguez, S. Bernet, P.K. Steimer, and I.E. Lizama. A survey on

neutral-point-clamped inverters. Industrial Electronics, IEEE Transac-
tions on, 57(7):22192230, July 2010.

5
 Directed Study on Research
Topics

Field Weakening Operation of the

Vector Controlled Induction Machine
Drive
Submitted by:
Jose Titus
EE14D022
 Field Weakening Operation
of the Vector Controlled
Induction Machine Drive
Aim
To study the operation of the vector controlled induction motor drive in the
field weakening region and to simulate the control algorithm in Plecs.

Field Weakening
In a VSI-fed induction machine drive, the maximum DC bus voltage is gen-
erally fixed. The stator voltage equations of the rotor flux oriented vector
controlled inducton machine under steady state conditions are given as

vsd = Rs isd Ls mr isq (1)

vsq = Rs isq + Ls mr imr (2)

The maximum possible values of the d and q axis voltages are limited due to
the limitation on the dc link voltage. Thus from Eq.(2), it can be observed
that for a given value of imr , the maximum speed that can be attained is
limited. To attain speeds above this maximum value, the value of imr should
be reduced. Since imr represents the rotor magnetising current, reducing imr
effectively means reducing the rotor flux. This operation is called field weak-
ening. The maximum available torque gets reduced during field weakening
operation due to the reduction in rotor flux.

Operational limits of the vector controlled drive

The maximum available dc link voltage places a limit on the maximum avail-
able stator terminal voltage, depending on the type of modulation used for
the power converter. Similarly, the maximum stator current is also limited,
either by the limitations of the semiconductor devices or by the maximum
rated current of the machine. These limits can be mathematically expressed
as
2 2
vsd + vsq Vs2max (3)
i2sd + i2sq Is2max (4)

1
Under high speed operation, the stator resistance drop can be neglected.
Then from Eq.(4),
vsq vsd
isd = isq = (5)
Ls mr Ls mr
 v 2  vsd 2
sq
+ Is2max (6)
Ls mr Ls mr
The current limit boundary given by Eq.(6) is an ellipse which is a function
of speed, mr . Also, the voltage limit boundary given by Eq.(4) is a circle
of constant radius. To ensure that the drive always operates within limits,
the operating region should lie in the common area bounded by the ellipse
and the circle, at the operating frequency. Eq.(6) can be written in standard
form as  vsq 2  vsd 2
+ 1 (7)
Ls mr Ismax Ls mr Ismax
Thus for a given limit stator current limit, the ellipse becomes larger as the
speed increases. Thus the inverter has to supply more voltage to regulate
the commanded value of current as the speed increases.

Machine operation below and above the rated speed

The rotor flux linkage is normally held at its rated value. The operational
limit curves plotted on the isd - isq plane is as shown in Fig.1.
Constant torque characteristics appear as rectangular hyperbolae in the
isd - isq plane. The maximum current limit is a circle. From the voltage
space phasor equations of the induction machine, we can write

~s = Ls isd + jLls isq (8)

s
2
i2sd + i i2sq = (9)
Ls
This can be written in the standard form of the ellipse as

i2sd i2sq
+ =1 (10)
Vmax 2 Vmax 2



Ls mr Lls mr

Eq.(10) represents the constant flux ellipse in the isd - isq plane. This is
shown in Fig.1. It can be seen that only a part of the maximum current
circle is allowable for operation due to the voltage limit constraint. The base
speed corresponds to the ellipse that intersects the maximum current circle
and the maximum rotor flux linkage line i.e at point D.

2
 Figure 1: Operational limits on the isd - isq plane

Maximum torque per flux linkage For a given flux linkage, the maxi-
mum torque will occur when the ellipse touches a constant torque curve at
exactly one point. Considering the ellipse equation, we get
h 2 i1
s 2 2 2
isd = i isq (11)
L2s
Using this value of isd along with the torque equation of the machine, the
locus of the points of maximum torque per flux linkage is obtained as
isd
isq = (12)
i
Eq.(12) represents a straight line in the isd - isq plane. Thus for a given
flux linkage, the maximum torque is obtained along this line. Thus dur-
ing field weakening, after hitting this line, isd shall not be further reduced.
Substituting isd = isq in the current limit equation,
r

isd = Imax (13)
1 + 2

3
Control scheme
The block diagram of the control scheme for field weakening operation is
shown in Fig.2.

Figure 2: Control block diagram for field weakening

The error between the maximum stator voltage and the actual stator
voltage is fed to a PI controller with an output limiter. The positive limit is
set at zero so that the controller becomes active only when the actual voltage
tends to exceed the maximum voltage. The output of the PI controller is
subtracted from the rated value of imr to generate the reference value.

Simulation Results
The simulation is done in Plecs software for the vector control of a 380 V, 30
kW induction machine. The variation of the speed and magnetising current
for operation with and without field weakening control is studied. These
results obtained are given in Fig.3 and Fig.4.

4
Figure 3: Variation of magnetising current with and without field weakening

Figure 4: Variation of operating frequency with and without field weakening.

5
 Directed Study on Research
Topics

Active damping of LC filter resonance

Submitted by:
Jose Titus
EE14D022
 Active damping of LC filter
resonance in a VSI-fed
vector controlled drive
Aim
To study and simulate the active damping control technique for output LC
filter in a VSI-fed vector controlled induction motor drive.

Power structure
VSI-fed vector controlled induction machine drives are widely employed in
the industry in varying range of applications. An LC filter is usually con-
nected between the inverter and the machine to filter out undesirable har-
monics from the inverter output. This makes the machine terminal voltage
and current to become very close to sinusoidal, thereby leading to increased
life of the machine and also avoiding problems due to electromagnetic inter-
ference. The power structure of the drive is as shown in Fig. 1. However, in

Figure 1: Schematic of the power circuit

a machine driven by a VSI with output filter, the motor terminal voltages
are found to oscillate at system resonant frequency. Although the magni-
tude of the resonant frequency voltage is small, the LC filter does not offer
any impedance at the resonant frequency leading to large currents flowing
between the inverter and the filter. This also causes the motor terminal
voltage to oscillate at resonant frequency. This problem can be avoided by
having a small value of resistor connected in series with the capacitors of the

1
filter. The resistors damp out the resonant components, thereby avoiding
overcurrent problems. However, use of the resistors leads to increased losses
in the system and reduced overall efficiency of the drive. Thus it is desir-
able to avoid the resistors, by emulating its effect in the control itself. This
technique is called active damping.

Active damping scheme

The equivalent circuit seen by the harmonic components, at the inverter
terminals with the LC filter connected is as shown in Fig. 2. The slip of

Figure 2: Equivalent circuit seen from the inverter terminals [?]

the machine for the harmonic frequencies is close to unity. Therefore the
rotor resistance can be neglected. Also the magnetising inductance being
much larger than the leakage inductance can be neglected for high frequency
components. With these assumptions and neglecting the stator resistance,
the equivalent circuit consists of the filter inductance and the capacitance
with the total leakage inductance of the machine connected in parallel to the
capacitor. The equivalent inductance is obtained as

Lf (Lls + Llr )
Leq = Lf ||(Lls + Llr ) = (1)
Lf + Lls + Llr

The resonant frequency of oscillations is then given as

1
n = p (2)
Leq Cf

The filter inductance value Lf is chosen so as to have a maximum voltage

drop of around 10% across it. The capacitance value is chosen so as to
have a resonant frequency around one-third of the switching frequency. The

2
dynamic equations of the drive with active damping scheme can be written
as Z
dif 1
vi = ic Rd + Leq + ic .dt (3)
dt Cf
In the active damping scheme, the capacitor currents are multiplied by a
value representing the fictitious resistance and subtracted from the source
voltages, so as to emulate the action of a resistor connected in series with the
capacitor. However, the capacitor current usually consists of the switching
frequency components along with the fundamental and resonant components.
In cases where the resonant and switching frequencies are close by, it is
difficult to extract only the resonant component. However, capacitor voltages
usually consists of only the fundamental and the resonant component and
does not contain significant switching component. Thus it is easier to extract
the capacitor current information from the information about the sensed
capacitor voltages.

Resonant frequency extraction

The sensed capacitor voltages are transformed to a synchronous frame ro-
tating at the fundamental frequency. This transforms the fundamental com-
ponent voltages to DC, which are then filtered out using a high pass filter.
The output is transformed back to the stationary frame to get the resonant
frequency signals. The block diagram for the resonant frequency extraction
scheme is as shown in Fig. 3.

Figure 3: Resonant frequency extraction block[?]

3
Control scheme
The extracted resonant frequency components are integrated to obtain vsr int ,
vsy int and vsb int . These signals lag by 180 out of phase with the resonant
capacitor current. At resonance, vres and ires are in phase. The inverter
phase delay is compensated for by advancing the integrated signals. This is
given as
vr comp = vsr int cos + vsr int sin (4)
vr comp , vy comp , vb comp are multiplied by Kdamp to emulate the resistor drop.
If is the desired damping factor, it can be shown that Kdamp = 2, where
s
Rd Cf
= (5)
2 Leq

Due to the problems associated with the use of a pure integrator, the inte-
gration is performed using a low pass filter with a very low cut off frequency.
The compensating signals obtained after multiplying by Kdamp are added to
the modulating signals of the inverter obtained from the vector control block.

Simulation Results
The active damping scheme discussed is simulated using MATLAB/PLECS.
A 30 kW VSI-fed vector controlled induction motor drive is used. The in-
verter switching frequency is kept at 2000 Hz and the corner frequency of
the LC filter is kept at 667 Hz. The results obtained are as shown below.

Figure 4: Starting current profile without Active Damping

4
 Figure 5: Starting current profile with Active Damping

Fig. 4 shows the simulated starting current profile without active damp-
ing control. Fig. 5 shows the starting response of the machine using active
damping control. The currents are well controlled and there is no resonance
observed. Without the active damping scheme, it was not possible to start
the machine due to very large resonant over currents.

Conclusion
The active damping control is studied and verified by simulations.

References
[1] K. Hatua, A.K. Jain, D. Banerjee, and V.T. Ranganathan. Active damp-
ing of output lc filter resonance for vector-controlled vsi-fed ac motor
drives. Industrial Electronics, IEEE Transactions on, 59(1):334342,
Jan 2012.

5
Directed Study on Research
Topics

Parameter Estimation Methods

Submitted by:
Jose Titus
EE14D022
 Self Commissioning scheme
for a Vector Controlled
Induction Motor Drive
Introduction
The accuracy of vector control algorithms in an induction motor drive is
heavily dependent on the accuracy with which the machine parameters are
known. These parameters are usually identified by performing the no-load
and blocked rotor tests on the machine. However, it may not be always pos-
sible to perform these tests on machines due to several constraints imposed
by field requirements. It is therefore required to identify these parameters by
other techniques. In VSI-fed vector controlled drives, the VSI can be used
to inject a desired voltage or current waveforms to the machine by using
suitable control. This fact can be used for parameter identification in the
machine by exciting the machine appropriately and analysing the response.
Several approaches towards parameter estimation and tuning of the con-
trol loops have been researched and are available in the literature. A self
tuning technique using fuzzy logic to estimate the parameters, is proposed
in [1]. However, the method is complicated and can cause issues in imple-
mentation. Another method is proposed in [2] wherein the parameters are
estimated by the response to step and DC injected currents. However, the es-
timation of rotor time constant in this method requires an additional voltage
sensor connected at the machine terminals.

Estimation of the stator transient inductance

The stator transient inductance, Ls of the machine is estimated by applying
a step voltage to the machine for a small time duration, when the machine
is at standstill. The Y- and B- phases are short circuited to the negative DC
bus during the test and hence the voltage applied is entirely along the d-axis.
The equation for d-axis voltage under these conditions can be written as
disd
vsd = Rs isd + Ls (1)
dt
The stator resistance drop can be neglected to approximate the equation as
disd
vsd = Ls (2)
dt

1
Figure 1: Waveforms from the impulse voltage test. (a) Gate pulse to the R
phase (b) R-phase current response to the applied pulse of 160 s

In the test, the pulse of magnitude equal to the DC bus voltage, Vdc is applied
for a small duration of t seconds. This duration is in the range of a few
hundred micro seconds. The current rises in a linear fashion during the test,
as a constant voltage is applied across an inductor. The change in current,
isd is noted. The value of stator transient inductance may be obtained as
Vdc t
Ls = (3)
isd
The waveform results obtained from the simulation on the 30 kW machine
are shown in Fig. 1. The stator and rotor leakage resistances can now be
computed as equal to half of the stator transient inductance.

Stator Resistance Estimation

The stator resistance is estimated by applying a DC current of rated value to
the machine and noting the voltage applied at the terminals of the machine,
at steady state. A PI controller is used for this purpose. Since the transient

2
response of the controller is not important, the controller parameters may
be chosen to have a low proportional gain and a relatively large integral
gain. The output of the PI controller is given to a PWM modulator. As
in the previous test, the Y- and B- phases are shorted to the negative DC
bus in this test also. Thus the applied current and voltage are entirely
along the d-axis. The output of the PWM controller can be directly used
to calculate the stator voltage applied. However, since the voltage required
to be applied to the machine is usually quite small(< 10V ), the error in
the calculated voltage due to the dead band effects and the switch voltage
drops can lead to significant inaccuracies. Thus these effects need to be
considered and compensated for while calculating the stator resistance. For
a given switching frequency and a given dead band, the drop in voltage can
be computed. Similarly the typical values of switch drops can be obtained
from the datasheets of the device.

Current controller tuning

Once the stator resistance and the stator transient inductance are knowm,
the current controller can be tuned to have the required bandwidth. The per
unit proportional and integral gains can be calculated as
Ls IB 2fbw
Kp =
G
Ts Rs
Ki =
Ls
where IB is the base value of current, fbw denotes the bandwidth of the
control loop in Hz and G denotes the gain of the inverter.

Rotor Time Constant Estimation

The estimation of the rotor time constant is based on the d-axis stator voltage
equation. This is given as
disd dimr
vsd = Rs isd + Ls Ls mr isq + (1 )Ls (4)
dt dt
The current controller is tuned so as to have a bandwidth of around 1kHz
for the current control loop and the switching frequency is chosen as 10 kHz.
With this choice the current controller has a settling time of less than a
millisecond. This controller is now used to inject a step DC current into the
machine R phase. The other two phases are kept shorted to the negative DC
bus terminal as in the previous tests. Once the current settles to its steady

3
Figure 2: Simulation result for the stator voltage fall with time constant, r

state value, the second term in the above equation goes to zero. Since the
machine is excited with DC current, mr is equal to zero. Thus, Eq.(4) can
be written as
dimr
vsd = Rs isd + (1 )Ls (5)
dt
Also, the instantaneous value of imr is given by the equation
dimr
isd = imr + r (6)
dt
This equation can be solved for imr to give,
t
imr = isd [1 e r ]
dimr isd t
= e r
dt r
Thus the second term in Eq.(5) falls with a time constant equal to the rotor
time constant. A corresponding fall can be observed at the output of the
pwm modulator. Thus the time taken for the modulator output minus the
resistive drop to fall to 0.368 times the initial value gives the value of the
rotor time constant. This method is well suited for machines with large time
constants in the range of hundreds of milliseconds. The same compensations
for deadband and switch drops used in the estimation of the stator resistance
test needs to be applied for this test as well. The waveform of the applied
stator voltage minus the resistive drop which falls with time constant equal
to r , obtained by simulating is as shown in Fig. 2.

4
Tuning of the flux control loop
After calculating the rotor time constant, the outer flux control loop can be
tuned. The per unit proportional and integral gains are given as

Kp = r 2fb
Ts
Ki =
Tr

Conclusion
A full cycle of all the above tests are carried out a number of times and the
results are averaged out. The speed PI controller is tuned manually after the
other loops are tuned.

References
[1] Toshiaki Kudor, K. Ishihara, and Haruo Naitoh. Self-commissioning for
vector controlled induction motors. In Industry Applications Society An-
nual Meeting, 1993., Conference Record of the 1993 IEEE, pages 528535
vol.1, Oct 1993.

[2] A.M. Khambadkone and J. Holtz. Vector-controlled induction motor

drive with a self-commissioning scheme. Industrial Electronics, IEEE
Transactions on, 38(5):322327, Oct 1991.

5
Directed Study on Research
Topics

Power Loss Calculations

Submitted by:
Jose Titus
EE14D022
 Loss Calculations for a
Three Level NPC Converter
Aim
To study the various loss occurring in a 3 level NPC converter and to quantify
the loss and thereby calculate the efficiency of the converter.

Simulation setup
A three level neutral point clamped converter was simulated in MATLAB
using PLECS blockset. The converter was controlled using an SVPWM
algorithm operating at a switching frequency of 3 kHz. It has a fixed DC bus
voltage of 1200 V and feeds power to an R-L load that draws a peak current
of 95 A.

Theory of Loss Calculation

Semiconductor switches being non-ideal devices are lossy in nature. Their
loss can be classified as conduction loss and switching loss. Conduction loss
occur when the device is conducting current in its ON state. Switching loss
occur during turn-on or turn-off of the device. Loss occurring due to leakage
currents in the blocking state are quite small and can be normally neglected.
The idea behind loss calculation is that, for a given circuit the current
and voltage waveforms during switching, and therefore the total loss energy
are principally a function of the pre-switching and post-switching conditions
at a given temperature. The loss calculation is done using the data available
from the datasheeets. IGBT with integrated anti-parallel diodes are modelled
in PLECS so as to allow the loss for both the switch and the diode to be
individually specified using lookup tables. Whether an IGBT is conducting
or a diode is conducting is decided by looking at the direction of the current
carried by the switch. From these tables, the actual loss during the simulation
are obtained by linear interpolation between the points on the table.

Computation of IGBT switching loss

Switching losses principally occur because the switching transitions are not
instantaneous. During the transition both current and voltage are substan-
tially larger than zero which leads to losses. For this simulation, the IGBT

1
 Figure 1: Turn on loss data

used is SKM100GB128D from Semikron. It is a 1200 V, 100 A device. The

turn on and turn off loss data for this device is obtained from the datasheet
and input to PLECS in the form of lookup tables as shown in Fig.1 and
Fig.2.

Figure 2: Turn off loss data

2
 Figure 3: Conduction loss table for IGBT

Computation of IGBT conduction losses

The on state voltage can be specified as a function of the device temperature
and current using a lookup table obtained from the datasheets. The con-
duction losses are then calculated as a product of the instantaneous current
and on state voltage during conduction. The conduction loss table input to
PLECS is shown below. The negative values of current in the table corre-
spond to the diode conduction.

Figure 4: Diode turn off losses

3
Losses for the clamping diode
The losses for the clamping diode are specified in a similar manner as for
the IGBT using lookup tables from the datasheet. Powerex make R-502 fast
recovery diodes are used. The loss tables for these are obtained from the
datasheet and are shown in Fig.4.

Results
The simulation gave the following results.

Total Clamping Diode switching loss = 2 W

Total Clamping Diode conduction loss = 78 W
Total IGBT switching loss = 140 W
Total IGBT conduction loss = 750 W
Total loss in the converter = 970 W
Total DC Input power = 88536 W
Converter Efficiency = 98.904 %

Conclusion
The losses and the efficiency of the 3 level inverter feeding an RL load is
evaluated.