VND5T050AK-E

Double channel high-side driver with analog current sense

for 24 V automotive applications
Datasheet production data

Features

Max transient supply voltage VCC 58 V

Operating voltage range
Typ On-State resistance (per ch.)
Current limitation (typ)
Off state supply current
General
Very low standby current
3.0 V CMOS compatible input
Optimized electromagnetic emission
Very low electromagnetic susceptibility
Compliance with European directive
2002/95/EC
Fault reset standby pin (FR_Stby)
Diagnostic Functions
Proportional load current sense
High current sense precision for wide range
currents
Off-state open load detection
Output short to VCC detection
Overload and short to ground latch off
Thermal shutdown latch-off
Very low current sense leakage
Protections
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Protection against loss of ground and loss
of VCC
Thermal shutdown
Electrostatic discharge protection
VCC 8 to 36V
RON 50 m
PowerSSO-24
ILIM 34 A
IS 2 A Application
All types of resistive, inductive and capacitive
loads
Description
The VND5T050AK-E is a monolithic device made
using STMicroelectronics VIPower technology,
intended for driving resistive or inductive loads
with one side connected to ground. Active VCC pin
voltage clamp protects the device against low
energy spikes.
This device integrates an analog current sense
which delivers a current proportional to the load
current.
Fault conditions such as overload,
overtemperature or short to VCC are reported via
the current sense pin.
Output current limitation protects the device in
overload condition. The device will latch off in
case of overload or thermal shutdown.
The device is reset by a low level pass on the fault
reset standby pin.
A permanent low level on the inputs and fault
reset standby pin disable all outputs and set the
device in standby mode.

September 2013 Doc ID 022694 Rev. 3 1/32

This is information on a product in full production. www.st.com 1
Contents VND5T050AK-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Maximum demagnetization energy (VCC = 24 V) . . . . . . . . . . . . . . . . . . 23

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32 Doc ID 022694 Rev. 3

VND5T050AK-E List of tables

List of tables

Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC = 24 V; Tj = 25 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Current sense (8 V < VCC < 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Open-load detection (VFR_STBY = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 14. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Doc ID 022694 Rev. 3 3/32

List of figures VND5T050AK-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram PowerSSO-24 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Treset definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Tstby definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Output stuck to VCC detection delay time at FRSTBY activation . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Delay response time between rising edge of output current and rising edge of current
sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 20. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 25. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 27. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . . 24
Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 25
Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 25
Figure 30. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 31. PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 32. PowerSSO-24 tape and reel shipment (suffix TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4/32 Doc ID 022694 Rev. 3

VND5T050AK-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

VCC

Signal Clamp

Control & Diagnostic 2

Undervoltage
Control & Diagnostic 1
Power
Clamp

IN1 DRIVER

IN2 CH1
VON
Limitation

Over Current
Temperature Limitation

OFF-state
Open-load
FR_Stby
VSENSEH

CS1
Current CH2
Sense
CS2 OUT2

OUT1
OVERLOAD PROTECTION
LOGIC (ACTIVE POWER LIMITATION)

GND
GAPGCFT00643

Table 1. Pin function

Name Function

VCC Battery connection

OUT1,2 Power output
GND Ground connection
Voltage controlled input pins with hysteresis, CMOS compatible. They control output
IN1,2
switch state
CS1,2 Analog current sense pins, they deliver a current proportional to the load current
In case of latch-off for overtemperature/overcurrent conditions, a low pulse on the
FR_Stby FR_Stby pin is needed to reset the channel.
The device enters in standby mode if all inputs and the FR_Stby pin are low.

Doc ID 022694 Rev. 3 5/32

Block diagram and pin description VND5T050AK-E

Figure 2. Configuration diagram PowerSSO-24 (top view)

9&& 287
1& 287
&6 287
,1 287
1& 287
)5B6WE\ 287
*1' 287
1& 287
,1 287
&6 287
1& 287
9&& 287

7$% 9&&

0O WER33/  ("1($'5

Table 2. Suggested connections for unused and not connected pins

Connection / pin Current Sense N.C. Output Input FR_Stby

Floating Not allowed X(1) X X X

Through 10 K Through 10 K
To ground X Not allowed Through 10 K
resistor resistor
1. X: do not care.

6/32 Doc ID 022694 Rev. 3

VND5T050AK-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

IS

VCC VCC
VFn
IFR_Stby IOUTn
FR_Stby OUTn
VOUTn
VFR_Stby
IINn ISENSEn
CSn
INn VSENSEn
VINn

GND

IGND

Note: VFn = VOUTn - VCC during reverse battery condition.

2.1 Absolute maximum ratings

Stressing the device above the ratings listed in Table 3 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not
implied. Exposure to the conditions reported in this section for extended periods may affect
device reliability.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC DC supply voltage 58 V

-VCC Reverse DC supply voltage 0.3 V

-IGND DC reverse ground pin current 200 mA

IOUT DC output current Internally limited A

-IOUT Reverse DC output current 30 A

IIN DC input current -1 to 10 mA

IFR_Stby Fault reset standby DC input current -1 to 1.5 mA

-ICSENSE DC reverse CS pin current 200 mA

VCC - 58 to
VCSENSE Current sense maximum voltage V
+VCC
Maximum switching energy
EMAX 210 mJ
L = 50 mH; Vbat = 32 V; Tjstart = 150C; IOUT = 2 A

Doc ID 022694 Rev. 3 7/32

Electrical specifications VND5T050AK-E

Table 3. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Maximum strain inductance in short circuit condition

Lsmax 40 H
RL = 300 m, Vbatt = 32 V, Tjstart = 150C, lout = ILMHmax
Electrostatic discharge
(Human Body Model: R = 1.5 K; C = 100 pF)
IN1,2 4000 V
VESD CS1,2 2000 V
FR_Stby 4000 V
OUT1,2 5000 V
VCC 5000 V
VESD Charge device model (CDM-AEC-Q100-011) 750 V

Tj Junction operating temperature -40 to 150 C

Tstg Storage temperature -55 to 150 C

2.2 Thermal data

Table 4. Thermal data
Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case (max.) (with one channel ON) 2 C/W
See
Rthj-amb Thermal resistance junction-ambient (max.) C/W
Figure 27

8/32 Doc ID 022694 Rev. 3

VND5T050AK-E Electrical specifications

2.3 Electrical characteristics

8 V < VCC < 36 V; -40C < Tj < 150C, unless otherwise specified.

Table 5. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC Operating supply voltage 8 24 36 V

VUSD Undervoltage shutdown 3.5 5 V
Undervoltage shutdown
VUSDhyst 0.5 V
hysteresis
IOUT = 2 A; Tj = 25C 50
RON On-state resistance(1) m
IOUT = 2 A; Tj = 150C 100
Vclamp Clamp voltage IS = 20 mA 58 64 70 V
Off-state; VCC = 24 V; Tj = 25C;
2(2) 5(2) A
VIN = VOUT = VSENSE = 0 V
IS Supply current
On-state; VCC = 24 V; VIN = 5 V;
4.2 6 mA
IOUT = 0 A
VIN = VOUT = 0 V; VCC = 24 V;
0 0.01 3
Tj = 25C
IL(off) Off-state output current A
VIN = VOUT = 0 V; VCC = 24 V;
0 5
Tj = 125C
Output - VCC diode
VF -IOUT = 2 A; Tj = 150C 0.7 V
voltage
1. For each channel
2. PowerMOS leakage included

Table 6. Switching (VCC = 24 V; Tj = 25 C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time RL= 12 30 s

td(off) Turn-off delay time RL= 12 40 s
dVOUT/dt(on) Turn-on voltage slope RL= 12 0.7 V/us V/s
dVOUT/dt(off) Turn-off voltage slope RL= 12 0.8 V/us V/s
Switching energy losses
WON RL= 12 0.5 mJ
during twon
Switching energy losses
WOFF RL= 12 0.3 mJ
during twoff

Doc ID 022694 Rev. 3 9/32

Electrical specifications VND5T050AK-E

Table 7. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low level voltage 0.9 V

IIL Low level input current VIN = 0.9 V 1 A
VIH Input high level voltage 2.1 V
IIH High level input current VIN = 2.1 V 10 A
VI(hyst) Input hysteresis voltage 0.25 V
IIN = 1 mA 5.5 7 V
VICL Input clamp voltage
IIN = -1 mA -0.7 V
Fault reset standby low level
VFR_Stby_L 0.9 V
voltage
Low level fault reset standby
IFR_Stby_L VFR_Stby = 0.9 V 1 A
current
Fault reset standby high level
VFR_Stby_H 2.1 V
voltage
High level fault reset standby
IFR_Stby_H VFR_Stby = 2.1 V 10 A
current
VFR_Stby Fault reset standby hysteresis
0.25 V
(hyst) voltage

Fault reset standby clamp IFR_Stby = 15 mA (t < 10 ms) 11 15 V

VFR_Stby_CL
voltage IFR_Stby = -1 mA -0.7 V
treset Overload latch-off reset time See Figure 4 2 24 s
tstby Standby delay See Figure 5 120 1200 s

Figure 4. Treset definition

7BUHVHW

)5B67%<

,1

287387

&6

2YHUORDG
&KDQQHO

*$3*&)7

10/32 Doc ID 022694 Rev. 3

VND5T050AK-E Electrical specifications

Figure 5. Tstby definition

)5B6WGE\

,1387Q

,*1'

WVWE\ WVWE\

*$3*&)7

Table 8. Protections and diagnostics

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC = 24 V 24 34 46 A
IlimH DC short circuit current
5 V < VCC < 36 V 46 A
Short circuit current VCC = 24 V;
IlimL 8.5 A
during thermal cycling TR < Tj < TTSD
TTSD Shutdown temperature 150 175 200 C
TR Reset temperature TRS + 1 TRS + 5 C
TRS Thermal reset of status 135 C
Thermal hysteresis
THYST 7 C
(TTSD-TR)
Turn-off output voltage IOUT = 2 A; VIN = 0;
VDEMAG VCC - 58 VCC - 64 VCC - 70 V
clamp L = 6 mH
Output voltage drop
VON IOUT= 100 mA 25 mV
limitation

Table 9. Current sense (8 V < VCC < 36 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

IOUT = 10 mA; VSENSE = 0.5 V;

K_ol Tj = -40C...150C 564 5563
2800
Tj = 25C...150C 972 4895
IOUT = 50 mA; VSENSE = 0.5 V;
Kled Tj = -40C...150C 1193 4268
2650
Tj = 25C...150C 1416 3958
I = 12 mA to 60 mA;
dK/Ktotled Current sense ratio drift OUT -35 35 %
VSENSE = 0.5 V; Ical = 35 mA
IOUT = 100 mA; VSENSE = 0.5 V;
K0 IOUT/ISENSE 1409 2540 3726
Tj = -40C...150C
I = 100 mA; VSENSE= 0.5 V;
dK0/K0(1) Current sense ratio drift OUT -20 20 %
Tj = -40C to 150C

Doc ID 022694 Rev. 3 11/32

Electrical specifications VND5T050AK-E

Table 9. Current sense (8 V < VCC < 36 V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

IOUT = 0.7 A; VSENSE= 2 V;

K1 IOUT/ISENSE 1597 2190 2764
Tj = -40 C...150 C
I = 0.7 A; VSENSE = 2 V;
dK1/K1(1) Current sense ratio drift OUT -15 15 %
Tj = -40 C...150 C
IOUT = 2 A; VSENSE = 2 V;
K2 IOUT/ISENSE 1850 2190 2550
Tj = -40 C...150 C
I = 2 A; VSENSE= 2 V;
dK2/K2(1) Current sense ratio drift OUT -10 +10 %
Tj = -40 C...150 C
IOUT = 8 A; VSENSE = 4 V;
K3 IOUT/ISENSE 2050 2190 2280
Tj = -40 C...150 C
I = 8 A; VSENSE= 4 V;
dK3/K3(1) Current sense ratio drift OUT -3 3 %
Tj = -40 C...150 C
IOUT = 0 A; VSENSE = 0 V;
0 1 A
Analog sense leakage VIN = 0 V; Tj = -40C...150C
ISENSE0
current IOUT = 0 A; VSENSE = 0 V;
0 2 A
VIN = 5 V; Tj = -40C...150C
Max analog sense
VSENSE IOUT = 8 A; RSENSE = 3.9 K 5 V
output voltage
Analog sense output
VSENSEH voltage in fault VCC = 24 V; RSENSE = 3.9 K 7.5 8.5 9.5 V
condition(2)
Analog sense output
ISENSEH current in fault VCC = 24 V; VSENSE = 5 V 4.9 7 12 mA
condition (2)

Delay response time VSENSE < 4 V; 0.15 A < IOUT < 8 A

tDSENSE2H from rising edge of ISENSE = 90 % of ISENSE max 150 300 s
INPUT pins (see Figure 6)
Delay response time VSENSE < 4 V;
between rising edge of ISENSE = 90% of ISENSEMAX,
tDSENSE2H output current and 250 s
IOUT = 90% of IOUTMAX
rising edge of current
sense IOUTMAX = 2 A (see Figure 10)

Delay response time VSENSE < 4 V, 0.15 A < IOUT < 8 A

tDSENSE2L from falling edge of ISENSE = 10 % of ISENSE max 5 20 s
INPUT pins (see Figure 6)
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open load in off-state condition.

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VND5T050AK-E Electrical specifications

Table 10. Open-load detection (VFR_STBY = 5 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Open-load off-state
VOL voltage detection VIN = 0 V; 8 V < VCC < 36 V 2 4 V
threshold
Output short circuit to
tDSTKON VCC detection delay at See Figure 7 180 1800 s
turn off
Off-state output current VIN = 0 V; VSENSE = 0 V;
IL(off2) -120 0 A
at VOUT = 4 V VOUT rising from 0 V to 4 V
Delay response from VOUT = 4 V; VIN = 0 V;
output rising edge to VSENSE = 90 % of VSENSEH
td_vol 20 s
VSENSE rising edge in
Rsense=3.9K
openload
Output short circuit to
tDFRSTK_ON VCC detection delay at See Figure 10; Input1,2 = low 50 s
FRSTBY activation

Figure 6. Current sense delay characteristics

INPUT

LOAD CURRENT
SENSE CURRENT
tDSENSE2H tDSENSE2L

Figure 7. Open-load off-state delay timing

OUTPUT STUCK TO VCC

VIN
VOUT > VOL

VSENSEH

VCS

tDSTKON

1. Vfr_stby = high.

Doc ID 022694 Rev. 3 13/32

Electrical specifications VND5T050AK-E

Figure 8. Output stuck to VCC detection delay time at FRSTBY activation

)567%<

9VHQVH+

9&6

W')567.B21
,QSXW /RZ
*$3*&)7

Figure 9. Switching characteristics

VOUT
tWon tWoff

90%
80%

dVOUT/dt(on) dVOUT/dt(off)

tr 10% tf

INPUT
td(on) td(off)

14/32 Doc ID 022694 Rev. 3

VND5T050AK-E Electrical specifications

Figure 10. Delay response time between rising edge of output current and rising
edge of current sense

VIN

tDSENSE2H

IOUT
IOUTMAX

90% IOUTMAX

ISENSE ISENSEMAX

90% ISENSEMAX

Figure 11. Output voltage drop limitation

Vcc-Vout

Tj=150oC Tj=25oC

Tj=-40oC

Von

Iout
Von/Ron(T)

Doc ID 022694 Rev. 3 15/32

Electrical specifications VND5T050AK-E

Figure 12. Device behavior in overload condition

t reset t reset

FAULT_RESET

INn

OUTPUTn

VsenseH
CSn

overload
OVERLOAD(*) overload reset
CHANNELn overload diag reset

1 2 3 4 5 6 7 8

1: OUTPUTn and CSn controlled by INn.

2: FAULT_RESET from 0 to 1 no action on CSn pin
3: Overload latch-off. INn high CSn high
4: FAULT_RESET low AND Temp channeln < overload_reset Overload latch reset after t_reset
4 to 5: FAULT_RESET low AND INn high thermal cycling, CSn high
5: FAULT_RESET high latch-off reset disabled
6 to 7: Overload event and FAULT_RESET high latch-off, no thermal cycling
7 to 8: Overload diagnostic disabled/enabled by the input
8: Overload latch-off reset by FAULT_RESET

(*) OVERLOAD = Thermal shutdown OR Power Limitation

16/32 Doc ID 022694 Rev. 3

VND5T050AK-E Electrical specifications

Table 11. Truth table

Conditions Fault reset standby Input Output Sense

Standby L L L 0
X L L 0
Normal operation
X H H Nominal
X L L 0
Overload
X H H > Nominal
X L L 0
Overtemperature / short to ground L H Cycling VSENSEH
H H Latched VSENSEH
Undervoltage X X L 0
L L H 0
Short to VBAT H L H VSENSEH
X H H < Nominal
L L H 0
Open load off-state (with pull-up) H L H VSENSEH
X H H 0
Negative output voltage clamp X L Negative 0

Doc ID 022694 Rev. 3 17/32

Electrical specifications VND5T050AK-E

Table 12. Electrical transient requirements (part 1)

ISO 7637-2: Test levels (1) Number of
2004(E) Burst cycle/pulse Delays and
pulses or
repetition time impedance
Test pulse III IV test times

5000
1 - 450 V - 600 V 0.5 s 5s 1 ms, 50
pulses
5000
2a + 37 V + 50 V 0.2 s 5s 50 s, 2
pulses

3a - 150 V - 200 V 1h 90 ms 100 ms 0.1 s, 50

3b + 150 V + 200 V 1h 90 ms 100 ms 0.1 s, 50

4 - 12 V - 16 V 1 pulse 100 ms, 0.01

5b(1) + 123 V + 174 V 1 pulse 350 ms, 1

1. Valid in case of external load dump clamp: 58 V maximum referred to ground.

Table 13. Electrical transient requirements (part 2)(1)

ISO 7637-2: Test level results
2004(E)
Test pulse III IV

1 C C

2a C C

3a C C

3b(2) E E

3b(3) C C

4 C C

5b (4) C C

1. In order to garantee the ISO transient classes a minimum 10 K protection resistors are needed an logic
pins.
2. Without capacitor between VCC and GND.
3. With 10 nF between VCC and GND.
4. External load dump clamp, 58 V maximum, referred to ground.

Table 14. Electrical transient requirements (part 3)

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to
E
disturbance and cannot be returned to proper operation without replacing the device.

18/32 Doc ID 022694 Rev. 3

VND5T050AK-E Electrical specifications

2.4 Electrical characteristics curves

Figure 13. Off-state output current Figure 14. High level input current

,ORII>X$@
,LK>X$@




 9LQ 9




2II6WDWH 
9FF 9
9LQ 9RXW  










         
         
7F>&@ ("1($'5
7F>&@
("1($'5

Figure 15. Input clamp voltage Figure 16. Input low level voltage

9LFO>9@ 9LO>9@

 

 

 ,LQ P$ 

 

 

 

 

 

 

 

 
                   

7F>&@ 7F>&@
("1($'5 ("1($'5

Figure 17. Input high level voltage Figure 18. Input hysteresis voltage

9LK>9@ 9LK\VW>9@
 

 






 

 






 
                   
7F>&@ ("1($'5 7F>&@ ("1($'5

Doc ID 022694 Rev. 3 19/32

Electrical specifications VND5T050AK-E

Figure 19. On-state resistance vs Tcase Figure 20. On-state resistance vs VCC

5RQ>P2KP@ 5RQ>P2KP@

 
  7F &

 
 
 ,RXW $  7F &
 9FF 9 
  7F &
 
7F &
 
 
 
 
                 

7F>&@ 9FF>9@
("1($'5 ("1($'5

Figure 21. ILIMH vs Tcase Figure 22. Turn-on voltage slope

,OLPK>$@ G9RXWGW2Q>9XV@

 

 

 
9FF 9
9FF 9
 5O 














         
         
7F>&@
("1($'5 7F>&@ ("1($'5

Figure 23. Turn-off voltage slope

G9RXWGW2II>9XV@




9FF 9
 5O 










         

7F>&@ ("1($'5

20/32 Doc ID 022694 Rev. 3

VND5T050AK-E Application information

3 Application information

Figure 24. Application schematic

+5V
VCC

Rprot FR_Stby

Dld
Rprot IN
MCU
OUT
Rprot CS

GND

RSENSE RGND
VGND DGND
Cext

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (RGND only)

This solution can be used with any type of load.
The following equations are an indication on how to size the RGND resistor.
1. RGND 600 mV / (IS(on)max).
2. RGND (VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC < 0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.

Doc ID 022694 Rev. 3 21/32

Application information VND5T050AK-E

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests Solution 2 is used (see below).

3.1.2 Solution 2: diode (DGND) in the ground line

A resistor (RGND = 4.7 k) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (600 mV) in the input
threshold and in the status output values, if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO T/R 7637/2 table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests that a resistor (Rprot) be inserted in line
to prevent the microcontroller I/O pins from latching-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= -600 V and Ilatchup 20 mA; VOHC 4.5 V
30 k Rprot 180 k.
Recommended Rprot value is 60 k.

22/32 Doc ID 022694 Rev. 3

VND5T050AK-E Application information

3.4 Maximum demagnetization energy (VCC = 24 V)

Figure 25. Maximum turn-off current versus inductance


"
91'7 6LQJOH 3XOVH
# 5HSHWLWLYHSXOVH7MVWDUW  &
$ 5HSHWLWLYHSXOVH7MVWDUW  &
,$


  
/P+ *$3*&)7

A: Tjstart = 150C single pulse

B: Tjstart = 100C repetitive pulse
C: Tjstart = 125C repetitive pulse

VIN, IL

Demagnetization Demagnetization Demagnetization

1. Values are generated with RL =0 .

In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not
exceed the temperature specified above for curves A and B.

Doc ID 022694 Rev. 3 23/32

Package and PCB thermal data VND5T050AK-E

4 Package and PCB thermal data

4.1 PowerSSO-24 thermal data

Figure 26. PowerSSO-24 PC board

GAPGCFT00418

1. Layout condition of Rth and Zth measurements (board finish thickness 1.6 mm +/- 10%; board double layer;
board dimension 77x86; board Material FR4; Cu thickness 0.070mm (front and back side); thermal vias
separation 1.2 mm; thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm; footprint
dimension 4.1 mm x 6.5 mm).

Figure 27. Rthj-amb vs PCB copper area in open box free air condition (one channel
ON)

57+MDPE

57+MDPE









     

3&%&XKHDWVLQNDUHDFPA
("1($'5

24/32 Doc ID 022694 Rev. 3

VND5T050AK-E Package and PCB thermal data

Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one
channel ON)
ZTH (C/W)
100
Cu=8 cm2
Cu=2 cm2
Cu=foot print

10

1
0.01 0.1 1 10 100 1000
Time (s)
GAPGCFT00634

Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24

1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered

Equation 1: Pulse calculation formula

Z TH = R TH + Z THtp ( 1 )
where = tp T

Doc ID 022694 Rev. 3 25/32

Package and PCB thermal data VND5T050AK-E

Table 15. Thermal parameters

Area/island (cm2) Footprint 2 8

R1 = R7 (C/W) 0.6

R2 = R8 (C/W) 0.75

R3 (C/W) 1

R4 (C/W) 7.7

R5 (C/W) 9 9 8

R6 (C/W) 28 17 10

C1 = C7 (W.s/C) 0.005

C2 = C8 (W.s/C) 0.01

C3 (W.s/C) 0.05

C4 (W.s/C) 0.3

C5 (W.s/C) 1 4 9

C6 (W.s/C) 2.2 5 17

26/32 Doc ID 022694 Rev. 3

VND5T050AK-E Package and packing information

5 Package and packing information

5.1 ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

5.2 PowerSSO-24 mechanical data

Figure 30. PowerSSO-24 package dimensions

Doc ID 022694 Rev. 3 27/32

Package and packing information VND5T050AK-E

Table 16. PowerSSO-24 mechanical data

Millimeters
Symbol
Min. Typ. Max.

A 2.15 2.47
A2 2.15 2.40
a1 0 0.075
b 0.33 0.51
c 0.23 0.32
D 10.10 10.50
E 7.4 7.6
e 0.8
e3 8.8
G 0.1
G1 0.06
H 10.1 10.5
h 0.4
k 5
L 0.55 0.85
N 10
X 4.1 4.7
Y 6.5 7.1

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VND5T050AK-E Package and packing information

5.3 PowerSSO-24 packing information

Figure 31. PowerSSO-24 tube shipment (no suffix)

Base Q.ty 49
Bulk Q.ty 1225
C Tube length ( 0.5) 532
B
A 3.5
B 13.8
C ( 0.1) 0.6
All dimensions are in mm.
A

Figure 32. PowerSSO-24 tape and reel shipment (suffix TR)

Reel dimensions

Base Q.ty 1000

Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C ( 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 100
T (max) 30.4

Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 24
Tape Hole Spacing P0 ( 0.1) 4
Component Spacing P 12
Hole Diameter D ( 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F ( 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 ( 0.1) 2

All dimensions are in mm. End

Start
Top No components Components No components
cover
tape 500mm min 500mm min
Empty components pockets
saled with cover tape.

User direction of feed

Doc ID 022694 Rev. 3 29/32

Order codes VND5T050AK-E

6 Order codes

Table 17. Device summary

Order codes
Package
Tube Tape and reel

PowerSSO-24 VND5T050AK-E VND5T050AKTR-E

30/32 Doc ID 022694 Rev. 3

VND5T050AK-E Revision history

7 Revision history

Table 18. Document revision history

Date Revision Changes

07-Feb-2012 1 Initial release.

Updated Table 2: Suggested connections for unused and not
connected pins
Table 9: Current sense (8 V < VCC < 36 V):
30-Mar-2012 2
dK0/K0: updated test condition from IOUT = 100 A to IOUT = 100 mA
Table 13: Electrical transient requirements (part 2):
added note
18-Sep-2013 3 Updated disclaimer.

Doc ID 022694 Rev. 3 31/32

 VND5T050AK-E

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32/32 Doc ID 022694 Rev. 3