AKHIL V MENON

+91 8050323819 | akvmenon@gmail.com | Bangalore, India

SUMMARY
Overall 3+ years of experience in Semiconductor/VLSI industry as RTL Design Engineer and
Design Automation Engineer
Experience in RTL Design in System Verilog for memory compilers, memory periphery circuitry
and various complex power state modeling
Experience in development of a System Verilog based verification methodology for the RTL
Experience in development and verification of UPF modeling for memories with complex power
states
Experience in development of ATPG,MBIST models for memory compilers
Experience in Perl Developed a QA tool for memory compilers that checks the quality of various
types of views before delivery Physical Views-LEF, GDS, netlist Front-End views- RTL, UPF,
ATPG, MBIST
Integral part of the sole Memory Compiler Team that has multiple customers internal as well as
external to Intel

PROFESSIONAL EXPERIENCE
Intel India Pvt. Ltd. Bangalore, India
RTL Design Engineer Dec 2014 Now
Responsible for RTL implementation of Register Files and Read only memories. This involves
Array, periphery, X-handling logic, fault injection modelling, power-aware RTL, SV assertions
Responsible for functional verification with the development of a verification environment that
generates randomized stimuli and outputs coverage numbers on both code and functional aspects
Responsible for modelling of UPF for the memory models and validating them through power-
aware simulation and comparison with liberty
Responsible for verification of the RTL model with back annotation from the lib models
Responsible for development of ATPG models of memories and making sure of high coverage
numbers
Responsible for development of MBIST models of memories and validating various Algorithms on
those models.
Responsible for verifying Formal Equivalence between the memory circuit and RTL
Integral part of 3 major process nodes and more than 5 memory Compiler project releases to
Internal as well as external customers

Design Automation Engineer Dec 2013 Dec 2014

Responsible for Development of QA tool used across by all major memory Compiler teams in Intel
Tool developed based on Perl using industry standard parsers for all major views LEF, liberty,
RTL thus ensuring reusability and performance
Developed Code testing infrastructure based on Test module in Perl to ensure quality before
release
Developed an automated regression suite that runs extensive QA checks on all range of compilers
that the tool is targeted for before release
This Tool is the sign off QA tool for all releases within the memory Compiler Team in Intel that
delivers RF,ROM,SRAM compilers to various customers

Ak hil V M e n o n | +9 1 8 0 5 0 3 2 3 8 1 9 | a k v me n o n @ g ma i l.co m
 Graduate Technical Intern Aug 2012 July 2013
Responsible for functional verification of loopback architectures in Xeon Server
Improved simulation speed and memory usage by Sim profiling for Full chip XEON server
simulations and identified areas of improvement 10% time savings 40% memory savings

SKILLS AND TOOLS

Tools/Methodologies : System Verilog based verification, Synopsys VCS , Synopsys Verdi
Automated Debug system, Cadence NC Simulator, Altera ModelSim, Mentor
Graphics Questa Sim, Mentor Graphics Tessent Fastscan, Mentor Graphics
Tessent ETChecker, Synopsys ESP CV, Synopsys PrimeTime, Synopsys
Design Compiler
Scripting : Perl, Tcl, Bash shell
HDL : System Verilog HDL
ACADEMIC CREDENTIALS
M.Tech. VLSI Design VIT University, Vellore, Tamil Nadu 2013 8.78 CGPA
B.Tech. Electronics & Communication Engg. - University of Calicut, Kerala 2011 70%

ACHIVEMENTS
Various Awards from stakeholders for contributions to the team, projects
Won First place in presentation at 3rd International Conference on Science, Engineering and
Technology at VIT University, Vellore
Obtained First position in XII CBSE Board Physics at School level

PERSONAL PROFILE
Gender, Nationality : Male, Indian
Date of Birth : 6th Sep 1989
Languages : English, Malayalam
Present Address : #14, 1st Floor, Flat #B1, Near Blue Hyundai Service Center, Opposite
Koramangala Police Station, Koramangala, Bangalore, Karnataka. Pin:
560095
DECLARATION
I hereby declare that the information furnished above is true to the best of my knowledge and
belief.

Place: Bangalore
Date: 6th February 2017 Akhil V Menon

Ak hil V M e n o n | +9 1 8 0 5 0 3 2 3 8 1 9 | a k v me n o n @ g ma i l.co m