Application Report

SPRABW6June 2014

Using K2L Devices for Dual Mode (LTE + WCDMA)

Applications
High-Performance and Multicore Processors

Abstract
This document describes the approach used in modeling and testing that was
performed on a K2L device to show the viability of implementing simultaneous dual
mode (LTE + WCDMA) applications on the K2L device family. The content of this
paper is covering the following topics: goals, parameters, implementation, and results.
Additional information for obtaining software solutions and support for simultaneous
dual mode application development is provided at the end of this document.

Dual Mode (LTE+WCDMA) Modeling/Testing

Goals
The goals of the dual mode modeling and testing included the following:
1. Partition the work flow and tasks required by dual mode base stations and map
them to software or hardware on a K2L device
2. Implement a dual mode test scenario that exercises the most significant flows (as
opposed to implementing a full system with full production software) and run it
on a K2L device to measure the desired metrics on real silicon. Most of the
software functionality (except hardware accelerator drivers) are replaced by stubs
representing the approximate potential cost of execution in terms of core cycles
and infrastructure traffic.

Parameters
The LTE and WCDMA parameters chosen for the dual mode test scenario are shown
in Table 1-1.
Table 1-1 LTE and WCDMA Parameters Chosen for Dual Mode Test Scenario
Parameter LTE-FDD (Rel 8) WCDMA (Rel. 9 DC-HSPA)
Bandwidth 10 MHz 10 MHz
Number of Cells 1 Dual Carrier
Number of Users Up to 64 Up to 32
Downlink Throughput (peak per cell) 75 Mbps 42 Mbps
Uplink Throughput (peak per cell) 37 Mbps 21 Mbps
Sector Size 2 km 2 km
Transmission (MIMO) 2x2 STTD
Reception (SIMO) 1x2 Div.
End of Table 1-1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications
of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

SPRABW6June 2014 Using K2L Devices for Dual Mode (LTE + WCDMA) Applications Application Report Page 1 of 10
Submit Documentation Feedback
 www.ti.com

In addition to the LTE and WCDMA parameters, the K2L device has several SOC
hardware settings that were selected as shown in Table 1-2.
Table 1-2 SOC Settings Chosen for Dual Mode Test Scenario
Setting Value Selected
System and DSP CorePac Clock Speed 1.2 GHz
ARM CorePac Clock Speed 1.2 GHz
External DDR Memory Type/Speed DDR3-1600 (No ECC)
End of Table 1-2

Implementation
As mentioned earlier, one of the goals of this modeling and testing was to show the
viability of a real dual mode application without implementing a full system with
complete software. This meant exercising the most significant processing flows and
selecting functional software for some processing tasks and latency models for others.

The chosen partitioning of the two standards on the K2L architecture is highlighted in
Figure 1.
Figure 1 System Partitioning Diagram

ARM TITCI66xDSP
PHY/Layer2ProcessingLayers
Core#0 Core#1
LTEPHY LTEL2
Core#0 PUSCH/PUCCH RLC/MACdata
path
PDSCH/PDCCH
Traffic UL/DL
PRACH,SRS Schedulers
generation
emulating Core#2 Core#3
L3&OAM
WCDMAPHY WCDMAPHY

ULxDCH/ DLHSPA/DCH
xCCH
PRACH

RadioAcceleration

Packet&SecurityAcceleration

Page 2 of 10 Using K2L Devices for Dual Mode (LTE + WCDMA) Applications Application Report SPRABW6June 2014
Submit Documentation Feedback
www.ti.com

LTE Processing LTE processing for Layer 1 and Layer 2 were modeled on DSP cores 0 and 1 and a
Layer 3 traffic generation model was run on ARM cores. The LTE Layer 1 processing
flows for uplink, PRACH, and downlink that were implemented are shown in Figure 2,
Figure 3, and Figure 4, respectively. These flow diagrams also show which processing
tasks were run on hardware accelerators in the device and which tasks were mapped to
software. All of the LTE software tasks were implemented as latency models to allow
flexibility during development and avoid developing and optimizing all of the
LTE-specific software/algorithms.

Figure 2 LTE Layer 1 Uplink Processing Flows Implemented (PUSCH and PUCCH)
DSP Core 0

Color Legend Just pass input data for

both ant symbols 13 SRS UE Parse Channel
HW Measurement
And Group Sounding
Task

SW Copy data to MSMC when

Task all channelEstim are
completed for Ant0 and 1
Shared
Only one write per Mem
subframe
Transfer done using
infrastructure DMA (cppi) PucchSR DDR3
IQNET RX
Copy the whole Transfer done using
subframe data infrastructure DMA (cppi)
to DDR
PUCCH
PucchAckNak DDR3
Preproc
Just pass input data for
Shared DDR3 both ant symbols 13
Mem
Transfer done using
infrastructure DMA (cppi)
PucchCQI Pucch DDR3
PucchCqi
BCP Measurement

FreqOffset UL Bit Proc

Shared Compensation TCP3D CRC Check DDR3 ToLayer2
Equalization IDFT Mem (DSP) BCP ULinput

Both ant all

symbols
Ant 0/1
symbols 3, 10
FFT RX Task ChannelEstim

Just pass input

data

FreqOffset
FreqOffset FreqOffset
Comp and
DFT IDFT
Estim

Figure 3 LTE Layer 1 PRACH Processing Flow Implemented

Color Legend

HW
Task
DRR3
R AC H is executed every 3 ms SW
Task
DSP Core 0
For antenna 0 and 1 For antenna 0 and 1 Per RootNr

Load Sub-block DRR3 BigDFT DRR3 Power Compute

DFT_3072 MatchFilter RACH_IFFT Peaksearch
Sequence Division Stage2 And ADD

SPRABW6June 2014 Using K2L Devices for Dual Mode (LTE + WCDMA) Applications Application Report Page 3 of 10
Submit Documentation Feedback
 www.ti.com

Figure 4 LTE Layer 1 Downlink Processing Flows Implemented (PDSCH and PDCCH)
DSP Core 0

Per Transport Block Per Symbol Per Symbol per Antenna

SRIO DDR3 Pre-Encode BCP LayerMapping Resource Shared

IFFT IQNET TX
Proc DL_TB_proc int Mapping Mem

PDCCH

Color Legend

FromLayer2
HW

DLflow
Task

SW
Task

The LTE Layer 2 tasks were also implemented using software latency models. These
software tasks included the following:
Uplink RLC/MAC and Uplink HARQ + scheduler software tasks mapped on
DSP core 1
Downlink RLC/MAC, PDCCH mapping, and Downlink HARQ + scheduler
tasks mapped also on DSP core 1

The synchronous and asynchronous portions of these processing flows are shown
graphically in Figure 5 and Figure 6, respectively.
Figure 5 LTE Layer 2 Synchronous Processing Flows Implemented
Trigger
SW
Data transfer

SRS DDR3A
Write
DDR3A
Trigger Everysubframe
CurrentSubframe
boundary+200us Executed per UL transport block per user
ToLayer2
ULPDCP
TriggerperTransport
FromCRCcheck blocksperuser
ULLayer1
UL RLC/MAC
DDR3A
DDR3A
Waiting for all UL transport blocks DDR3A
DDR3A
DDR3A
DDR3A UL HARQ+Scheduler DDR3A
DDR3A Executed per DL IP frame per user

ToDLLayer1
PDCCHMapping
BCPtask
DL RLC/MAC
DDR3A
DL HARQ+Scheduler
DDR3A DDR3A DDR3A
DDR3A
DDR3A DDR3A
Trigger Everysubframe
PreviousSubframe
boundary+800us

FromLayer2
DLPDCP

Page 4 of 10 Using K2L Devices for Dual Mode (LTE + WCDMA) Applications Application Report SPRABW6June 2014
Submit Documentation Feedback
www.ti.com

Figure 6 LTE Layer 2 Asynchronous Processing Flows Implemented

IP frames:
-95%: 500 bytes/frame (A) & (D)
SW -5%: 40 bytes/frame (B)
Rate: as in L2 sync scenario + (C)

Trigger Flow (C) Triggerevery

Data transfer DDR 3A 250 us
Normal UL Flow
+Control UL Flow
+ source DL HO
= (A) + (C) Flow (A) FromULLayer2
NetCP DDR 3A RLC/MAC

DDR 3A
Incl. Air
De-ciphering Target UL HO (from UE, wait Flow (D)
for LP from X2) HO
DDR 3A
SW mostly manipulates (re order)
descriptors in Queues
20% of (A)
Flow (B)

RoHC
DDR 3A DDR 3A

SW reads some payload

say the 40 bytes, writes
back compressed header,
Processing : 3us/packet
Normal DL Flow
+Control DL Flow
+ source DL HO
+ target DL HO X2 link
= 60% of (A) + (C)
DDR 3A
60% of Flow (A)

IP frames:
-95%: 500 bytes/frame (A)
-5%: 40 bytes/frame (B ) Flow (C) DDR 3A

Rate:
as in L2 sync scenario Target DL HO (S1 flow)
HO
+ 20% for DL HO from X2 link (C)
DDR 3A + re stof DDR 3A
Ne tCP
NetCP
DDR 3A
ToDLLayer2
Incl. Air
IP-fragmented Flow RLC/MAC
Ciphering 20% of (A)
DDR 3A

SW reads some payload,

writes back uncompressed
header, say 40 bytes
Processing : 3us/packet
Flow (B)
RoHC DDR 3A
DDR 3A

The LTE Layer 3 traffic generation model was run on ARM core 0. The amount of
Layer 3 traffic to be generated was estimated based on traffic measurements from an
EEMBC Networking benchmark (TCP jumbo) which had previously been run on the
ARM core.

WCDMA Processing
WCDMA processing for Layer 1 was run on DSP cores 2 and 3. The non-HSPA+
uplink and downlink processing flows that were implemented are shown in Figure 7.
The HSPA+ processing flows are shown in Figure 8. Since most of the WCDMA
processing is performed by hardware acceleration, all of the Layer 1 software tasks were
implemented using functional software in this case (instead of latency models).

WCDMA Layer 2 processing was not implemented due to the minimal expected
impact to the scenario (particularly relative to the LTE Layer 2 processing). In a full
system with complete software, the WCDMA Layer 2 processing and transport
processing (Mac-e/Mac-hs schedulers and Frame Protocol) may be executed on DSP
(C66x) or ARM (A15). Running them on the DSP would be expected to have some
slight impact on the latencies presented in the results section. The NetCP can terminate
both Frame Protocol (FP) and NodeB Application protocols (NBAP).

SPRABW6June 2014 Using K2L Devices for Dual Mode (LTE + WCDMA) Applications Application Report Page 5 of 10
Submit Documentation Feedback
 www.ti.com

Figure 7 WCDMA (Non-HSPA+) Processing Flows Implemented

C1 - DPCCH FD, ChEst

RAC Core #2 / #3 Core #2

Antenna T1.2 T1.4 T1.6
T1.1 MEM
Interface T1.3 T1.5 T1.7
DPCCH FD DPCCH ChEst DPDCH MRC

C2 - DPCCH MRC, TFCI Decode, FBI, TPC

Core #2 / #3 Core #2
RAC
Antenna T1.2 T1.8 DPCCH MRC, T1.10 DPDCH Final
T1.1 MEM
Interface T1.3 T1.9 TPC, FBI, T1.11 Despreading &
DPCCH FD
TFCI Decode Decoding

T1.12
T1.13 TAC
Antenna
T1.39
T1.14 Interface
TPC Transmission
T1.15

Queue
Manager
FBI
Transmission
MEM

C3 - DPCCH PM, P-PDP

RAC
RAC Core #2 / #3
Antenna T1.18 T1.20
T1.1 T1.17 MEM
Interface T1.19 T1.21 DPCCH FD &
DPCCH PM P-PDP
DPCCH FD

C4 - DPCCH FT, EOL

RAC
RAC Core #2 / #3
Antenna T1.23 T1.25
T1.1 T1.22 MEM
Interface T1.24 T1.26 DPCCH FD &
DPCCH FT EOL
DPCCH FD

C5 - DPDCH FD, MRC, Final Despreading, Decoding

Core #2 Queue
RAC Core #2 VCP2 Core #2
Antenna DPDCH Final Manager
T1.1 T1.27 MEM T1.28 T1.29 MEM T1.30 T1.31 T1.32 T1.33
Interface Despreading & FPT
DPDCH FD DPDCH MRC DPDCH Decoding DPDCH Decoding
Decoding MEM

C6 - DPDCH Encode, Tx

Queue
Core #2 TAC
Manager Antenna
T1.36 T1.37 MEM T1.38 T1.39
Interface
DPDCH Encode DPDCH Tx
MEM

C7 - RACH S-PDP

Queue Queue
Core #3
Antenna Manager Manager
T1.40 T1.41 T1.42
Interface
RSA PD & S-PDP
MEM MEM

Page 6 of 10 Using K2L Devices for Dual Mode (LTE + WCDMA) Applications Application Report SPRABW6June 2014
Submit Documentation Feedback
www.ti.com

Figure 8 HSPA+ Processing Flows Implemented

Priority 1
DPCCH Channel
To Layer 2
Estimation
Periodicity 1 slot 1 1 Subframe
Happy bit
To Mac-e
E-DPCCH MRC RSN
Core2 Tasks
2 E-TFCI
Core3 Tasks 1 slot
RAC
Accelerators AIF2 PM / Memory HARQ_ACK
FT / FD
HS-DPCCH MRC CQI To Mac-HS
3 PCI
1 slot
Polling 1 Subframe
SF
FBI
Rx DPCCH MRC
TPC
HSPA+ 4
1 slot 1 slot
Users

E-DPDCH Final Post-

TCP3d

Buf
E-DPDCH MRC Despreading TCP3d To FTP

fer
Decoding
+ Pre-TCP3d Tasks Tasks
5
1 slot 1 TTI

DPCCH P-PDP
6
First at slot then every Frame

DPCCH EOL
7
1 Frame

1 TTI
HS-DSCH
HS-DSCH
BCP Post-TCP3e
Pre-TCP3e Tasks
Tasks
1
Tx 1 Subframe
TAC
From FPT HS-SCCH Encode Memory Modulation & AIF2
HSPA+ Spreading
Users 2 1 slot
1 TTI
FDPCH

Results
This section describes the results that were measured when running the implemented
dual mode test scenario on a K2L device. The maximum and minimum measured LTE
processing flow latencies are shown in Table 1-3.
Table 1-3 LTE Measured Processing Flow Latencies
LTE Processing Flow Min Latency (ms) Max Latency (ms)
Layer 1 Downlink 0.29 0.54
Layer 1 Uplink 0.75 0.88
Layer 1 PRACH 0.82 1.03
Layer 2 Downlink RLC/MAC + Ciphering 0.22 0.30
Layer 2 Uplink RLC/MAC + Ciphering 0.22 0.30
Layer 3 Traffic Generation 0.36 0.57
End of Table 1-3

The Layer 1 latencies listed above were defined as follows.

The Layer 1 Downlink/PDSCH processing latency is defined as the processing
time from the moment the first bit is received from the network to the end of the
first processed IFFT.

SPRABW6June 2014 Using K2L Devices for Dual Mode (LTE + WCDMA) Applications Application Report Page 7 of 10
Submit Documentation Feedback
 www.ti.com

The Layer 1 Uplink/PUSCH processing latency is defined as the processing time

from the moment the last SC-FDMA symbol is received to the last CRC checked
transport block is computed.
The Layer 1 PRACH processing latency is defined as the processing time from the
moment the last SC-FDMA symbol is received to the last signature detected.

The maximum and minimum measured HSPA+ processing flow latencies are shown
in Table 1-4 (all non-HSPA+ WCDMA tasks easily met their individual latency
constraints to stay real-time).
Table 1-4 HSPA+ Measured Processing Flow Latencies
HSPA+ Processing Flow Min Latency (ms) Max Latency (ms)
Layer 1 Downlink (Data arrival to BCP 0.016 0.022
encoding done)
Layer 1 Uplink (RAC E-DPDCH to last 1.42 1.98
code block decoded)
End of Table 1-4

Software Solutions and Support

The system validation as described above is crucial to validate system assumptions
prior to realizing a full software solution. In parallel to this effort, TI has heavily
invested in developing foundational software as well as an ecosystem with partners to
provide complete solutions for Small Cell base stations.
Figure 9 TI Small Cell Hardware/Software Ecosystem

For easy integration with their own software packages, customers can rely on TI
platform software and the TI Multicore Software Development Kit (MCSDK). These
tools enable customers to quickly benefit from KeyStone II features such as - but not
limited to - the digital radio front end (included in IQN), the Multicore Navigator

Page 8 of 10 Using K2L Devices for Dual Mode (LTE + WCDMA) Applications Application Report SPRABW6June 2014
Submit Documentation Feedback
www.ti.com

(including a HW queue manager and PacketDMA mechanisms), and radio

accelerators. Software packages like the Resource Manager (RM) and the Open Event
Manager (OpenEM) facilitate true multicore development, rather than viewing the
platform as a concatenation of multiple single cores. The RM enables efficient resource
sharing across cores, which is key to a successful dual-mode implementation.

TI's focus on enabling foundational SW has already proven its benefits, as TI's partner
applications currently collaborate on top of MCSDK in K2L HW platforms. More
details can be found on the TI website:
http://www.ti.com/ww/en/smallcells/software.html#ecosystem

SPRABW6June 2014 Using K2L Devices for Dual Mode (LTE + WCDMA) Applications Application Report Page 9 of 10
Submit Documentation Feedback
 IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright 2014, Texas Instruments Incorporated