International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
192
LOW POWER AUTO GATED FLIP-FLOP DESIGN USING CLOCK
GATING TECHNIQUE
Ms. Aparna B
Dept. of Electronics and communication
Nehru Institute of Technology
Coimbatore, Tamilnadu.
Abstract
The clock gating can enable the clock signals from the
CDN (clock distribution network). This technique could
be activating the clock which is needed for the operation
of the circuit. The unnecessary clock signals are not
activated during the clock gating. This saves the
dynamic power of the circuit. The auto gated flip-flops
which are to be using clock gating technique for only
small power consumption. The novel approach we are
going to design the circuit based on look ahead clock
gating which is to be used for the timing constraints for
each clock pulses. The enabling clock pulses for the
derived timing signals to the gated logic which is to be
saves the power from the flip-flops. The look ahead
technique can also to be reducing the delay and the
distortions from the circuit for the achievement of the
application level. This could be applied into the parallel
bus specific clock gating for application level
implementation. This can be adopted for the all sectional
view from particular architecture implementation. This
process could be available for the structural level
implementation for all the CMOS logic gates for the
integrated chip. This architecture can be designed and
verified by using TANNER EDA tool.
Key points: - Clock Gating, Auto Gated Flip-Flop,
Parallel Bus specific clock gating
I. INTRODUCTION
The clock signals are to be enabled at the process of
system level [2] and it can be effectively capture the
functional block modules. This could be need not be
clocked. These signals are activated later into the clock
enabling signals [2] in the form of gate level. In the other
[5] devices the clock signals are automatically added by
the design consideration. Still the circuit having some
floating at the high level. For this situation we need to
[8] calculate the dynamic power consumption consumed
by a circuit when the clock signals are enabled. This
period is assessing the clock gating requires the [11]
analysis and the requirements of FFs Pre-charge and
evaluation state as presented.
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Volume 4, Issue 3, March 2015
Mr. Arul Kumar M
Dept. of Electronics and communication.
Nehru Institute of Technology
Coimbatore, Tamilnadu.
The clock will be disabled in the next cycle by
XOR-ing the output [9] of the present data input and it
will reveal at the output in the next cycle. Then the
output of the XOR gates are OR-ed for generating the
gate signal for the FFs [10] which is to be used to avoid
the glitches. The Integrated clock gate (ICG) can be used
by the environmental tools by the combination of
LATCH with the AND gate [13]. These latches could be
used in ultra low power applications for a digital filter.
The data driven clock gating signal are being used as an
enabling signals [12] in this applications. There will be a
trade off for ICG is the number of clock pulses could be
disabled. The pulses could also be a tradeoff [5] for the
hardware overhead. While increase the number of flip-
flops the hardware overhead decreases to obtain by OR-
ing the enable signals. The level of this high and the low
state of signals could be processed in the same versa to
give the proper output.
The clock gating signals are not enable as free. The
logics and the interconnections are could be desired [7]
to enable those signals and the output can be covered by
area and the power consideration. In some operation
individual clock input [4] has been given to the FFs and
it consumes more amount of power. These clock
separations have been yielding more size also. This
could be results in high overhead [8] of the output. Thus
the clock load has been reduced by using the circuits
shared by Flip-Flops. This could be consumed small
amount of power.
The registers attached to use the clocks and the
enable condition used by clock gating. To achieve the
clock gating from the enable conditions [2] in order to
use the imperative design. This process also saves the
power as well as large number of MUXs in the logic
circuit [11]. These circuits are could be replaced by
using the Clock gating signals [5] from the CDN. The
general form of the ICG can also to be distributing these
signals to the clocks for the level of interchanging [6] as
a part of the CDN. Since the level of the clock gating
 International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
logic change the clock tree structure and it will be
remain at the same tree.
Clock gating logic levels having the strategy are as
follows:
1) The RTL level code has to enable the condition
which could be accessed the logic level
synthesis.
2) The design could be specific modules or a
registers that can be processed by ICG as a
library function.
3) The automated clock gating has been semi-
automatically inserted and it will be generated as
an ICG cells. So this will be enable the RTL
level or it will be insert into the ICG level for the
optimizations.
II. EXISTING SYSTEM DATA
DRIVEN CLOCK GATING
Data driven gating is causing area and power
overheads that must be considered. In an attempt to
reduce the overhead, it is proposed to group several FFs
to be driven by the same clock signal, generated by bring
the enabling signals of the individual FFs. This may
however, lower the disabling effectiveness. It is
therefore beneficial to group FFs whose switching
activities are highly correlated and derive a joint
enabling signal. In a recent paper, a model for data-
driven gating is developed based on the toggling activity
of the constituent FFs. The optimal fan-out of a clock
gate yielding maximal power savings is derived based on
the average toggling statistics of the individual FFs,
process technology, and cell library in use. In general,
the state transitions of FFs in digital systems depend on
the data they process. Assessing the effectiveness of
data-driven clock gating requires, therefore, extensive
simulations and statistical analysis of the FFs activity.
Fig 1: Data driven clock gating
The dynamic power consumption could be reduced
by using clock gating technique. This data driven clock
gating signals having toggling activity to enable the
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Volume 4, Issue 3, March 2015
clock signals. So the flip-flops and the latches are to be
enabled by using the gate signals. The outputs from the
X-OR gates are OR ed to give the combination of output
joint gate signals from the flip-flops and then latched to
avoid the glitches presented in the specified units.
III. PROPOSED SYSTEM AUTO
GATED FLIP-FLOP
Flip-flops have their content modification solely
either at the rising or falling fringe of the modify signal.
But, once the rising or falling fringe of the modify
signal, the flip-flops content remains constant even
though the input modification. in a very typical D Flip
Flop, the clock signal perpetually flows into the D flip-
flop no matter whether or not the input changes or not. A
part of the clock energy is consumed by the interior
clock buffer to manage the transmission gates
unnecessarily. Hence, if the input of the flip-flop is the
image of its output, the shift of the clock will be
suppressed to conserve power.
The auto gated flip-flop design has been
illustrated in Fig 2. This block consists of master and the
slave combination of flip-flops and the latch. The FFs
falling edge of the clock pulse could be gives the time
prior of the input signal. The XOR gates are to be
highlighting the state of the slave latch when it could be
enabled. The sectional view of this latch and the flip-flop
can be having the timing constraints when compared to
the data driven clock gating. The level of the clock
signal enables the pulses from the triggering edges of the
input. The gating can be detected to be critical in the
master slave flip-flop enabling.
Fig 2: Block diagram of auto gated flip-flop
LOOK AHEAD CLOCK GATING:
Look-ahead path and pipelining to eliminate the
carry chain delay and reduce AND gate fan-in and fan-
out. The look-ahead clock gating block consists of
enhanced auto gated symbol for master and the slave
 International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
blocks. This could be used as a look-ahead structure for
reducing the timing constraints of the each block.
Fig 3: Block diagram of the look ahead clock gating
The enhanced auto gated flip-flops could be
having the related use of the sectional circuits from the
each and every input. The output from the flip-flop as Q
and X could be input of the logic block and the
continuous input to another block. The XOR and the OR
gated logic could be used as a leap forward approach for
the input signal. The clock and the gated clock also
given to the logic and then it will be adopted as a signal
from the each block of the architecture. The rising and
the falling edge of the clock pulse enables the clock load
from the switching.
The output from the flip-flop k could be given to
the logic as well as the gated signal as (1-(1-p) ^k for the
output of the next level logic. The gated signal clock
pulses also to be the path recognize of the master slave
of the enhanced auto gated logic. This logic has been
given to the next level of the flip-flop for automatic
process (1-(1-p) ^k of the gate as general signals from
the input. Then the output of the flip-flop could be given
to the clock gated signal and the clock enabling signals
to give the final output. This gives the timing constrains
path of the look ahead clock signal from the inputs.
The look ahead clock gating overcomes the
drawbacks of the auto gated flip-flops in the tight timing
constrains from the clock pulses which is not enabled in
the gated signal. The structural details from the signals
where it could be not recognize in the rising and the
falling edges of the clock pulses. During the
computation path the setup time and the holding timing
can also to enable in the path of all the input pulses from
the master slave blocks.
IV. IMPLEMENTATION OF THE
AUTO GATED FLIP-FLOP
The auto gated flip flops could be implemented
as an application of parallel bus specific Clock gating
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(PBSC). This could be efficient of power saving from
the circuits used in the flip-flops for measuring the
outputs. An activity-driven parallel bus specific CG
(PBSC afterward) is employed to maximize dynamic
power reduction at RT level before synthesis. It chooses
solely a set of flip-flops (FF) to be gated by selection,
and therefore the downside of gated FF choice is reduced
from exponential quality into linear. When the OBSC is
applied to the look, the parts activity redundant
operations throughout the clock gated amount square
measure determined by forward traversing the circuit
from the gated FF outputs. These parts are going to be
power gated mistreatment the clock modify signal
generated by OBSC as long as the implementation of
RTPG will cut back active discharge power. The
practicableness analysis of RTPG is predicated on our
planned minimum average idle time construct.
BSC circuit compares the inputs and outputs,
and gates the clock after they square measure equal.
BSC are often used as a final CG choice to cut back
dynamic power once no CG is often applied throughout
synthesis. However, BSC is way from best in terms of
dynamic power minimization, and therefore the partial
BSC (PBSC afterward) circuit.
To reduce the high power consumption
in the related low power structure design for high
performance has been presented here. The level of the
each data given to the bit level of the flip-flop as auto
gated flip-flop can be adopted form the input bit wise
operation. The signal from the structural view can be
delivered the sequence of the each input as a clock level
output signal. And also the carry look-ahead used a pre
scalar technique with systolic 4-bit counter modules with
the cost of an extra detector circuit. The detector circuit
detected the assertion of lower order bits to enable
counting in the higher order bits.
Fig 4: Block of parallel Bus specific clock gating
 International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
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Volume 4, Issue 3, March 2015

The main structure consists of the look-ahead with the existing and the proposed circuits. The delay
path and the counting path. The Bus is partitioned into could also to be detected from the each circuit and it also
uniform 4-bit synchronous up counting modules. The to be compared with the conventional circuits as much
counting paths counting logic controls counting as 70-90%. The nano meter technology could be adopted
operations and the look-ahead logic anticipates future as a 90nm process to detect the chip integration level
states and thus prepares the parallel datas for these from the analysis.
future states. In the counting path, each module serves
two main purposes. The first purpose is to generate all
bits associated with their ordered position and the second
purpose is to enable the future states of the look-ahead
path.

Fig 6: Schematic of the auto gated flip-flop

Fig 5: Waveform of parallel Bus specific clock gating

Parallel Bus specific clock gating architecture

enables high flexibility and reusability, and thus enables
short design time for wide counter applications. The
architecture is composed of four basic module types
separated by auto gated FFs in a pipelined organization.
These four modules type are placed in a highly
repetitious structure in both the counting path and the
look-ahead paths.

V. SIMULATION RESULTS
The proposed auto gated and the look-ahead design
has been simulated and verified by using the TANNER Fig 7: Schematic of the enhanced auto gated flip-flop
EDA tools. By the level of this consideration we could
find out the output as the power consumption of the The implementation of the parallel bus specific
proposed circuit. This design could be analyzed as the could be adequate from the look-ahead design and then it
implementation in the proposed design. could be compared with the conventional DFF based
counter design. Therefore the proposed design is very
A Transient analysis is carried out assuming well suited for low power and high performance
typical parameters, with power, supply voltage in volts, applications.
transient analysis from 0-1000ns,the clock period ,the
data period and taking the delay time.

The total power dissipation has been improves

as much from the circuit that can be adopted to compare

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 International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Fig 8: Schematic of Look ahead clock gating
VI. CONCLUSION
In this paper we have proposed the auto gated flip
flop design with the implementation of parallel bus
specific applications. The circuit has been designed and
verified by using the T-SPICE compiler. The
computation could be enabled as a power and the delay
timing constrains of the each clock pulses. The target
matching could be pursued from the digital process of
the each clock cycling for the auto gated flip-flops. This
could be considered and followed by this proposed
design to implement this survey and the evaluation of
the circuits. The performance of the proposed design
could not be limited as much in the conventional
circuits.
ACKNOWLEDGEMENT
I wish to acknowledge the efforts of my Project
Guide Mr. Arul Kumar M and the head of the
department Dr.R.Deepa for their guidance which helped
me work hard towards producing this research work.
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