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TM

HIP0061
60V, 3.5A, 3-Transistor Common Source
December 1997 ESD Protected Power MOSFET Array

Features Description
Three 3.5A Power MOS N-Channel Transistors The HIP0061 is a power MOSFET array that consists of
three matched N-Channel enhancement mode MOS transis-
Output Voltage to 60V
tors connected in a common source configuration. The
rDS(ON) . . . . . 0.225 Max Per Transistor at VGS = 10V advanced Intersil PASIC2 process technology used in this
product utilizes efficient geometries that provides outstand-
Pulsed Current . . . . . . . . . . . . . . . .10A Each Transistor ing device performance and ruggedness.
Avalanche Energy . . . . . . . . . . 100mJ Each Transistor The HIP0061 is designed to integrate three power devices in
Grounded Tab Eliminates Heat Sink Isolation one chip thus providing board layout area and heat sink sav-
ings for applications such as Motor Controls, Lamps,
Solenoids and Resistive Loads.
Applications
Automotive
Appliance Symbol
Industrial Control
DRAIN1 DRAIN2 DRAIN3
Robotics 2 5 7

Relay, Solenoid, Lamp Drivers


GATE1 GATE2 GATE3
Ordering Information 1 3 6

TEMP. PKG.
PART NUMBER RANGE (oC) PACKAGE NO.
4
HIP0061AS1 -40 to 125 7 Ld Staggered Z7.05C SOURCE, TAB
Vertical SIP

HIP0061AS2 -40 to 125 7 Ld Gullwing SIP Z7.05B

Pinouts
HIP0061AS1 HIP0061AS2
(SIP - VERTICAL) (SIP - GULLWING)
TOP VIEW TOP VIEW

7 DRAIN3 7 DRAIN3
6 GATE3 6 GATE3
5 DRAIN2 5 DRAIN2
4 SOURCE 4 SOURCE
3 GATE2 3 GATE2
2 DRAIN1 2 DRAIN1
1 GATE 1 1 GATE 1

TAB
TAB
TAB (SOURCE) INTERNALLY CONNECTED TO PIN 4 TAB (SOURCE) INTERNALLY CONNECTED TO PIN 4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. FN3982.3
Copyright Intersil Americas Inc. 2002. All Rights Reserved
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HIP0061

Absolute Maximum Ratings TA = 25oC Thermal Information


Drain to Source Voltage, VDS Thermal Resistance (Typical, Note 4) JA (oC/W) JC (oC/W)
(Over Operating Junction and Case Temperature Range). . . . 60V SIP-Vertical Package . . . . . . . . . . . . . 55 3
Drain to Gate Voltage, VDGR . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V SIP-Gullwing Package . . . . . . . . . . . . 55 3
Gate to Source Voltage, VGS . . . . . . . . . . . . . . . . . . . . . . .-15, +20V Maximum Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . 150oC
Pulsed Drain Current, IDM, Each Output, Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC
All Outputs on at VGS = 10V (Notes 1, 2) . . . . . . . . . . . . . . . . 10A Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300oC
Continuous Source to Drain Diode Current, ISD
at VGS = 10V (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5A
Die Characteristics
Continuous Drain Current, IDS, Each Output,
All Outputs on at VGS = 10V (Note 2) . . . . . . . . . . . . . . . . . . 3.5A Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . V- (Source, Tab)
Single Pulse Avalanche Energy, EAS (Note 3). . . . . . . . . . . . 100mJ

Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC
Drain to Source On-State Voltage Range . . . . . . . . . . . . 5V to 10V
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Pulse width limited by maximum junction temperature.
2. Drain current limited by package construction.
3. VDD = 25V, Start TJ = 25oC, L = 15mH, RGS = 50, IPEAK = 3.5A. See Figures 1, 2, 12, and 13.
4. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS ID = 100A, VGS = 0V TC = -40o C to 60 - - V


125oC

TC = 25o C - 70 - V

Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250A 1.8 2.3 2.7 V

Zero Gate Voltage Drain Current IDSS VDS = 60V TC = 25o C - - 1 A


VGS = 0V
TC = 125o C - - 10 A

Forward Gate Current, Drain Short IGSSF VDS = 0V, VGS = 20V - - 100 nA
Circuited to Source

Reverse Gate Current, Drain Short IGSSR VDS = 0V, VGS = -15V - - -100 nA
Circuited to Source

Drain to Source On Resistance (Note 5) rDS(ON) VGS = 10V, ID = 3.5A TC = 25oC - 0.215 0.265

VGS = 10V, ID = 3.5A TC = 125oC - 0.365 0.425

VGS = 5V, ID = 2A TC = 25oC - 0.275 0.320

VGS = 5V, ID = 2A TC = 125oC - 0.465 0.5

Drain to Source On Resistance Matching rDS(ON) VGS = 10V, ID = 3.5A TC = 25oC - 95 - %

Forward Transconductance (Note 5) gfs VDS = 10V, ID = 1A - 2.5 - S

Turn-On Delay Time (Note 6) td(ON) VDD = 30V, RL = 15, - 10 - ns


VGS = +10V, ID = 2A, RG = 50
Rise Time (Note 6) tr See Figure 14 - 25 - ns

Turn-Off Delay Time (Note 6) td(OFF) - 18 - ns

Fall Time (Note 6) tf - 12 - ns

Total Gate Charge (Note 6) Qg(TOT) VDS = 50V, VGS = 10V, ID = 2A - 8.0 9.5 nC
See Figures 16, 17
Gate-Source Charge (Note 6) Qgs - 0.7 1.0 nC

Gate-Drain Charge (Note 6) Qgd - 3.5 4.0 nC

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HIP0061

Electrical Specifications TC = 25oC, Unless Otherwise Specified (Continued)

PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Short-Circuit Input Capacitance, CISS VDS = 25V, VGS = 0V - 142 - pF


Common Source f = 1MHz

Short-Circuit Output Capacitance, COSS - 107 - pF


Common Source

Short-Circuit Reverse Transfer CRSS - 24 - pF


Capacitance, Common Source

Source-Drain Diode Ratings and Specifications


PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Diode Forward Voltage (Note 5) VSD ISD = 2A, VGS = 0V - 0.9 1.1 V
Reverse Recovery Time trr ISD = 2A, dISD/dt = 100A/s - 50 - ns
NOTES:
5. Pulse test: Pulse width 300s, duty cycle 2%.
6. Independent of operating temperature.

Typical Performance Curves

10
10s 10
ID , DRAIN CURRENT (A)

10s
ID , DRAIN CURRENT (A)

100s
100s
1ms
10ms
100ms 100s
1
OPERATION IN THIS DC 1
1ms
AREA MAY BE OPERATION IN THIS
10ms
LIMITED BY rDS(ON) AREA MAY BE
100ms
LIMITED BY rDS(ON)
DC
TC = 25oC
TC = 105oC
TJ = MAX RATED
0.1 TJ = MAX RATED
1 10 100 0.1
1 10 100
VDS , DRAIN VOLTAGE (V)
VDS , DRAIN TO SOURCE VOLTAGE (V)

FIGURE 1A. 25oC SAFE-OPERATING AREA CURVE FIGURE 1B. 105oC SAFE-OPERATING AREA CURVE

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HIP0061

Typical Performance Curves (Continued)

50

10

IAS, AVALANCHE CURRENT (A)


STARTING TJ = 25oC
ID , DRAIN CURRENT (A)

10s 10 STARTING TJ = 125oC

1
5
OPERATION IN THIS 100s
AREA MAY BE
1ms
LIMITED BY rDS(ON) 10ms
100ms
TC = 125oC DC
TJ = MAX RATED
0.1 1
1 10 100 0.001 0.01 0.1 1.0
VDS , DRAIN TO SOURCE VOLTAGE (V) tAV , TIME IN AVALANCHE (ms)

FIGURE 1C. 125oC SAFE-OPERATING AREA CURVE FIGURE 2. UNCLAMPED INDUCTIVE-SWITCHING

10.0 20
VGS = 10V
VDS = 15V 25oC
VGS = 8V -40oC
VGS = 6V VGS = 5V
125oC
ID, DRAIN CURRENT (A)

7.5 15
ID, DRAIN CURRENT (A)

5.0 10
VGS = 4V

2.5 5

PULSE DURATION = 300s, TC = 25oC


0 0
0 2 4 6 8 10 0 2 4 6 8 10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 3. TYPICAL SATURATION CHARACTERISTICS FIGURE 4. TYPICAL TRANSFER CHARACTERISTICS

2.5 1.2
rDS(ON), NORMALIZED ON RESISTANCE

PULSE DURATION = 300s, VGS = 10V, ID = 3.5A ID = 100A

2.0
1.1
NORMALIZED BVDSS

1.5

1.0
1.0

0.9
0.5

0 0.8
-75 -25 25 75 125 175
-75 -25 25 75 125 175
TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC)

FIGURE 5. NORMALIZED rDS(ON) vs JUNCTION TEMPERA- FIGURE 6. NORMALIZED BVDSS vs JUNCTION TEMPERATURE
TURE

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HIP0061

Typical Performance Curves (Continued)

2.0 12
VGS = VDS, ID = 250A
VDS = 50V

VGS, GATE-SOURCE VOLTAGE (V)


VDS = 30V
1.5
VGS(TH), NORMALIZED

VDS = 20V
8

1.0

4
0.5

ID = 2.0A, TC = 25oC
0 0
-75 -25 25 75 125 175 0 2 4 6 8 10
TJ, JUNCTION TEMPERATURE (oC) Q, GATE CHARGE (nC)

FIGURE 7. NORMALIZED VGS(TH) vs JUNCTION TEMPERA- FIGURE 8. GATE-SOURCE VOLTAGE vs GATE CHARGE
TURE

750 5
VGS = 0V, f = 1MHz, TC = 25oC

600 4
C, CAPACITANCE (pF)

ID , DRAIN CURRENT (A)

450 3
VGS = 10V
VGS = 5V
CISS
300 2
COSS
CRSS

150 1

0 0
0 5 10 15 20 25 25 50 75 100 125 150
VDS, DRAIN TO SOURCE VOLTAGE (V) TC, CASE TEMPERATURE (oC)

FIGURE 9. TYPICAL CAPACITANCE vs VOLTAGE FIGURE 10. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE

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HIP0061

Typical Performance Curves (Continued)

10
ZJC, NORMALIZED THERMAL IMPEDANCE

TC = 25oC

1 D = 1.0
0.5
0.2

0.1
0.1 0.05
0.02
0.01 NOTES:
1. DUTY FACTOR, D = t1/t2
SINGLE PULSE 2. PEAK TJ = PDM x (ZJC) +TC

10-6 10-5 10-4 10-3 10-2 10-1


t, RECTANGULAR PULSE DURATION (s)

FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

Test Circuits and Waveforms

tP tAV
10 V
VDS

VGS 0
L IAS

RG +
DUT
VDD
VGS -
ID 0
BVDSS
tP
0V ID VDS
0.01
0

FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS

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HIP0061

Test Circuits and Waveforms

VDD tON tOFF

td(ON) td(OFF)

RL tr tf
VDS
90% 90%
VDS
VGS

DUT 10% 10%

0V
90%
RGS

50% 50%
VGS
PULSE WIDTH
10%

FIGURE 14. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 15. RESISTIVE SWITCHING WAVEFORMS

+VDS
CURRENT Qg
REGULATOR SAME TYPE
10V
AS DUT
+ 0.2F 25k
10V
BATTERY
-
0.1F
Qgs Qgd

VG
DUT

IGS
0

CHARGE

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. BASIC GATE CHARGE WAVEFORM

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PSPICE Model Listing
Device Model Netlist for the HIP0061 Power MOSFET Array

*Rev: 6/12/95 KP=3.150e-03 PHI=0.65 GAMMA=2.55


.SUBCKT HIP0061 1 2 3 4 5 6 7 + VMAX=6.42e+07 NSUB=4.33e+16 THETA=0.60973
X1 8 1 11 4 HIP0061_1 ETA=0.0015 KAPPA=1.275
LS1 2 8 7.5n + L=1u W=3050u)
X2 9 3 11 4 HIP0061_1 .MODEL J1 NJF (VTO=-15.0 BETA=10.736
LS2 5 9 7.5n LAMBDA=1.15e-02 PB=0.5848 IS=+1.0e-13
X3 10 6 11 4 HIP0061_1 + RD=3.53e-02 ALPHA=0.2)
LS3 7 10 7.5n .MODEL D1 D (IS=1.0e-15 N=0.03 RS=1.0)
LS4 4 11 7.5n .MODEL D2 D (IS=3.0e-13 RS=2.5e-03 TT=20N
.ENDS CJO=350e-12)
.MODEL D3 D (IS=1.0e-13 N=1.0 RS=2.0)
.SUBCKT HIP0061_1 3 2 11 9 .MODEL D4 D (IS=1.0e-13 RS=2.0e-03 CJO=80e-12)
MOS1 4 2 1 1 NMOS1 .MODEL D5 D (IS=1.0e-15 RS=1.0e-03 CJO=2.5e-12)
JFET 13 1 4 J1 .ENDS
D1 5 6 D1
DBODY 1 13 D2
DBREAK 3 7 D3
DSUB 9 13 D4
DESD1 2 12 D5
DESD2 15 12 D5
VBREAK 7 1 DC 90
C21 2 1 750P
C23 2 13 45P
C24 2 4 1100P
RDRAIN 13 14 9.0e-02
LDRAIN 14 3 7.5n
RSOURCE 1 15 17.5e-03
LSOURCE 15 11 7.5n
FDSCHRG 4 2 VMEAS 1.0
E41 5 15 4 1 1.0
VPINCH 6 8 DC 10.0
VMEAS 8 15 DC 0.0
.MODEL NMOS1 NMOS LEVEL=3 (VTO=2.75 TOX=5e-08

NOTE: For further discussion of the PSPICE PowerFET macromodel consult Spicing-Up SPICE II Software for Power MOSFET Modeling,
Intersil Application Note AN8610.

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HIP0061

Single-In-Line Plastic Packages (SIP)


-A- A 0.006
Z7.05B
7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE SURFACE MOUNT
E -B- (0.15)
GULLWING LEAD FORM
C2
L2 INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
HEATSLUG A 0.170 0.180 4.32 4.57 -
D PLANE
-C- C2 0.048 0.055 1.22 1.39 5
L
0.00 - 0.0098 D 0.350 0.370 8.89 9.39 -
(0.00 - 0.25)
L1
E 0.395 0.405 10.04 10.28 -
PIN D1 0.310 - 7.88 - -
#1
c E1 0.310 - 7.88 - -
e 0o- 8o
L 0.549 0.569 13.95 14.45 -
b
L1 0.068 0.088 1.72 2.24 -
0.004
0.010 (0.25) M B A M C M (0.10)
L3 L2 0.045 0.055 1.15 1.40 -
L3 0.030 BSC 0.76 BSC 4
0.450 b 0.028 0.034 0.71 0.86 5, 6, 7
E1 (11.43) MIN
c 0.018 0.024 0.46 0.60 5
e 0.050 BSC 1.27 BSC -
D1 0.350 Rev. 2 12/95
(8.89)
MIN NOTES:
0.609
1. These package dimensions are within allowable dimensions of
(15.46)
MIN JEDEC MO-169AC, Issue A.
2. Controlling dimension: Inch.
BACK VIEW
3. Dimensioning and tolerance per ANSI Y14.5M-1982.
0.129
(3.27) 4. Gauge plane L3 is parallel to heatslug plane.
TYP
5. Dimensions include lead finish.
0.030
(0.76)
e 6. Leads are not allowed above the datum -B- .
TYP 7. Dimension b does not include dambar protrusion. Allowable
LAND PATTERN
dambar protrusion shall not cause the lead width to exceed the
maximum b by more than 0.003 (0.08mm).

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HIP0061

Single-In-Line Plastic Packages (SIP)


Z7.05C
0.006 (0.15)
7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE
STAGGERED VERTICAL LEAD FORM
A
INCHES MILLIMETERS
D
SYMBOL MIN MAX MIN MAX NOTES
-B-
P A 0.170 0.180 4.32 4.57 -
D1 F
B 0.028 0.034 0.71 0.86 3, 4
E2
C 0.018 0.024 0.46 0.60 3
D 0.395 0.405 10.04 10.28 -
E HEADER D1 0.198 0.202 5.03 5.13 -
BOTTOM
E1 L1 E 0.595 0.605 15.11 15.37 -
E1 0.350 0.370 8.89 9.39 -
E2 0.110 BSC 2.79 BSC
e 0.050 BSC 1.27 BSC -
L
-A- e1 0.200 BSC 5.08 BSC -
e
B
e2 0.169 BSC 4.29 BSC -
e3 e1 e2 e3 0.300 BSC 7.62 BSC -
C F 0.048 0.055 1.22 1.39 3
7 PLACES
ALL LEADS L 0.150 0.176 3.81 4.47 -
0.010 (0.25) M A B M
0.024 (0.61) M A L1 0.600 0.620 15.24 15.74 -
P 0.147 0.152 3.73 3.86 3
Rev. 0 6/95
NOTES:
1. Controlling dimension: INCH.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimensions include lead finish.
4. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall not cause lead width to exceed maxi-
mum B by more than 0.003 inches (0.08mm).

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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