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DIGITAL TECHNIQUES
Licence By Post
You should also follow the requirements of your national regulatory authority
(the CM in the UK) and laid down company policy as regards local
procedures, recording, report writing, documentation etc.
For health and safety in the workplace you should follow the
regulations/guidelines as specified by the equipment manufacturer, your
company, national safety authorities and national governments.
AUTHORITY
You should also follow the requirements of your national regulatory authority
(the CAA in the UK) and laid down company policy as regards local
procedures, recording, report writing, documentation etc.
For health and safety in the workplace you should follow the
regulations/ guidelines as specified by the equipment manufacturer, your
company, national safety authorities and national governments.
NOTE
LBP
140 Narbeth Drive
Aylesbury
Bucks
,-., HP20 1QA UK
PAGE
Numbering systems
Decimal 1
Binary 2
Octal 8
Hexadecimal 11
Binary coded decimal 14
Digital circuits
-r-.
,
Logic gates 18
Electronic gates 25
De Morganis rules 34
Take-off warning 36
Landing gear lever disagree 37
Sequential/ combinational logic 38
Flip-flops
SR 39
Clocks 40
D type SR 41
JK 42
Counters 43
Shift register 44
Encoders/ decoders
Encoders 46
Analogue to digital converter 47
;
r Decoders 49
~ Digital to analogue converter 50
R-2R type D to A converter 51
Multiplexers 52
Demultiplexers 55
Passenger entertainment system 57
Assignments 58
Solutions to activities 59
r
Basically, very slowly! Make sure you understand each part before going
onto the next. It is important you can recognise logic gates, be able to draw
relevant truth tables and be able to interpret aircraft schematic diagrams in
relation to logic circuits.
This book is written mainly for the B 1 and B2 technician with the A line
mechanic needing to study only a small section and all to level 1 standard.
The B2 technician needs to study this book in its entirety with all subjects to
level 2 and Electronic Instrument Systems to level 3.
The B 1 technician needs to study most of the book with most subjects at
level 2 - check JAR66.
All students should refer to JAR66 for the subjects to be studied and the
level of knowledge required.
~-
NUMBERING SYSTEMS
Decimal System
= 72306
= 10 + 9 + 5 + 02 + 006
= 19526
3 was used because it is an easy number to show you that any number to
the power of nought is equal to 1.
It can be seen that the decimal system is based on successive powers of 10,
the number with the smallest value (10) is known as the least significant
digit (LSD) and the number with the highest value (104 in my example) is
known as the most significant digit (MSD).
- 1-
The disadvantage of the decimal system for use in a digital computer is that
the circuits which would be used, eg transistors, would have to have 10 ,'-"
discrete levels at collector current. For example OmA (milliamps) = 0,
lmA = 1, 2mA = 2, 3mA = 3 etc. Such a system would be extremely difficult
to operate because:
Any errors from the above may cause an error increment of one or two,
giving an incorrect output (eg instead of 8 [correct reading] it might be
7 or 9).
Where accuracy and speed are important it would be better to use a system
which has just two states. Reliance is high because the circuit is either
HIGH (voltage level) or LOW (voltage level) or ON and OFF and component
characteristics variations are unimportant.
The system that is the basis of today's digital processing is the "two states"
BINARY SYSTEM.
For example:
27 24 + 23 + 21 + 20
= 16 + 8 + 2 + 1
further expanded
= 1 x 24 + 1 x 23 0 x 2 2 + 1 x 21 = 1 x 2
1 1 0 1 1
-2 -
r To avoid confusion between systems with different radix this would be
written as 1101 b to identify it as a binary number.
12= 2- 1 = _l_ = 05
2
"
I
I
Example
17 = 2 4 + 20 + 2-1 + 2-2
expanded gives
1 x 24 + 0 x 23 + 0 x 22 + 0 x 21 + 1 x 20 + 1 x 2-1 + 1 x 2-2
r .;i
1 0 0 0 1 1 1
~~'!'!:'.:'
1775 = 100011 b
The table below shows the relationship between Binary and Decimal
numbers up to Decimal 21, but it could obviously be continued for larger
numbers.
-3 -
Decimal 5-bit Binary No (word) Decimal 5-bit Binary No (word)
Number Number
24 23 22 21 20 24 23 22 21 20
0 0 0 0 0 0 11 0 1 0 1 1
1 0 0 0 0 1 12 0 1 1 0 0
2 0 0 0 1 0 13 0 1 1 0 1
3 0 0 0 1 1 14 0 1 1 1 0
4 0 0 1 0 0 15 0 1 1 1 1
5 0 0 1 0 1 16 1 0 0 0 0
,,
6 0 0 1 1 0 17 1 0 0 0 1 :~
,.J'
7 0 0 1 1 1 18 1 0 0 1 0
8 0 1 0 0 0 19 1 0 0 1 1
9 0 1 0 0 1 20 1 0 1 0 0
10 0 1 0 1 0 21 1 0 1 0 1
From the table it can be seen that the binary number is longer than the
decimal number but because of the very fast switching speeds of modern
circuits this does not present a problem. Also because of the reliability of the
two-state system, the practical advantages gained by using binary numbers
are considerable.
This method is OK but when you get larger numbers it becomes much more
difficult, to convert from decimal to binary, the successive division by two
may be employed, the 'remainder' of any division (which must be either O or
1) is then recorded successively in a separate column. The following
examples show the method used.
- 4 -
Example a Example b
2 796 2 217
2 99 " 1 2 27 " 0
2 49 " 1 2 13 " 1
,,-..,
..
2 24 " 1 2 6 " 1
2 12 " 0 2 3 " 0
2 6 " 0 2 1 " 1
2 3 " 0 2 0 " 1
r
:z-7
::'
CONVERSION OF DECIMAL TO BINARY
(a) 846
(b) 317
(c) 147
You should practice converting the smaller numbers using powers of 2 and
perhaps speed it up a bit.
-5-
Example
(lx32)+(1x8)+(lx4)+(lxl) = 45
So 32 16 8 4 2 1
1 0 1 1 0 1
ACTIVITY: So the idea is to write down the powers of 2 and put 1 's in the
powers you need to make up the number. Try these:
(a) 47
(b) 32
(c) 21
The following example shows you how to convert decimal fractions to binary.
You use successive multiplication by two, recording the carries and then
reading DOWN the carries column.
1 230 x 2
READ DOWN
And write from left to right 0 460 x 2
to give binary fraction:
0 920 x 2
0-10011 b
0 840 x 2
1 680 x 2
- 6 -
Conversion of a decimal fraction to a binary fraction
r
The next example shows how to convert a mixed decimal number to binary.
Note that it must be treated in two parts as shown.
Example
WHOLE FRACTION
2 14 0 625 x 2
,,,.....
i
r 2 7 remainder 0 1 250 x 2
READ
2 3 " 1 UP READ 0 500 x 2
DOWN
2 1 " 1 1 000
0 " 1
The easy way to convert this is to write the powers of 2 above each bit
position starting from left and working towards the right eg:
1 0 1 1 0 1
-7-
Examples:
64 32 16 8 4 2 1
1 1 01101
So 64 + 32 + 8 + 4 + 1 = 10910
1 1 0 1 1
13 510
64 32 16 8 4 2 1 .5 25
1 0 0 1 1 1 0 1 1
= 64 + 8 + 4 + 2 + 5 + 25
= 787510
In the binary system the number of bits in a word can be quite lengthy and
problems can occur such as the high possibility of an error in manipulating
so many digits.
The octal system helps lessen these difficulties, being more compact and
easily converted back to decimal or binary.
-8 -
The system uses the base or radix 8, this means of course, to convert from
decimal to octal we divide by 8 then record the remainders as before and
read upwards to get the octal number.
To convert this number to binary split each octal number into it's three
figure binary number and join together.
Example 1
8 1 remainder 4 UP
1 4 3 4
O remainder 1 001 100 011 100
To convert from binary to octal, start from the right and group into threes, if
the final group does not have three bits then add noughts to make up to the
three .
.!""'
~,ti Example 2
-9-
Example 3
01000002 to octal
I I
I I
0 :1 0 0 :o O O
0 4 0
01000002 = 40s
To convert from octal to binary Oust a recap) the reverse procedure is used.
1 2 6 3
Put into groups
Of three
i
001
~
010 110
~ \011
1263s = 10101100112
Example
tl
08125 x 2 :::; 1.6250
0625 x 2 :::; 1250 read
025 x 2 = 05 down
05x2:::; lO 1
09062510 = 0111012
- 10 -
/
,-.
to convert to octal
09062510 = 072s
0-11101
li\
I I
I I
0 . :I 1 1
r, I
! add nought
'I
J I
111 0 10
7 2
= 72s
Hexadecimal System
This system has a base or radix of 16 and is used again where large binary
numbers are handled to cut down possible errors. Since we have only ten
different digit symbols (0 to 9 inclusive) six other symbols have to be used
these are the letters A to F inclusive. The table below shows the three
numbering systems already considered and the hexadecimal system.
- 11 -
Decimal Octal Binary Hexadecimal
0 0 0000 0
1 1 0001 1
2 2 0010 2
3 3 0011 3
4 4 0100 4
5 5 0101 5
6 6 0110 6
7 7 0111 7
8 10 1000 8
9 11 1001 9
10 12 1010 A
11 13 1011 B
12 14 1100 c
13 15 1101 D
14 16 1110 E
15 17 1111 F
14 t() ,0000 \0
16 762
16 4 7 remainder A t
16 2 remainder F I read up
O remainder 2
:. 76210 = 2FA16
2 B
group into}
4 digits } 0010 1011 1100
:. 2BC16 = 1010111002
- 12 -
ACTIVITY: Convert the following Binary numbers to Hexadecimal
Fractions in Hexadecimal
,I \
Group into four digits 01110 1000
== 01110110002
111100001111101100011.00010011012
74175430464s
1E1F6313416
- 13 -
Binary Coded Decimal BCD
There are several forms of this system but we shall concentrate on the 8421
code. It is used in display read-out systems, decoders and counters.
DECIMAL BCD
23 22 21 20
8 4 2 1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1 ,,
1 0 0 0 ,
8 J
9 1 0 0 1
It is called an 8421 code as each digit is weighted from left to right 8421 in
powers of 2.
You might be thinking that this is the same as the binary code, however,
with numbers from 10 upwards each number is represented by the 4 bit
code.
Is 0100
It\ 0010 1001
10000101
0101
1000
8 5
8510
- 14 -
ACTIVITY: Convert the following decimal numbers to BCD
DECIMAL 347
BINARY 101011011
8421 BCD 0011 0100 0111
OCTAL 533
HEXADECIMAL 159
When a number such as decimal 347 is converted into any binary form the
corresponding group of binary digits is known as a WORD. Each word is
formed of a number of BITS (BINARY DIGITS) and this represents the word
length.
Adding
The rules are similar to those when adding decimal numbers, eg 5+5 = 0 and
carry 1 to the next higher 'power' column, and 1+ 1 in binary results in O
r J'
carry 1.
Rules
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = O with 1 to carry
1011
1110
11001 Note 1 + 1 + 1 = 1 carry 1
111 Carry
= 11001
- 15 -
Subtraction
Rules
0-0=0
1-0=1
1-1=0
0 - 1 = 1 borrow 1
11011
10101 -
lj
00110 ---.,,1-~
Multi plication
Rules
OxO=O
Oxl=O
lxO=O
1x 1 =1
Example: multiply 1100 x 11
1100
_i1
1100
1100 ADD
100100
Division
Rules 1 0
1) 1 1) 0
- 16 -
1010
110) 111100
110
00110
110
00000
,-..; The computer needs to distinguish between positive and negative numbers.
For storage purposes only there is usually an additional bit added which
identifies whether the number is positive or negative, eg:
Example - using an 8 bit binary word the sign bit is added on the front.
Decimal binary .. /
- 25 ...x100100100 f
sign bit
-ve
+ 1025 ...X001010010
sign bit
+ve
As mentioned, this is a convenient method for storing numbers but does not
allow direct subtraction of one number from another.
By inverting the number and adding 1 we get the negative of the number.
This process is called TWO's COMPLEMENT.
The Twos Complement process involves inverting each bit in a word and
adding 1
- 17 -
Example. Find the negative binary number of +5 decimal
Note negative numbers have a 1 in the most significant bit position whilst
the positive number has a 0.
5- 7 = 5 + (-7) +7=0111
Invert= 1000
Add 1 = 1001
= 0101 + 1001
= 0101
1001
1110
1110=-2 +2 0010
Invert 1101
Add 1 ----=1
1110
This means that both addition and subtraction can be done by the same
circuits in a computer which considerably reduces the hardware involved.
DIGITAL CIRCUITS
Logic gates
Devices used in logic networks control the flow of information through the
system and are therefore known as logic gates since the 'gates' are opened
and closed by the binary inputs in order to perform a logical function.
Logic gates are the basic building blocks from which many different kinds of
logical outputs can be obtained. The gates we shall consider are the AND,
NOT, OR, NAND, NOR and XOR gates. They are made up of electronic
components and the output can be represented by Boolean algebra (named
after George Boole (1815 -1864).
- 18 -
Logic gates have binary inputs of 1 or O and they may represent (in a circuit)
ON, CLOSED (logic 1) or OFF, OPEN (logic 0). We shall be using the
American symbols for the gates (there are British Standard symbols but are
not in common use in the aircraft industry).
AND Gate
This gate can have two or more inputs and only one output. It will give an
output if all inputs are on. If any one input is not available the output will be
zero. The symbol for a 2 input AND gate is shown below.
A
s
B
+ve
SWITCH A SWITCH B
~[11 LAMP
1
EARTH
I""'
j The AND gate can be made up electrically by two switches in series.
The lamp will only light when switches A AND Bare both made. If any one
switch is open the lamp will not light.
When switch A is open (logic 0) and switch Bis open (logic 0) there is no
output the lamp (logic 0).
When switch A is made (logic 1) and switch Bis open (logic 0) there is still no
output to lamp (logic 0).
- 19 -
When switch A is open (logic 0) and switch B is made (logic 1) - still no
output to lamp (logic 0).
When switch A is made (logic 1) and switch Bis made (logic 1) there is an
output to the lamp (logic 1).
A B s
0 0 0
1 0 0
0 1 0
1 1 1
Where A and B are the inputs and S is the output. Only 2 inputs are shown
but there may be more A, B, C, D etc.
ACTIVITY: Sketch a circuit for a three input AND gate and draw it's symbol
and derive it's truth table.
The Boolean expression for this gate is written A.B = S. The dot means AND,
and the expression is read as "A AND B equals S" (in some books the output
is called z).
OR Gate
This can have two or more inputs and will give an output if any one input is
logic 1.
A
s
B
- 20 -
SWITCH A
1----< I [ 1,----11 j
+VE
LAMP EARTH
SWITCH B
An OR gate circuit can be made up by two switches in parallel. The lamp will
light if switch A ORB is closed.
A B s
0 0 0 Both switches open
1 0 1 Switch A closed
0 1 1 Switch B closed
1 1 1 Switches A and B closed
A + B = S
NOT Gate
S=A
A
This gate produces an inversion of the input signal, so when the input is A
the output is NOT A, which is symbolised by a bar on top of the A = A. So the
output of this gate is the opposite to it's input.
- 21 -
So input logic 1, output logic 0. Input logic 0, output logic 1. The truth table:
A S
1 0
0 1
S=A
NAND Gate
This is short for NOT AND and works similar to a NOT gate except that it has
more than one input.
A
s
B
The bubble on the end of what is an AND gate has the same function as in
the NOT gate - it inverts the signal, except that in this case more than one
input is involved. In this gate when A is O AND B is O then the output is 1. In
the AND gate this would be 0. So the NAND gate is an inverted AND gate.
A B s
0 0 1
1 0 1
0 1 1
1 1 0
- 22 -
NOR GATE
A
s
8
A B s
0 0 1
0 1 0
1 0 0
1 1 0
XOR Gate
You may have noticed that the OR gate gives an output when A ORB = 1
and when A AND 8 = 1. The XOR gate only gives an output when A OR B are
1 not when A and B are 1, so it is exclusively an OR gate and will not work
under the AND function. It is read as a two syllable word x then or.
A
s
8
- 23 -
The truth table is:
A B s
0 0 0
1 0 1
0 1 1
1 1 0
AB+AB =S
It should be appreciated that for all the gates so far discussed we have
assumed logic 1 is positive (+5 volts) and logic O is zero (0 volts). This is
called POSITIVE LOGIC and is the notation most frequently used.
However, NEGATIVE LOGIC may be used, and this means that logic O is
positive (+5 volts) and logic 1 is zero (0 volts). We shall use positive logic
throughout this book.
:_o_o ~~~0- s
LOGIC CIRCUIT 1
With reference to logic circuit 1, what is the output logic level S if A = logic 1
B = logic O and C = logic 1?
The output of gate 2 is A.B.C (read as "NOT [A AND NOT B] AND C").
- 24 -
ACTIVITY: Study the following circuits and determine the logic level of the
output from each.
0 ?
LOGIC CIRCUIT 2
0 ?
LOGIC CIRCUIT 3
Electronic Gates
Electrics have played a part in logic circuits as shown in the drawings above
on AND and OR circuits. Micro switches, suitably wired are still used on
many aircraft to perform logic functions.
With the introduction of electronics, solid state circuitry can perform the
most complex logic functions with the advantages of minimal size and
weight; very low power consumption, and extremely fast operation.
- 25 -
The s_implest logic using discrete components was the diode-resistor logic,
the diagram below shows an AND gate.
+ve
S =A.B
ov
AND GATE CIRCUIT
t
J
When A or B = 0 then current will fl.ow through the resistor and the diodes.
This means that all the voltage is dropped across the resistor and no voltage
is on the output line, so the output is OV (logic state 0).
When A and B are logic 1 (+5 volts), no current flows, voltage is the same
both sides of resistor Rand output is +5v (logic state 1).
S=A+B
ov
OR LOGIC CIRCUIT
When A or Bare logic 1 current will fl.ow and Swill be high logic 1.
The next advance was resistor transistor logic and diode transistor logic. The
diagrams below show some typical circuits.
- 26 -
R3
Rl
A
B
T2
R2
Rl R2
Tl
B _ _ ,___
Today since the integrated circuit (IC) became possible the logic gates work
by transistor-transistor logic (TTL), metal oxide semiconductors (MOS) and
complementary metal oxide semiconductor (CMOS) group of families.
The following diagram shows a typical IC with it's plastic case partly cut-
,,,..._ away to show the 'chip'.
- 27 -
CONNECTIONS
FROM CHIP
TO PINS
PLASTIC BODY
AN IC PACKAGE
Note the metal pins - for inserting into a suitable IC socket or to be soldered
into a PCB (Printed Circuit Board). Note also the metal connections from the
chip to the pins. The reason for this form of construction is so as to allow the
chip to be connected to other circuits. It is too small, in it's original form, to
be handled and/ or to be connected to anything.
The diagrams below show the some TIL and CMOS gates.
+ sv
Rl R2 R4 R6
Dl
B
F
R3 RS
- 28 -
+SV
Rl R2
+ sv
Dl D2
A s
T2
B
T3
~:
D
Tl~
I
T41
a:rls F
I
CMOS NOR GATE
~
sv
. . ~.'
'~'
A
Tl T2 ds D
+
D F
D
B T3
T4
- 29 -
Properties of TIL and CMOS
TIL uses bi-polar transistors along with diodes and transistors formed to
microscopic dimensions on a slice of silicon (chip). TIL must have a steady
5v de supply, while CMOS will work on de voltages between 3 and 15v and
usually requires much less power. CMOS uses unipolar Field Effect
Transistors (FET) with metal-oxide-silicon technology, this lends itself to
VLSI as they take up less room on a chip, compared to the TIL. CMOS has a
much higher input impedance.
One important point with CMOS is that if static electric charges are allowed
to build up on it's input pins, these voltages can break down the thin layer of
silicon oxide insulation between the gate and the other electrodes of
MOSFET'S and this will destroy the IC. So anti-static protection is important.
Speed of operation - the time that elapses between the application of a signal
to an input terminal and the resulting change in the logical state at the
output terminals.
Fan out - the maximum number of similar circuits that can be connected to
it's output terminals without the output falling outside the limits at which
logic levels 1 and O are specified.
Noise margin - this is maximum noise voltage (unwanted voltage) that can
appear at it's input terminals without producing a change in output state.
- 30 -
If you look back at the diagrams for the TIL AND gate and the ITL NAND
gate you will see that the NAND gate uses fewer components and is therefore
cheaper to produce.
This also applies to the NOR gate, ie it is cheaper to produce than the OR
gate.
NAND gates can be connected together to form any of the other basic gates -
thus reducing production costs by manufacturing one gate only. The
following drawings show how these gates can be formed.
NOT GATE
(INVERTING)
AND GATE
OR GATE
- 31 -
NOR GATE
NAND GATE
The following drawings show the pin connections of ICs for different gate
configurations. There is no need to remember them but it does give a good
idea of how the chip (with the gates in) is connected - although the chip itself
is so small that it looks like a piece of silver metal 4 or 5 mm square.
Vee.
Gnd
Vdd
Vss
- 32 -
Vee
Grd
Vdd
Vss
A A
AB
A+B=AB
B B
AND GATE
A A
A+B A ......8= A+ s
B B
OR GATE
- 33 -
A
A
B
B
NAND GATE
A ';
-.....,/.
A AB=A+ B
B
B
NOR GATE
At first sight it might appear that they are not equivalent by looking at the
Boolean expressions. However using De Morgans rules we can prove they are
~s~e. ~
De Morgans rules state:
A+B=A.B
A.B =A+ B
To apply the rule - split the bar and change the sign.
- 34 -
Taking the first AND gate output A.B output of equivalent circuit A . B =
split the bar A + B change the sign A . B. Double bar over a letter
removes the bar, ie second bar negates the single bar so the output is A.B,
same as the AND gate. This procedure can be used with all the equivalent
circuits. However, much more importantly, to convert the AND gate into it's
OR gate equivalent, remove bubbles where there are any, add bubbles where
there are none. No bubbles on AND gate so add bubbles on all three
connections.
If you look at the NAND gate you will see that the OR gate has two bubbles
on the input (none on the NAND) and none on the output,(one on the NAND).
So WHERE THERE ARE BUBBLES REMOVE THEM, WHERE THER ARE NO
BUBBLES PUT SOME IN, this will then give you the equivalent circuit.
.,.":'
--~;;---
We now need to look at how these gates are used in aircraft circuits. You will
need to be able to interpret these diagrams and explain how an output is
arrived at.
- 35 -
NO. I THkOTTLE
SWITCH ASSY ,. CENTRAL
76-11 AURAL WARNING
II- R
__..,.,? RETA/10
, NO. I THROTTI.E
u 31-51
..
I
l>DVANC. AOVANCEO
15
l. 0 1
II- L
~
NO. 2 THROTTLE
SWITCH ASSY
~ATARO
I
76- II
I
Of THIS DRAWING,
ALL GROUNDS ARE
LOGIC "I", OPENS
ARE LOGIC o.
PROXIMITY SWITCH
a LOGIC UNIT
32-61 SU.TS NOT 26
SU.TS~~ FUU..T EXTENDED
NOT FUU.Y I
~XTEt<OD - A
.
.I.
._/
,
L OUTBOARD FLAP
POSITION XMTR
27-54
oTo2:t~ .. FLAPS
I}- L FLAPS > z~ . GREATER THAN z~ 27
2 TO WARNING
I
II- F
I
SPOILER HANDLE
SWITCH
27-62
RETRACT~ D
EXTEND
I
J.
I
SPOILERS
EXTENOCD
I
a
CIRCUITS
HORIZ STABILIZER
MOTION SENSOR
27-45
IN,
~ GREEN IIAND
II- T
.
'
u HORIZONTAL ST.l81LIZ(R
za
I
HOT IN NOT IN GREEN BA.NO
GAEEH BAND
LEFT
GROUND SENSING
RELAY
3224
~FLIGHT
I ' a
... GROuND
AIRCRAFT
OH GROUNO
I
25
~
It can be seen that it consists of two OR gates and an AND gate, with logic
states sent from 7 parameters.
When either throttle lever is pushed forward, the switch at that position is
made (advance) and there is a logic state 1 to OR gate 1.
- 36 -
Five other parameters are sensed and logic states sent to OR gate 2.
then the inputs to OR gate 2 are all logic O and it's output to the AND gate is
logic state 0.
The aircraft on the ground (weight switch) gives another logic 1 to the AND
gate, which has at this time 2 logic l's and a logic 0.
If either of the four inputs go out of the take-off position eg flaps greater
than 25, then the flap input signal to logic gate 2 is logic 1 which makes the
input to the AND gate logic 1. The AND gate now has three logic 1 's which
now gives an output to the warning circuits (CONFIG light and aural
warning).
zav oc
BAT. aus
L/G POS
SYS 11 <C-30>
K10266 CP37)
'--:.; GEAR OISAGRE
RELAY
LEVER
..~
NOT ON
"937 CYBG) LD
,R LVI (P]-1) @.......
,,..
EICAS COIIPTER (L & l)(EJ-4)
- 37 -
The previous diagram is of an undercarriage "gear disagree" indication
circuit. Systems 1 and 2 sense any disagreement between the landing gear
position and the landing gear selector lever position. So if a disagreement is
detected then the 'gear' light illuminates.
ACTIVITY: Explain the operation of the circuit. (If in doubt about anything
contact your tutor).
FLAP/SLAT
r~
CONFIG WARNING MODULE
ASSY-DISAGREE
ARM/WARNING /
GATES j
~FLAPS
~\ -
EICA.S OISPl.A Y
PROXIMITY SWITOt
ELECTRONICS UNIT
STABILIZER TRIM
(GREEN BAND)
ST A&LIZER POSITION XMIR
PARKING BRAKE
RELEASE
It is important that you look at the logic schematic diagrams for your aircraft
and work out how the gates are used.
- 38 -
So far we have only been looking at combination logic circuits whose outputs
are always the same for the same combination of inputs.
FLIP-FLOPS
Memory type circuits use 'flip-flops' as their main components. There are
many types but we shall look at three, the SR or RS, D and JK flip-flops.
These are so called because on the application of a suitable pulse at the
input it causes it to 'flip' into one of it's two stable states and stay in that
state until a second input will 'flop' it into its previous state.
SR Flip-flop
,-....: The SR flip-flop has two output terminals Q and Q. The diagram shows the
, SR flip-flop using NAND gates.
0
1 tr
o a
SR FLIP-FLOP
-~
'.'_".:,..
When S = 1 R = 0 Q = 1 Q = 0 the flip flop is SET
- 39 -
s R Q Q
1 0 1 0
0 1 0 1
0 0 Depends on state before inputs applied
1 1 Indeterminate
Q = 1 (Q = 0) or Q = 0 (Q = 1).
Clocks
The diagrams below shows a clocked SR flip-flop and it's truth table.
I- - - - - - - - - - - - - - - - - - - - - - - - - I
5 I
A I
I Q
s a
CK (CLOCK)
~SL CK
R
B
R I
I DRAWING SYMBOL
-------------------------
CLOCKED SR FLIP FLOP
- 40 -
OUTPUTS OUTPUTS
DURING
BEFORE AFTER
INPUTS CLOCK
CLOCK CLOCK COMMENTS
PULSE
PULSE PULSE
s R A B Q Q Q Q
0 0 1 1 1 0 1 0 NO CHANGE IN
0 0 1 1 1 0 1 0 OUTPUTS
1 0 0 1 1 0 1 0 FLIP-FLOP SETS
WITH
1 0 0 1 0 1 1 0 Q=l & Q=O
0 1 1 0 1 0 0 1 FLIP-FLOP
RESETS \YJTH
0 1 1 0 0 1 0 1 Q=O& Q=l
1 1 0 0 1 0 1 1 THIS INPUT IS
1 1 0 0 0 1 1 1 NOT ALLOWED
D Type SR Flip-flop
The D stands for delay. If you look at the truth table, when the clock pulse
changes (rises), whatever is at Dis transferred to Q, when clock pulse falls Q
stays at that level. NO MATTER WHAT IS APPLIED TOD, Q will only change
state at the next clock pulse. The truth table shows that the output equals
the input one clock pulse earlier ie, the data is held back until the clock
pulse= 1.
D ~
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -.
$
a
D Q
NS
I er CK
DRAWING SYMBOL
I
L - - - - - - - - - - - - - -- - - - - - - - - - - - -- -
I
- 41 -
OUTPUTS
OUTPUTS AFTER
INPUT BEFORE CLOCK
CLOCK PULSE
PULSE
D s R Q Q Q Q
0 0 1 1 0 0 1
0 0 1 0 1 0 1
1 1 0 1 0 1 0
1 1 0 0 1 1 0
JK Flip-flop
The next diagrams show the layout and truth table of the JK flip-flop using
_)
NAND gates.
I tj
J a
CK
.n_~ --,---. CK
K
K
DRAWING SYMBOL
CK
~ - --- --- - -- -- - --- - -- ----- - -
JK FLIP-FLOP
OUTPUTS
DURING CLOCK OUTPUTS AFTER
INPUTS BEFORE CLOCK
PULSE CLOCK PULSE COMMENTS
PULSE
J K Q Q A B Q Q
0 0 1 0 1 1 1 0 NO CHANGE IN
0 0 0 1 1 1 0 1 OUTPUTS
1 0 1 0 1 1 1 0 STAYS AT OR
SETS TD
1 0 0 1 0 1 1 0 Q=l&Q=l
0 0 0 1 STAYS AT OR
0 1 1 1
RESETS TO
0 1 0 1 1 1 0 1 Q=O&Q=l
1 1 1 0 1 0 0 1
TOGGLES
1 1 0 1 0 1 1 0
- 42 -
The two inputs are called J and K, the operation is fully described in the
truth table and J = K = 1 is allowed (unlike S = R = 1 in a SR flip flop) and
toggles (changes state) when this input is applied.
These flip-flops are used in counters and shift registers and a wide variety of
logic circuits.
Counters
There are many types of counters and the flip-flop counter is the one
discussed here. The next diagram shows the basic principles of counting
using flip-flops. It is a 4 bit binary counter using JK flip-flops. The J & K
inputs are at logic 1 so any pulse 1 to O will trigger the output to change
from it's previous state. The output of one flip-flop is the input to the next -
f". they are said to be connected in 'cascade'.
OUTPUT PULSES
QA QB QC QD
..~
. ...............................................................................
.:
:. .
.
J Q
. A 4-BIT BINARV COUNTER
It R It R It R It R
RESET
1.................................................. 11 .. .. l
BUPPLV
+ve -ve
START
I
I
INPUT
PULSES
0
r it
,_ '
.. ...
,.,;:;.?
ClA
0
QB: I 0 t' I
0
o'-----'r
l'-----'~~ y
QC: I v ---=--0
.
_____.!-/_....____,~
OD J 0
I/ l_
BACK
TO
START
FOUR BIT BINARY COUNTER
- 43 -
As can be seen from the diagram, every time the input pulse falls from 1 to O
the counter increases the 4 bit binary number by 1, eg:
You should now be able to follow the sequence through yourself. Remember
every time the outputs go from 1 to O the next flip-flop triggers. When the
count reaches 1111 (15) all four flip-flops are reset.
Studying the diagram further you will see it takes two input pulses to make
flip-flop A go from Oto 1 and back to 0, two pulses from QA to force QB from
Oto 1 and back again, and so on down the chain.
In fact each flip-flop acts as a divide by two circuit and four flip-flops in a
chain like this make a divide by 16 circuit, because the pulse frequency at
Qo output is one sixteenth of the frequency of the input.
QUESTION: If there are two flip-flops connected in cascade what would the
division be? (5 mins). If you are not sure of the answer check
with your tutor (Full Students).
Shift registers
Assume the register is cleared and therefore reads 0000 and an externally
generated word 1011 is to be stored in the register. At the end of the first
clock pulse QA= 1 JB = 1. After the second clock pulse flip-flop Bis set QA=
1 QB= 1.
The state of the register when the third clock pulse arrives is JA = 0 KA = 1
JB= Jc= 1 KB= Kc= 0 and at the trailing edge of the clock pulse flip-flop A
resets and flip-flop C sets. Now QA= JB = 0, QB = Qc =Jc = Jo = 1.
- 44 -
The last bit to be stored is 1 and at the end of the fourth clock pulse flip-
flops A, C and Dare set and flip-flop Bis reset ie 1011 is stored. The effect of
each clock pulse is to shift the content of the register one place to the right.
0 0 0 0
SERIAL INPUT
1011
~-----l J a J a J a
SERIAL
T A T 8 T C T D OUTPUT
K K K K
RESET
CLOCK OR SHIFI' PULSE
The shift register shown is SERIAL IN and SERIAL OUT but a register can
also be:
OUT
IN
IN
......_____!-~ OUT
- 45 -
IN
OUT
Encoders
These are generally at the input end of a system to convert the input signal
into a binary code necessary for the operation of the system. Encoding
circuits may take many forms eg: convert an analogue signal to BCD or 4 bit
binary code; take in a binary signal and convert it into another code to suit
the system eg, OCTAL to BCD.
SWITCHES
DECIMAL
INPUT__.,
D C B A (lsb)
CHASSIS EARTH
+
BINARY CODED DECIMAL OUTPUT
- 46 -
The drawing shows a keyboard layout (decimal input) to give a BCD output.
By pressing any one key or switch (suitably decimal numbered) the
appropriate BCD code is given at the output.
Assume "4" is pressed then diode Ds will conduct through Re making the
output (C) go high, all the other inputs stay low (DBA), so the output is 0100
(decimal 4).
In Flight Data recording some of the inputs into the system are in analogue
form, such as de, ac or syncro signals. This mans that they have to be
encoded into digital for use by the Central Processing Unit (CPU). This is
done by an Analogue to Digital Converter.
The diagram below shows the basic layout of a digital ramp converter.
When the start pulse is applied, it becomes logic 1, the counter is reset, no
pulses are fed through the AND gate as it is 'closed'.
DIGITAL OUTPUT
CLOCK
ANALOGUE
INPUT
START
DIGITAL TOANALOOUE
CONVERTER
A comparator is a device with two inputs which compare the voltages at each
input to determine which is greater, the output is logic 1 if A is larger than B
and logic O if input Bis larger than A. On start Bis 0, A is the larger output,
from the comparator is logic statel and when the START pulse goes low the
AND gate 'opens' and the clock pulses go to the counter. Each pulse causes
the counter to advance.
- 47 -
As the counter counts up, its value is converted into it's analogue equivalent
by the digital to analogue convertor (DAC or D to A or D / A) and applied to
the comparator at B. The DAC output therefore increases in steps until it
reaches just above the analogue input level ie, B input >A. The comparator
output goes low, AND gate closes, the count stops, the digital read-out is
then taken from the counter.
The best approximation we can obtain, depends on how much input B has to
be greater than A ie, the step size, this is known as the quantization error.
This type of Analogue to Digital (ADC or A to Dor A/D) converter is slow in
operation and is unsuitable for high speed operation, and of course the
larger the voltage the longer (more steps) time it takes. The comparator
would be an operational amplier (see JAR Module 4).
However, the fastest type of ADC of the ones considered is the successive
approximation type.
CONTROL DIGITAL
LOGIC OUTPUT
DAC
This is similar to the previous circuit but the register is used instead of a
counter and a control logic block is included between the comparator and
register, which controls the output of the register.
Initially a reset signal puts all bits in the register to 0. The control logic sets
the MSB in the register to 1 and the rest to logic 0. The output of the DAC is
then compared to the analogue input if B > A then this number is too large
and the MSB remains at 1.
- 48 -
At the next clock pulse the control changes the next bit in the register B>A it
is set to O if B<A it is set to 1 and so on until all the bit values are found. The
digital read out can then be read.
This has a fast conversion time which does not depend on the analogue
voltage level but just the number of bits in the converter.
Decoders
.......
BINARY COOED
DECIMAL TO
BCD NUMBERS
'O' MEANS A LOW VOLTAGE
CURRENT FLOWING THROUGH
THE SEGMENT TO EARTH
SEGMENT ON
""r"
. - - - - - - .-
0,. ~1-o/
.. . _ _.
O
\
z
y
.f :,-:-----------'
d O
BCD T07 e 1 (NO CURRENT SEGMENT OFF)
0
x SEGMENT
f O
w DECODER
g O
EXAMP\.E. THE
NUMBER9
DECIMAL. COOED
t
THE EXAMPLE SHOWS '9' AS
TO BINARY (1001) SEGMENTS a b c d f & g ARE ON
A SEVEN SEGMENT CODE
0000100 SHOWING THE CHARACTER '9'
- 49 -
Digital to Analogue Converter
The next drawing shows a binary weighted resistor method, so called as the
values of the resistors increase in accordance with the binary system eg, R,
2R, 4R, SR. The output from the resistor chain is connected to an
operational amplifier as a summing amplifier with a feedback resistor R r. The
output Vo is therefore Vo= - Rr( V1 + V2 + V3 +.Yu (see JAR Module 4)
(R 2R 4R SR)
Also in the circuit are four switches S, S1. S2. S3, S4 which are electronic
switches (digitally controlled). Each switch connects the resistor to a fixed
reference Vref when the input bit is logic 1 (+5v) and to ground (Ov) when the
input bit is logic 0.
VREF
51 R
V1
msb R1 J '
52 2R
V2
VO
ANALOGUE
53 4R OUTPUT
4BIT V3 VOLTAGE
DIGITAL
INPUT
V4 8R
lsb
ov
II'
CHASSIS EARTH
Vo = (Yi+ V2 + V3 + V4 l
( 2 4 S )
- 50 -
Vo =- (0 + 0 + 04 -JU
8
Vo=+ lv
Note. With the example shown the output was positive but if Vref was +8v
then the output would be -lv.
Vo= - (-....__)
( 2)
= + 4v
ACTIVITY: If the Vref is -5v what would be the weighting of the LSB in this
system where Rr = R 1K?
The accuracy of this system depends on the resistors and the precision of
the input supply. Resistors can be made to reasonable accuracy and the
electronic switches can be replaced by precision level amplifiers, these
ensure there outputs are exactly 5v or Ov depending upon their outputs.
High input ensures 5v from the amplifier to the input resistor of the op amp
(operational amplifier) and a low output ensures Ov.
R - 2R Type D to A Converter
Another problem is the larger the bit word the more the range of resistors is
required ie, for every extra bit the range of the required resistors doubles. So
another method of converting digital to analogue must be found for digital
words with a large number of bits - it is called the R- 2R type.
The circuit works on the principle that a pair of 2R resistors at the end of the
ladder can be considered in parallel, forming an overall resistance R.
- 51 -
This system does use twice the number of resistors compared to the binary
weighted network, but the use of only two values of resistors means the
system can handle any number of input bits, simply be extending the
resistor ladder.
It is not essential you know the full operation of this DAC but you should
know it exists.
Rf
R R R 2R Vout
2R
2R 2R 2R 2R
Vl V2 V4
lsb msb
With reference to the drawing above Vout = V Rr (8v4 + 4v3 + 4v2 + 4v 1) for
the bit input shown. 16 R
'Multiplexers
A multiplexer is a device which selects data from one of many inputs and
connects this data to a common single output. Some practical examples are
in Flight Data Recording {FDR) where the Digital Flight Data Acquisition Unit
(DFDAU) receives a large number of inputs from the various aircraft
parameters which have to be sampled and eventually fed to the FDR.
- 52 -
When the passenger selects the required service eg the film channel, then
only the information on that line relevant to the film channel is selected by a
'de-multiplexer' and fed to the passenger.
Eachtrain is sent down the same main line in this fashion. Data can be
transmitted like this, but at much greater speeds of course.
DATA
INPUTS
--- 0j)-----
/
COMMON LINE
DATA OUTPUT
r The next diagram shows the basic principle of a multiplexer showing the
data to be transmitted. Just check, first of all you are satisfied that with the
inputs on X and Y = 0. These are the 'command signals'.
A B c 0
x O
DATA SELECT
y O
26
- 53 -
So with command input of X = 0 Y = 0 logic 1 goes out through the OR
gate. Now work through the multiplexer action when X = 1 Y = O. You
should see the AND gate 2 gives logic 1. Now try X = 0 Y = 1 and you will see
the AND gate 3 gives an output of 1 and finally when X = 1 Y = 1 then AND
gate 4 will give an output of 1. So the OR gate will have passed the input
1111 down to data highway.
The next diagram shows Four data channels operating at 200bits/ sec. The
buffer store is a holding store until access to the data highway is signalled.
2 COMMON 2
800 BIT/ S LINE
3 3
3 3
4 4
Data from the systems connected to Channels 1, 2, 3 and 4 are fed into a
Buffer Store, until each store is signalled by the clock pulse to output its
data onto the common line in sequence.
- 54 -
As you can see from the diagram there must be some way of converting
these signals to the appropriate receiving channel, ie channel 1 input signal
data to be picked up by channel 1 receiving channel.
De-multipexer
These are similar to a multiplexer but work "the other way round". They take
r'- sequential input data from a common data line and output each piece of
data to it's appropriate channel. The drawing below shows the mechanical
equivalent of the electronic device.
COMMON LINE
SERIAL DATA INPUT LJ SEPARATE DATA
LINE OUTPUTS
~ -
It has 8 AND gates, three NOT gates, and input line and 8 output lines.
As the name implies it has 1 input line and 8 output lines, with the single
data input line is connected to all eight gates. Each gate will be enabled by
the signals on the select lines 82 81 So.
Assuming 000 input on the select lines only GATE O will open and the data
will appear at its output. The truth table shows the logic states of the de-
multiplexer .
- 55 -
00 =
52 01=
51
02 =
so \
-..,J'
03=
04=
05 =
06=
07 =
DATA INPUT
<r,
.'
SELECT CODE OUTPUTS
S2 S1 So 07 06 05 o, 03 02 01 Oo
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
- 56 -
The next diagram shows the basic principles of a passenger entertainment
system.
The multiplexer selects all the inputs in turn, (12 channels of recorded
music, passenger address messages and tape signals) digitises them
(analogue to digital converter) into one serial data signal stream. This stream
of data is fed to the seats via the sidewall disconnects. The data is received
by the electronic boxes. Depending on the selection made by the passenger,
the signal is de-multiplexed and decoded (digital to analogue) to output the
required signal.
PASSENGER CONTROL
UNIT (PCU)
CON INSIDE Of ARN REST)
--
TAPE
-------- REPRODUCER PASSENGER CONTROL
UNIT (PCU)
12 CHANNELS (ON INSIDE Of AR/I REST)
RECORDED
HUS IC
ADDRESS
HESSAGES
SIDE WALL
HUL TIPLEXED DISCONNECT
AUDIO AND C1ST SEAT IN
POIIER FWD COLUMN)
SIDE WALL
DISCONNECT
C1ST SEAT IN
AFT COLUHN)
- 57 -
ASSIGNMENT
(i) Encoding
(ii) Decoding
(iii) A to D conversion
(iv) D to A conversion
(v) Multiplexing and de-multiplexing
3. Sketch an aircraft system using logic gates and explain its operation.
- 58 -
SOLUTIONS TO ACTIVITIES
Page 4
(a) 1 x 24 + 0 x 23 + 0 x 22 + 1 x 21 + 1 x 20 = 1001 b
= 10110.000b
Page 5
(a) 2 846
2 423r0
2 21 lrl
2 105rl
2 52rl
2 26r0
2 13r0
2 6rl
2 3r0
2 lrl
Or 1 = 110 100 11102
(b) 2 317
2 158rl
2 79r0
2 39rl
2 18rl
2 9rl
2 4rl
2 2r0
2 lrO
Orl = 100111 lOb
- 59 -
(c) 2 147 ,._.:
2 73rl
2 36rl
2 18r0
2 9r0
2 4rl
2 2r0
2 lrO
Orl = 1001001 b
Page 6
(a) 32 16 8 4 2 1
1 0 1 1 1 12 = 4710
,,--
(b) 32 16 8 4 2 1 ;.
1 0 0 0 0 0 2 = 3210 ~;
(c) 32 16 8 4 2 1
1 0 1 0 12 = 2110
Page 8
(a) 32 16 8 4 2 1
1 1 0 0 1 12 = 5110
(b) 64 32 16 8 4 2 1
1 1 1 0 0 1 b = 11510
(c) 8 4 2 1 .5
1 0 1 1 . 12 = 11.510
Page 10
(a)
I 10~010b\
1! I
101 0*0' 100
5 2 4a
/11Jf!l\
(b)
.._,/
001 110 100 000
1 6 4 Os
- 60 -
I l
(c) /1~o~opo\
111 010 001
7 2 ls
(a)
/\6~
100 010 110
1000101102
(b) 5 6 2 5s
J( +~
110 010 110
~
101
1011100101102
I""
(c)
,I'
6 5 2 1 7s
Page 11
!
(a) 1111.1112
.. I i
7 . 7s
r
' .
5 . 4s
11oj.011j100
..,...,,,,~
' ~:-:;
(c)
......
6 . 3 4s
(a)
.
.64
~
.1101002
(b) .77s
.. )t
.111 llb
(c)
~
.43s
.100 Olb
- 61 -
Page 13
I ! I
(a) il 110! 00102i
i t I ~ i
E 415
I I I
(b) i O11 lj 1111 i
; -f ; ~ ;
7 F16
I I I
(c) i 001 lj 1001 i
,t ; ~
3 916
(a) 2 D
.. 32 16 8 4 2 1
0010 1101 = 1 0 1 1 0 b = 4510
(b) lAF
~ ~ 256 128 64 32 16 8 4 2 1
0001 1010 1111 = 1 1 0 1 0 1 1 1 l 2 = 43110
(c) 21A
.. -._. 512 256 128 64 32 16 8 4 2 1
0010 0001 1010 1 0 0 0 0 1 1 0 1 02 = 53810
(a) 163210
(b) 494
256 128 64 32 16! 8 4 2 1
0001 1 ! 1 1 !
0 1 1 1 02
1 E E16
(c) 5174
I I
4096 2048 1024 512 256! 128 64 32 16! 8 4 2 1
0001 0 1 0 0 !0 0 1 li O 1 1 0
1 4 I 3 I 616
- 62 -
178 to Decimal
0001
Ii \ 0111 1000 =
'
ll')
C'l
co
C'l
~
v
sO
1 0 1 1 1 1 0 0 02
C'l
M
'
~ CO V N ~
= 37610
= 1011111!000
= 570s
EF16 = 111011112
= 23910
= 011J101J111
= 357s
Page 13 (bottom)
(a) 0.6250
= 12 1 + 0 x 2-2 + 1 x 2-3
= .1010
(b) 0.81250
= 1 x 2 1 + 1 x 2-2 + 1 x 2-3 + 1 x 2- 4
= .1101
= .015
'
(a) 9 4
r i1
'~i:. 1001 0100
\
(b) 5 2 9'\.
~ )l
0101 0010 1001
(c) 2 9 4 7"'-....
/ ~ \ ~
0010 1001 0100 0111
I I
(a) 011 li 0000 ilOOl
7 . 0 . 910
(b) 0011lo11olo100
3 . 6 . 410
- 63 -
Page 25
Page 35
1
1>-
l1
-
2
=D- =D-
3 =D-
Page 38 For both these activities send your answers to your tutor (Full
Students only).
- 64 -