Field Effect Transistor

Field Effect Transistor

The FET transistors are voltage controlled devices,
where as the BJT transistors are current controlled
devices.
The FET transistors have basically three terminals, such
as Drain (D), Source (S) and Gate (G) which are
equivalent to the collector, emitter and base terminals
in the corresponding BJT transistor.
In BJT transistors the output current is controlled by
the input current which is applied to the base, but in
the FET transistors the output current is controlled by
the input voltage applied to the gate terminal.
 Field Effect Transistor
uses the voltage that is applied to their input terminal, called
the Gate to control the current flowing through them
resulting in the output current being proportional to the input
voltage.
As their operation relies on an electric field (hence the name
field effect) generated by the input Gate voltage, this then
makes the Field Effect Transistor a VOLTAGE operated
device.
The BJT transistors are bipolar devices because they
operates with both types of charge carriers, such as electrons
and holes but the FET transistors are unipolar devices
because they operate with the charge carriers of either
electrons (for N-channel) or holes (for P-channel).
 Field Effect Transistor
In the FET , the output current passes between the drain and
source terminals and this path is called channel and this
channel may be made of either P-type or N-type
semiconductor materials.
The control of current flowing in this channel is achieved by
varying the voltage applied to the Gate.
In BJT, a small input current operates the large load, but in FET
a small input voltage operates the large load at the output.
TYPES:
Junction Field Effect Transistor (JFET)
Insulated-gate Field Effect Transistor (IGFET), which is
more commonly known as the standard Metal Oxide
Semiconductor Field Effect Transistor (MOSFET)
 JFETs can be used for several applications
including:
High Input Impedance Amplifier
Low-Noise Amplifier
Differential Amplifier
Constant Current Source
Analog Switch or Gate
Voltage Controlled Resistor
 The Junction Field Effect Transistor
The Junction Field Effect Transistor (JFET) has no PN-junctions
but instead has a narrow piece of high resistivity
semiconductor material forming a Channel of either N-type
or P-type silicon for the majority carriers to flow through with
two ohmic electrical connections at either end commonly
called the Drain and the Source respectively.

The N-channel JFETs channel is doped with
donor impurities meaning that the flow of
current through the channel is negative
(hence the term N-channel) in the form of
electrons.
in the P-channel JFETs the channel is
doped with the acceptor impurities due to
this the current flowing through this
channel is positive (i.e. due to holes).
 Junction Field Effect Transistor (JFET)
1. The N-channel JFET has more current conduction than
P-channel JFET because the mobility of electrons is
greater than the mobility of holes.
2. So the N-channel JFETs are widely used than P-
channel JFETs.
3. in JFET the Drain and Source terminals are connected
with the channel.
4. The small voltage at the gate (G) terminal controls the
current flow in the channel (between drain and
source) of the JFET.
5. The small voltage applied at the gate terminal
controls the current flow in the channel between the
drain and source of the JFET.
6. This gate voltage is negative in N-channel JFET and it
is positive in P-channel JFET
 P-channel JFETs channel is doped with acceptor
impurities meaning that the flow of current
through the channel is positive (hence the term
P-channel) in the form of holes.
N-channel JFETs have a greater channel
conductivity (lower resistance) than their
equivalent P-channel types, since electrons have
a higher mobility through a conductor compared
to holes.
This makes the N-channel JFETs a more efficient
conductor compared to their P-channel
counterparts.
 One of the main differences between the BJT and JFET transistors is
that when the JFET has reverse-biased junction, then the gate
current may be zero, but in the BJT the base current always must be
greater than zero. The comparison of symbols between BJT and
JFET is shown in the below figures.
 Operation of JFET
is based on controlling the bias on the PN junction
between gate and channel (note that a single PN
junction is discussed since the two gate contacts are
tied together in parallel what happens at one gate-
channel pn junction is happening on the other).

If a voltage is applied between the drain and source,

current will flow (the conventional direction for current
flow is from the terminal designated to be the gate to
that which is designated as the source).

The device is therefore in a normally on state.

To turn it off, we must apply an appropriate voltage to
the gate and use the depletion region created at the
junction to control the channel width.
 An n-type channel is formed between two p-type layers
which are connected to the gate.

Majority carrier electrons flow from the source and exit the
drain, forming the drain current.

The pn junction is reverse biased during normal operation,

and this widens the depletion layers which extend into
the n channel only (since the doping of the p regions is
much larger than that of the n channel).

As the depletion layers widen, the channel narrows,

restricting current flow.
 biased N-channel JFET
The JFET is always operated with the gate-source PN junction reverse-biased
a voltage is assumed to be applied so that the drain is positive relative to the
source
VDS provides a drain-
to-source voltage
and supplies current
from drain to source

VGS sets the reverse-bias

voltage between the gate
and the source

If the gate is diffused into the N-type channel, then a reverse biased PN-junction is formed
which results a depletion region around the gate terminal when no external supply is
applied to the transistor. Generally the JFETs are called as depletion mode devices.

This depletion region produces a potential gradient which is of varying thickness around
the PN-junction and restrict the current flow through the channel by reducing its effective
width and thus increasing the overall resistance of the channel itself.

Comparison between a JFET and a BJT

Bipolar Transistor Field Effect Transistor

Emitter (E) >> Source (S)

Base (B) >> Gate (G)

Collector (C) >> Drain (D)

 Biasing of an N-channel JFET
dc bias voltages applied to an n-channel JFET
The JFET is always operated with the gate-source PN junction reverse-biased

VDD provides a drain-to-

source voltage and
VGG sets the reverse-bias supplies current from drain
voltage between the gate to source.
and the source.

Assume VGG = VGS.

Reverse-biasing of the gate-source junction with a negative gate voltage produces

a depletion region along the PN junction, which extends into the N channel and
thus increases its resistance by decreasing the channel width.

The channel width and the channel resistance can be controlled by varying the
gate voltage, thereby controlling the amount of drain current ID.
 JFET drain characteristics curve for VGS = 0
Variable VDS (VDD)

ID becomes essentially constant

the gate-to-source voltage is zero the drain current is at maximum
(VGS = 0 V) (by shorting the gate to for VGS = 0 condition and is
the source)
defined as IDSS JFET begins to breakdown
where the ID increases
rapidly and it is an
As VDD is increased from 0 A, ID irreversible breakdown
will increase proportionally As VDS increases from point B to
point C, the reverse-bias voltage
the region where the voltage from gate to drain (VGD) produces a
Breakdown can result
and current relationship depletion region large enough to
offset the increase in VDS, thus
in damage to the
follows Ohm's law device, So JFETs are
keeping ID relatively constant.
operated below
the channel resistance is essentially breakdown and
constant because the depletion within the constant-
region is not large enough to have current area.
significant effect.
pinch-off voltage.This value of drain current is IDSS
(Drain to source current with gate shorted)
 VGS controls ID
connect a bias voltage, VGG, from gate to source as

As VGS is set to increasingly more negative

values by adjusting VGG, a family of drain
characteristics curves

ID decreases as the magnitude of VGS is

increased to the larger negative values because
of the narrowing of the channel

For each increase in negative values of VGS, the

JFET reaches pinch-off at values of VDS less
than VP. So, the amount of drain current is
controlled by VGS.
Pinch-off occurs at a lower VDS as VGS is
increased to more negative values
 At ohmic region of the drain characteristic curve for n-channel
type

The pinch-off curve

 Cutoff voltage
The value of VGS that makes ID approximately zero is the cutoff
voltage, VGS(off).

This cutoff effect is caused by the

widening of the depletion region to a
point where it completely closes the
channel.

The JFET must be operated between VGS = 0 V and VGS(off).

For this range of gate-to-source voltages, ID will vary from a maximum
of IDSS to a minimum of almost zero.

The relation between VP and VGS(off) is VP = VGS(off).

 example
For the JFET, VGS(off) = 4 V and IDSS = 12 mA.
Determine the minimum value of VDD required to
put the device in the constant-current are of
operation

If VDD is increased to 15V, what is ID and

VDS?
ID remains at approximately 12 mA.
 JFET Transfer Characteristic
an n-channel JFET, VGS(off) is negative, and for a p-channel JFET,
VGS(off) is positive. Because VGS does control ID, the relationship
between these two quantities is very important

general transfer characteristic curve that

illustrates graphically the relationship
between VGS and ID

The JFET transfer characteristic curve

shows that the operating limits of a JFET
are ID = 0 when
VGS = VGS(off)
and
ID = IDSS when VGS = 0
The JFET transfer characteristic curve can be developed from the drain characteristics
curves,

n-channel JFET transfer characteristic

curve (blue) from the JFET drain
characteristic curves (green).
 JFET Biasing Circuits
gate bias of biasing arrangements for the n-channel JFET

coupling capacitors (C1 and C2)

KVL:

to ensure that Vi appears at the

input to the FET amplifier for the
ac analysis
Network for dc analysis
 Determine the Q-point values for the gate biasing circuit if
VGG=0.5V, VGS(off) = -7 V, IDSS = 9 mA, VDD = 5 V and RD = 500