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Index
This chapter contains a collection of data sheets for the generator models contained in the PSSE
dynamics model library.
Model Description
CBEST EPRI battery energy storage FACTS model
CDSMS1 American Superconductor DSMES device model
CGEN1 Third order generator model
CIMTR1 Induction generator model with rotor flux transients
CIMTR2 Induction motor model with rotor flux transients
CIMTR3 Induction generator model with rotor flux transients
CIMTR4 Induction motor model with rotor flux transients
CSMEST EPRI superconducting electromagnetic energy storage FACTS model
CSTATT Static condenser FACTS model
CSVGN1 SCR controlled static var source model
CSVGN3 SCR controlled static var source model
CSVGN4 SCR controlled static var source model
CSVGN5 WECC controlled static var source model
CSVGN6 WECC controlled static var source model
FRECHG Salient pole frequency changer model
GENCLS Classical generator model
GENDCO Round rotor generator model with dc offset torque component
GENROE Round rotor generator model
GENROU Round rotor generator model
GENSAE Salient pole generator model
GENSAL Salient pole generator model
GENTRA Transient level generator model
1.1 CBEST
EPRI Battery Energy Storage
STATEs # Description
K AVR state 1
K+1 AVR state 2
K+2 IQ, reactive current (pu)
K+3 Energy output (pu sec)
K+4 Energy input (pu sec) ( < 0 )
VARs # Description
L PAUX, supply signal (MW)
L+1 PINIT (pu on MBASE)
L+2 POUT (pu on SBASE)
L+3 QOUT (pu on SBASE)
L+4 EOUT total energy (pu on SBASE, sec)
VARs # Description
L+5 Memory
This incorporates technology developed for the United States Electric Power Industry under the
sponsorship of the Electric Power Research Institute (EPRI).
1 + PAC MBASE
PAUX 1 1 POUT
MBASE SBASE
PMAX IACMAXVAC
POUT > 0
OUTEFF
s
+
POUT EOUT
+
POUT < 0
INPEFF
s
1.2 CDSMS1
American Superconductor DSMES Device
This model incorporates technology of American Superconductor Corporation (ASC) and was
developed under the sponsorship of ASC.
STATEs # Description
K IQ, Q-path reactive current (pu)
K+1 AVR state 1 (pu)
K+2 AVR state 2 (pu)
VARs # Description
PAUX, active power control signal
L
(MW)
POUT, output active power (pu on
L+1
SBASE)
QOUT, output reactive power (pu on
L+2
SBASE)
L+3 IDC, output D_SMES DC current (kA)
L+4 IL, coil current (kA)
VTR, D-SMES step-up transformer low
L+5
voltage (pu)
L+6
Internal Storage
L+22
ICONs # Description
CONV_TYPE, converter type:
M 0 current-source converter
1 voltage source converter
IBUS_CONTR:
M+1
number of remote control bus
BOOST_CONTR, boost control flag:
M+2 0 if no
1 if yes
VOLT_SEN_LOC, voltage control sensor
location flag:
M+3
0 for the D-SMES bus
1 for controlling the remote control bus
TURN_ON_VOLT, voltage control flag:
0 if no
M+4 1 if yes
No means that Vi thresholds are ignored
by P-path.
TURN_ON_POWER, active power
(damping control) flag:
M+5 0 if no
1 if yes
No means that PAUX signal is ignored.
TURN_ON_P, active power output flag:
0 if no
M+6
1 if yes
No turns off P-paths (POUT=0).
TURN_ON_Q, reactive power output flag:
0 if no
M+7
1 if yes
No turns off Q-path (QOUT=0).
VDSMES
Selecting VAC
Vremote the Control
Voltage
V1 Calculating
V2 the Voltage AVR_MODE
V3 Mode Analyzing
V4 (AVR_MODE) the
DSMES
Operation ADSOC
PAUX Conditions Output P-path
Algorithm POUT
(ADSOC)
ADSOC Q-path
BOOST_CONTR Boost Flag Output Algorithm QOUT
DT01_010
General Diagram
V1
VAC V1 AVR_MODE=5
V2
V2 VAC < V1 AVR_MODE=4
V3
V3 VAC < V2 AVR_MODE=3 AVR_MODE
V4
V4 VAC < V3 AVR_MODE=2
VAC
VAC < V2 AVR_MODE=1
DT01_011
The MW Injection of DSMES is also enabled immediately after VAC quick crossing the
V3 > VAC V4 range.
IINIT IINIT
IMIN t
IMIN t t1 t2 t3
t* t* + TDIS t1 + t2 + t3 = TDIS
DT01_013
Calculating
IL
the Coil Current IL
(see the magnet PMAX IACMAX VDSMES
discharge curve)
PDC 1 MBASE POUT
1 1
VDC MBASE SBASE
ADSOC
Output P-path PDC = PAUX
OR (dissipating energy PMIN IACMAX VDSMES
Branch OR
Selection by the resistor bank) POUT
POUT = 0
DT01_014
P-Path Algorithm
Q-Path Algorithm
VREF VQMAX IQMAX
QLIM
+
VAC (1+sT1) (1+sT2) KAVR IQ Q MBASE QOUT
1
(1+sT3) (1+sT4) S SBASE
POUT
QLIM
VQMIN IQMAX VDSMES
ADSOC
Output Q-path QOUT
Branch OR
Selection AVR_DROOP
Siemens Energy, Inc., Power Technologies International
QOUT = 0
DT01_015
Overload Diagram
P OUT 2
2 SLIM if AVR MODE < = 2 and t > t*
I QMAX = I
ACMAX V DSMES SLIM MAX
2 2
Q LIM = S P SRATED
LIM OUT
t
t*
S LIM MAX = KOL S RATED TOVLD TBACK
DT01_016
PSSE32.0.5
PSSE32.0.5 Generator Model Data Sheets
PSSE Model Library CGEN1
1.3 CGEN1
Third Order Complex Generator Model
STATEs # Description
K speed (pu)
K+1 Angle (radians)
K+2 rd (1)
K+3 rd (2)
K+4 rd (3)
K+5 rq (1)
K+6 rq (2)
K+7 rq (3)
VARs # Description
L Internal memory
L+1 Internal memory
All constants except S(1.0) and S(1.2) are in pu machine MVA base.
Set Rmd (2), Lmd (2), Rkd (2) and Lkd (2) to 0 for 2nd order d-axis model.
Set Rmq (2), Lmq (2), Rkq (2) and Lkq (2) to 0 for 2nd order q-axis model.
d-Axis
Iq Laq
q-Axis
1.4 CIMTR1
Induction Generator Model
STATEs # Description
K Eq
K+1 Ed
K+2 Eq
K+3 Ed
K+4 speed (pu)
VARs # Description
Admittance of initial condition Mvar
L
difference
L+1 Motor, Q
L+2 Telec
ICON # Description
M Memory
1.5 CIMTR2
Induction Motor Model
STATEs # Description
K Eq
K+1 Ed
K+2 Eq
K+3 Ed
K+4 D speed (pu)
VARs # Description
Admittance of initial condition Mvar
L
difference
L+1 Motor, Q
L+2 Telec
ICON # Description
M Memory
1.6 CIMTR3
Induction Generator Model
STATEs # Description
K Eq
K+1 Ed
K+2 Eq
K+3 Ed
K+4 speed (pu)
K+5 Angle deviation
VARs # Description
Admittance of initial condition Mvar
L
difference
L+1 Motor, Q
L+2 Telec
ICON # Description
M Memory
1.7 CIMTR4
Induction Motor Model
STATEs # Description
K Eq
K+1 Ed
K+2 Eq
K+3 E
K+4 speed (pu)
K+5 Angle deviation
VARs # Description
Admittance of initial condition Mvar
L
difference
L+1 Motor, Q
L+2 Telec
ICON # Description
M Memory
1.8 CSMEST
EPRI Current and Voltage-Source SMES Device
STATEs # Description
K IDC, coil dc current (pu)
K+1 AVR state 1
K+2 AVR state 2
K+3 IQ, reactive current (pu)
VARs # Description
L PAUX, supplementary signal (MW)
L+1 PINIT (pu on MBASE)
L+2 POUT (pu on SBASE)
L+3 QOUT (pu on SBASE)
L+4 VDC (pu)
L+5 Memory
ICON # Description
0 current-source converter
M
1 voltage-source converter
This incorporates technology developed for the United States Electric Power Industry under the
sponsorship of the Electric Power Research Institute (EPRI).
IDCVDC(IDC)[IDCIDCMIN1]
PINIT
PMAX IDCVDCMAX IACMAXVAC KVACIDC
+
1 + MBASE
PAUX 1 1 1 1 1 POUT
MBASE PDC SBASE
+
PMAX IDCVDCMIN IACMAXVAC KVACIDC
IDCVDC(IDC)[IDCIDCMAX1]
KR IDC0
+
1 1
PDC IDC VDC sL IDC
DROOP
P DC 2 P DC 2 or P DC 2
I2 ------------- I2 ------------- K I 2 -------------
ACMAX V ACMAX V
I =
QMAX DC V AC
AC AC
1.9 CSTATT
Static Condenser (STATCON)
STATEs # Description
K First regulator
K+1 Second regulator
K+2 Thyristor
VARs # Description
L Ei, Internal voltage (pu)
L+1 ISTATC, STATCON current
L+2 Internal memory
VREF
VMAX Limit Max
+ VAR(L)
(1 + sT1) (1 + sT2) K + 1 MBASE
|V| S Xt ISTATC
(1 + sT3) (1 + sT4) SBASE VAR(L+1)
Ei
VMIN Limit Min
Other ET
Signals
VOTHSG DROOP
where:
I CMAX V T
I CMAX0 = -------------------------------
- otherwise
V CUTOUT
I LMAX V T
I LMAX0 = ------------------------------
- otherwise
V CUTOUT
Note: |V| is the voltage magnitude on the high side of generator step-up transformer, if present.
1.10 CSVGN1
Static Shunt Compensator
STATEs # Description
K First regulator
K+1 Second regulator
K+2 Thyristor
VAR # Description
L Y (model output)
ICON # Description
M Memory
+
+ K(1 + sT1) (1 + sT2) 1
|V| X Y
(1 + sT3) (1 + sT4) 1 + sT5
VMIN RMIN/RBASE
Other
Signals
VOTHSG
RBASE = MBASE
Note: |V| is the voltage magnitude on the high side of generator step-up transformer, if present.
1.11 CSVGN3
Static Shunt Compensator
STATEs # Description
K First regulator
K+1 Second regulator
K+2 Thyristor
VAR # Description
L Y (model output)
ICON # Description
M Memory
RBASE = MBASE
Note: |V| is the voltage magnitude on the high side of generator step-up transformer, if present.
1.12 CSVGN4
Static Shunt Compensator
STATEs # Description
K First regulator
K+1 Second regulator
K+2 Thyristor
VAR # Description
L Y (model output)
RBASE = MBASE
1.13 CSVGN5
Static var Compensator
STATEs # Description
K Filter output
K+1 First regulator state
K+2 Second regulator state
K+3 Thyristor delay
VAR # Description
L Y (model output)
Filter VEMAX
1 + 1 + sTS2 1 + sTS4
KSVS
/VOLT(IBUS)/ 1 + sTs1 1 + sTS3 1 + sTS5
or
/VOLT(ICON(M))/ + + VEMAX 1st Stage 2nd Stage
BMAX
VERR
If VERR > DVLO: BR = BMAX + KSD (VERR DV)
BR
If DVHI < VERR < DVLO: BR = BR 1 MBASE(I)
Br 1 + sTS6 B
SVS SBASE VAR(L)
If VERR < DVHI: BR = BMIN
Thyristor Delay
If DV = 0, If DV > 0,
DVLO = BMAX/KSVS DVLO = DV
DVHI = BMIN/KSVS DVHI = DV
1.14 CSVGN6
Static var Compensator
STATEs # Description
K Filter output
K+1 First regulator state
K+2 Second regulator state
K+3 Thyristor delay
VARs # Description
L Y (model output)
L+1 BSHUNT switch timer
Other
Signals
VREF VOTHSG
VMAX VEMAX
Filter + +
1 + 1 + sTS2 1 + sTS4
KSVS BR
VOLT(IBUS) 1 + sTs1 1 + sTS3 1 + sTS5
or
VOLT(ICON(M))
VMIN VEMIN
Position 1 is normal (open).
VERR If VERR > DV2, switch will
close after TDELAY cycles.
BMAX 1 2
BSHUNT
+
If VERR > DVLO: BR = BMAX + KSD (VERR DV)
If DVHI < VERR < DVLO: BR = BR 1 +
BR Y
B R 1 + sTS6
If VERR < DVHI: BR = BMIN
+
Fast Override BMIN
BIAS
Thyristor Delay
If DV = 0, If DV > 0,
DVLO = BMAX/KSVS DVLO = DV
DVHI = BMIN/KSVS DVHI = DV
1.15 FRECHG
Frequency Changer Model
STATEs # Description
K Eq
K+1 kd
K+2 q
K+3 speed (pu)
K+4 Angle (radians)
K+5 Eq
K+6 kd
K+7 q
K+8 speed (pu)
K+9 Angle (radians)
Notes:
From bus unit assumed to be on the same system base frequency as that in the working case.
CON(J) through CON(J+11), STATE(K) through STATE(K+4) are quantities for the from bus unit.
CON(J+12) through CON(J+24), STATE(K+5) through STATE(K+9) are quantities for the to bus
unit.
Xd, Xq, Xd, X, Xq, Xl, H, and D are in pu on the corresponding Machine MVA base. Xq must be
equal to Xd.
H1*MBASE1 = H2*MBASE2
1.16 GENCLS
Constant Internal Voltage Generator Model
J H, Inertia1
J+1 D, Damping constant
1 H and D are in pu machine MVA base.
If H is 0, then DSTATE(K) and DSTATE(K+1) will always be
zero.
STATEs # Description
K speed (pu)
K+1 Angle (radians)
1.17 GENDCO
Round Rotor Generator Model Including dc Offset Torque Component
Note: Xd, Xq, Xd, Xq, Xd, Xq, Xl, H, and D are in pu, machine MVA base.
STATEs # Description
K Eq
K+1 Ed
K+2 kd
K+3 kq
K+4 speed (pu)
K+5 Angle (radians)
VARs # Description
L Telec
L+1 dc offset current
L+2 Phase at switch
L+3 Time of switch
L+4 id, Value at kPAUSE = 1
L+5 iq, Value at kPAUSE = 1
L+6 id
L+7 iq
1.18 GENROE
Round Rotor Generator Model (Exponential Saturation)
Note: Xd, Xq, Xd, Xq, Xd, Xq, Xl, H, and D are in pu, machine MVA base.
STATEs # Description
K Eq
K+1 Ed
K+2 kd
K+3 kq
K+4 speed (pu)
K+5 Angle (radians)
1.19 GENROU
Round Rotor Generator Model (Quadratic Saturation)
Note: Xd, Xq, Xd, Xq, Xd, Xq, Xl, H, and D are in pu, machine MVA base.
STATEs # Description
K Eq
K+1 Ed
K+2 kd
K+3 kq
K+4 speed (pu)
K+5 Angle (radians)
1.20 GENSAE
Salient Pole Generator Model (Exponential Saturation on Both Axes)
Note: Xd, Xq, Xd, Xd, Xq, Xl, H, and D are in pu, machine MVA base.
STATEs # Description
K Eq
K+1 q
K+2 kd
K+3 speed (pu)
K+4 Angle (radians)
1.21 GENSAL
Salient Pole Generator Model (Quadratic Saturation on d-Axis)
Note: Xd, Xq, Xd, Xd, Xq, Xl, H, and D are in pu, machine MVA base.
STATEs # Description
K Eq
K+1 kd
K+2 q
K+3 speed (pu)
K+4 Angle (radians)
1.22 GENTRA
Transient Level Generator Model
Note: Xd, Xq, Xd, H, and D are in pu, machine MVA base.
STATEs # Description
K Eq
K+1 speed (pu)
K+2 Angle (radians)
VAR # Description
L Ed
This chapter contains a collection of data sheets for the compensator models contained in the
PSSE dynamics model library.
Model Description
COMP Voltage regulator compensating model
COMPCC Cross compound compensating model
IEEEVC 1981 IEEE voltage compensating model
REMCMP Remote bus voltage signal model
2.1 COMP
Voltage Regulator Current Compensating Model
This model allows the voltage regulator of machine I to sense the voltage at a point separated from
the machine terminals by an impedance of Xe.
VT VCT
VCT = V T jXe I T
IT ECOMP
2.2 COMPCC
Voltage Regulator Current Compensating Model for Cross-Compound Units
This model allows the voltage regulators of machines I and M to sense the voltage separated from
the machine terminals.
VT
IT1
IT2
I T1 + I T2
E COMP1 = V T --------------------- R 1 + jX 1 + I T1 R 2 + jX 2
2
I T1 + I T2
E COMP2 = V T --------------------- R 1 + jX 1 + I T2 R 2 + jX 2
2
2.3 IEEEVC
Voltage Regulator Current Compensating Model
This model allows the voltage regulator of mMachine I to sense the voltage at a point separated
from the machine terminals by an impedance of RC + jXC.
VT VCT
V V T + R + jX C I T
IT CT C ECOMP
2.4 REMCMP
Voltage Regulator Current Compensating Model
This model allows the voltage regulator of machine ID to sense the voltage at a remote bus.
This chapter contains a collection of data sheets for the stabilizer models contained in the PSSE
dynamics model library.
Model Description
BEPSST Transient excitation boosting stabilizer model
IEE2ST Dual-input signal power system stabilizer model
IEEEST 1981 IEEE power system stabilizer model
IVOST IVO stabilizer model
OSTB2T Ontario Hydro delta-omega power system stabilizer
OSTB5T Ontario Hydro delta-omega power system stabilizer
PSS1A IEEE Std. 421.5-2005 PSS1A Single-Input Stabilizer model
PSS2A 1992 IEEE type PSS2A dual-input signal stabilizer model
PSS2B IEEE 421.5 2005 PSS2B IEEE dual-input stabilizer model
PSS3B IEEE Std. 421.5 2005 PSS3B IEEE dual-input stabilizer model
PSS4B IEEE 421.5(2005) dual-input stabilizer model
PTIST1 PTI microprocessor-based stabilizer model
PTIST3 PTI microprocessor-based stabilizer model
ST2CUT Dual-input signal power system stabilizer model
STAB1 Speed sensitive stabilizer model
STAB2A ASEA power sensitive stabilizer model
STAB3 Power sensitive stabilizer model
STAB4 Power sensitive stabilizer model
STABNI Power sensitive stabilizer model type NI (NVE)
STBSVC WECC supplementary signal for static var system
3.1 BEPSST
Transient Excitation Boosting PSS
J+4 T3 (sec)1
J+8 T7 (sec)
J+9 T8 (sec)
J+10 T9 (sec)
J+11 T10 (sec)
J+12 LSMAX
J+13 LSMIN
J+14 VCU (pu) (if equal zero, ignored)
STATEs # Description
K PSS state 1
K+1 PSS state 2
K+2 PSS state 3
K+3 PSS state 4
K+4 PSS state 5
K+5 PSS state 6
K+6 TEB state 1
K+7 TEB state 2
VARs # Description
L Memory
L+1 Derivative of pu bus voltage (first bus)
L+2 Memory
L+3 Derivative of pu bus voltage (second bus)
L+4 Initial bus voltage (pu)
L+5 RETREAT
L+6 VMAX
T 12
RETREAT = C RT ------------------------
T 12 T 11
K1
Input
Signal #1 1 + sT1
+
sT3 1 + sT5 1 + sT7 1 + sT9
1 + sT4 1 + sT6 1 + sT8 1 + sT10
+
K2
Input Output Limiter
Signal #2 1 + sT2 LSMAX
VS = VSS if VCU + VTO > VT > VCL + VTO
VS = 0 if VT < VTO + VCL +
VSS VOTHSG
VS = 0 if VT > VTO + VCU
+
LSMIN
VMAX =
If VT > VLIMIT
3.2 IEE2ST
IEEE Stabilizing Model With Dual-Input Signals
J+4 T3 (sec)1
J+5 T4 (>0) (sec)
J+6 T5 (sec)
J+7 T6 (sec)
J+8 T7 (sec)
J+9 T8 (sec)
J+10 T9 (sec)
J+11 T10 (sec)
J+12 LSMAX
J+13 LSMIN
J+14 VCU (pu) (if equal zero, ignored.)
J+15 VCL (pu) (if equal zero, ignored.)
1 If T equals 0, sT will equal 1.0.
3 3
STATEs # Description
K First signal transducer
K+1 Second signal transducer
K+2 Washout
K+3 First lead-lag
K+4 Second lead-lag
K+5 Third lead-lag
VARs # Description
L Memory
L+1 Derivative of pu bus voltage, first bus
L+2 Memory
L+3 Derivative of pu bus voltage, second bus
Input K1
Signal #1 1 + sT1
+
sT3 1 + sT5 1 + sT7
1 + sT4 1 + sT6 1 + sT8
+
Input K2
Signal #2 1 + sT2 Output Limiter
LSMAX
VS = VSS if (VCU > VCT > VCL)
1 + sT9
1 + sT10 VS = 0 if (VCT < VCL) VOTHSG
VSS
VS = 0 if (VCT > VCU)
LSMIN
3.3 IEEEST
IEEE Stabilizing Model
J+3 A4
J+4 A5
J+5 A6
J+6 T1 (sec)
J+7 T2 (sec)
J+8 T3 (sec)
J+9 T4 (sec)
J+10 T5 (sec)1
STATEs # Description
K 1st filter integration
K+1 2nd filter integration
K+2 3rd filter integration
K+3 4th filter integration
K+4 T1/T2 lead-lag integrator
K+5 T3/T4 lead-lag integrator
K+6 Last integer
VARs # Description
L Memory
L+1 Derivative of pu bus voltage
Filter
1 + A5s + A6s2
Input 1 + sT1 1 + sT3
Signal (1 + A1s + A2s2) (1 + A3s + A4s2) 1 + sT2 1 + sT4
Output Limiter
LSMAX
VS = VSS, if (VCU > VCT > VCL)
sT5
KS VS = 0, if (VCT < VCL) VOTHSG
1 + sT6 VSS
VS = 0, if (VCT > VCU)
LSMIN
3.4 IVOST
IVO Stabilizer Model
J+4 T2
J+5 MAX1
J+6 MIN1
J+7 K3
J+8 A3
J+9 A4
J+10 T3
J+11 T4
J+12 MAX3
J+13 MIN3
J+14 K5
J+15 A5
J+16 A6
J+17 T5
J+18 T
J+19 MAX5
J+20 MIN5
STATEs # Description
K Integrator 1
K+1 Integrator 2
K+2 Integrator 3
MAX1 MAX3
MAX5
A +T S A +T S A +T S
1 1 3 3 5 5
PELEC K ------------------------ K ------------------------ K ------------------------ VOTHSG
1A + T S 3A + T S 5A + T S
2 2 4 4 6 6
MIN5
MIN1 MIN3
3.5 OSTB2T
Ontario Hydro Delta-Omega Power System Stabilizer
J+18 EFDTHR
J+19 TSEAL
STATEs # Description
K Washout TS block
K+1 Lead-lag T1/T3 block
K+2 Lead-lag T2/T4 block
K+3 TANG block
VARs # Description
L S1
L+1 TSEC duration
L+2 TSEAL duration
VNGMX
VMGMX
KANG
1 + sTANG
0
S1
HLIM + VSMX
K TS 1 + sT1 1 + sT2 +
VOTHSG
1 + sTS 1 + sT3 1 + sT4
Speed
LLIM VSMN
(pu)
Notes:
1. S1 normally open.
2. S1 closes if Et < ETHR and >THR or > THR within TSEAL seconds of last
time Et < ETHR.
4. S1 opens if:
a. <THR, or
b. EFD < EFDTHR, or
c. after being closed for T-OFF seconds.
5. Once open, stays open.
3.6 OSTB5T
Ontario Hydro Delta-Omega Power System Stabilizer
J+3 T2(sec)
J+4 T3/T4
J+5 T4 (>0) (sec)
J+6 HLIM
J+7 LLIM
J+8 KANG (>0)
J+9 TANG
J+10 VNGMX
J+11 VMGMX
J+12 T-ON
J+13 T-OFF
J+14 VSMX
J+15 VSMN
J+16 THR
J+17 ETHR
J+18 EFDTHR
J+19 TSEAL
STATEs # Description
K Washout TS block
K+1 Quadratic lead-lag block
K+2 Quadratic lead-lag block
K+3 TANG block
VARs # Description
L S1
L+1 TSEC duration
L+2 TSEAL duration
VNGMX
VMGMX
KANG
1 + sTANG
0
S1
HLIM + VSMX
K TS 1 + sT1 1 + sT2 +
VOTHSG
1 + sTS 1 + sT3 1 + sT4
Speed
LLIM VSMN
(pu)
Notes:
1. S1 normally open.
2. S1 closes if Et < ETHR and >THR or > THR within TSEAL seconds of last
time Et < ETHR.
4. S1 opens if:
a. <THR, or
b. EFD < EFDTHR, or
c. after being closed for T-OFF seconds.
5. Once open, stays open.
3.7 PSS1A
IEEE Std. 421.5-2005 PSS1A Single-Input Stabilizer Model
The PSSE model IEEEST can be used to simulate the PSS1A model. The correspondence
between the IEEEST model CONs and the PSS1A parameters (shown in the block) diagram are as
given in the table below.
PSS1A parameter
CONs IEEEST CON
(as shown in the PSS1A block diagram)
J A1 A1
J+1 A2 A2
J+2 A3 TR
J+3 A4 0.0
J+4 A5 0.0
J+5 A6 0.0
J+6 T1 T1
J+7 T2 T2
J+8 T3 T3
J+9 T4 T4
J+10 T5 Tw
J+11 T6 Tw
J+12 KS KS
J+13 LSMAX VSTMAX
J+14 LSMIN VSTMIN
J+15 VCU 0.0
J+16 VCL 0.0
IBUS, IEEEST, ID, ICON(M), ICON(M+1), CON(J) to CON(J+16) /
3.8 PSS2A
IEEE Dual-Input Stabilizer Model
J+5 T7
J+6 KS2
J+7 KS3
J+8 T8
J+9 T9 (>0)
J+10 KS1
J+11 T1
J+12 T2
J+13 T3
J+14 T4
J+15 VSTMAX
J+16 VSTMIN
STATEs # Description
K Washout, first signal
K+1 Washout, first signal
K+2 Transducer, first signal
K+3 Washout, second signal
K+4 Washout, second signal
K+5 Transducer, second signal
K+6
.
. Ramp Tracking Filter
.
K+13
K+14 First lead-lag
K+15 Second lead-lag
VARs # Description
L Memory
L+1 Derivative of pu bus voltage, first bus
L+2 Memory
L+3 Derivative of pu bus voltage, second bus
Model Notes:
M 0
N 0
M N 8
If M = 0, then N is set equal to 0
To bypass: set M = N = 0
Washouts
Transducers
Lead-Lags
VSTMAX
N
sTw1 sTw2 1 + 1 + sT8 + 1 + sT1 1 + sT3
Input 1 + sTw1 1 + sTw2 KS1 VOTHSG
1 + sT6
Signal #1 (1 + sT9)M 1 + sT2 1 + sT4
+
VSTMIN
KS3
3.9 PSS2B
IEEE 421.5 2005 PSS2B IEEE Dual-Input Stabilizer Model
J+3 Tw3
J+4 Tw4
J+5 T7
J+6 KS2
J+7 KS3
J+8 T8
J+9 T9 (> 0)
J+10 KS1
J+11 T1
J+12 T2
J+13 T3
J+14 T4
J+15 T10
J+16 T11
J+17 VS1MAX
J+18 VS1MIN
J+19 VS2MAX
J+20 VS2MIN
J+21 VSTMAX
J+22 VSTMIN
STATEs # Description
K Washout-first signal
K+1 Washout-first signal
K+2 Transducer-first signal
K+3 Washout-second signal
K+4 Washout-second signal
K+5 Transducer-second signal
K+6
.
. Ramp tracking filter
.
K+13
K+14 First lead-lag
K+15 Second lead-lag
K+16 Third lead-lag
VARs # Description
L Memory
L+1 Derivative of pu bus voltage-first bus
L+2 Memory
L+3 Derivative of pu bus voltage-second bus
3.10 PSS3B
IEEE Std. 421.5 2005 PSS3B IEEE Dual-Input Stabilizer Model
J+9 A3
J+10 A4
J+11 A5
J+12 A6
J+13 A7
J+14 A8
J+15 VSTMAX (pu), stabilizer output maximum limit
STATEs # Description
K Time lead block (first signal)
K+1 Time lead block (second signal)
K+2 First signal washout
K+3 Second signal washout
K+4 Washout block
K+5
First two-order block
K+6
K+7
Second two-order block
K+8
3.11 PSS4B
IEEE 421.5(2005) Dual-Input Stabilizer Model
J+1 DL-I
J+3 BL-I
J+4 BL-I1
J+5 L-I1
J+6 BL-I2
J+7 L-I2
J+8 TH (>0)
J+9 AH (>0)
J+10 BH
J+11 M
J+12 BH1
J+13 H1
J+14 BH2
J+15 H2
J+16 KL1
J+17 KL11
J+18 TL1
J+19 TL2
J+20 TL3
J+21 TL4
J+22 TL5
J+23 TL6
J+25 KL17
J+26 TL7
J+27 TL8
J+28 TL9
J+29 TL10
J+30 TL11
J+31 TL12
J+32 KL
J+33 VLmax
J+34 VLmin
J+35 KI1
J+36 KI11
J+37 TI1
J+38 TI2
J+39 TI3
J+40 TI4
J+41 TI5
J+42 TI6
J+43 KI2
J+44 KI17
J+45 TI7
J+46 TI8
J+47 TI9
J+48 TI10
J+49 TI11
J+50 TI12
J+51 KI
J+52 VImax
J+53 VImin
J+54 KH1
J+56 TH1
J+57 TH2
J+58 TH3
J+59 TH4
J+60 TH5
J+61 TH6
J+62 KH2
J+63 KH17
J+64 TH7
J+65 TH8
J+66 TH9
J+67 TH10
J+68 TH11
J+69 TH12
J+70 KH
J+71 VHmax
J+72 VHmin
J+73 VSTmax
J+74 VSTmin
STATEs # Description
K
First signal transducer
K+1
K+2
First notch filter (first signal)
K+3
K+4
Second notch filter (first signal)
K+5
K+6
K+7 Second signal transducer
K+8
K+9 Time lag block (second signal)
STATEs # Description
K+10
First Notch filter (second signal)
K+11
K+12
Second notch filter (second signal)
K+13
K+14 Lead-lag (low frequency, part 1)
K+15 Lead-lag (low frequency, part 1)
K+16 Lead-lag (low frequency, part 1)
K+17 Lead-lag (low frequency, part 2)
K+18 Lead-lag (low frequency, part 2)
K+19 Lead-lag (low frequency, part 2)
K+20 Lead-lag (medium frequency, part 1)
K+21 Lead-lag (medium frequency, part 1)
K+22 Lead-lag (medium frequency, part 1)
K+23 Lead-lag (medium frequency, part 2)
K+24 Lead-lag (medium frequency, part 2)
K+25 Lead-lag (medium frequency, part 2)
K+26 Lead-lag (high frequency, part 1)
K+27 Lead-lag (high frequency, part 1)
K+28 Lead-lag (high frequency, part 1)
K+29 Lead-lag (high frequency, part 2)
K+30 Lead-lag (high frequency, part 2)
K+31 Lead-lag (high frequency, part 2)
VARs # Description
L L-I
L+1 H
L+2 VL
L+3 VI
L+4 VH
3.12 PTIST1
PTI Microprocessor-Based Stabilizer
J+10 T3
J+11 T4
VARs # Description
L from EQ
L+1 Pe average
L+2 Vdl
L+3 Vql
L+4
L+5 States for transfer
L+6
L+7 Function
L+8 Tap setting
L+9 Pe last
ICONs # Description
Number of time steps to activate frequency
M
calculation
Number of time steps to activate power
M+1
calculation
M+2 Number of time steps to activate controls
+
+ PM K(1 + sT1) (1 + sT3) Tap
Ms +
Selection X VOTHSG
1 + sTF (1 + sT2) (1 + sT4) Table
+
Et
1 Pe on MBASE base
1 + sTP
M = 2. H
TF = TP 0.2 sec
K = 1 to 10, depends on tuning
T1 = 0.1 to 0.5, depends on tuning
T2 = 1 to 3 sec
T3 = 0.1 to 0.5, depends on tuning
T4 = 0.05 sec
tF = tC = 0.025 sec
tP = 0.0125 sec
3.13 PTIST3
PTI Microprocessor-Based Stabilizer
J+1 tP
J+2 tC
J+3 Xq
J+4 M
J+5 TP > 0
J+6 TF > 0
J+7 K
J+8 T1
J+9 T2 > 0
J+10 T3
J+11 T4 >0
J+12 T5
J+13 T6 (see Note 1)
J+14 A0
J+15 A1
J+16 A2
J+17 B0
J+18 B1
J+19 B2 (see Note 2)
J+20 A3
J+21 A4
J+22 A5
J+27 DL
J+28 AL
J+29 LTHRES (see Note 4)
J+30 PMIN (see Note 6)
VARs # Description
L from EQ
L+1 Pe average
L+2 Vdl
L+3 Vql
L+4 Frequency filter state or store
L+5 Power filter state or store
L+6 1st lead/lag state or store
L+7 2nd lead/lag state or store
L+8 Tap setting or analog output
L+9 PELAST
L+10 3rd lead/lag state or store
L+11 Torsional filter store
L+12 Torsional filter store
L+13 Torsional filter store
L+14 Torsional filter store
L+15 Frequency filter output
L+16 Power filter output
L+17 1st lead/lag output
L+18 2nd lead/lag output
L+19 3rd lead/lag output
L+20 1st stage torsional filter output
L+21 2nd stage torsional filter output
VARs # Description
L+22
.
. Output averaging table
.
L+37
L+38 Output accumulator
L+39 Analog ramp
Optional Features:
1. Third Lead/Lag
To disable: set T6 = 0
If enabled: T6 > 0
2. Torsional Filter
Ms + + K(1 + sT1) (1 + sT3) 1 + sT5 (A0 + A1s + A2s2) (A3 + A4s + A5s2)
1 + sTF PM (1 + sT2) (1 + sT4) 1 + sT6 (B0 + B1s + B2s2) (B3 + B4s + B5s2)
+
1 VAR(L+1)
1 + sTP Pe average
1 Et
DL
+
ICON(M)=0 Tap
Selection X
Table
Averaging Limit VOTHSG
Function Function DL
AL
ICON(M)=1
AL
3.14 ST2CUT
Stabilizing Model With Dual-Input Signals
J+3 T2 (sec)
J+4 T3 (sec)1
J+5 T4 (>0) (sec)
J+6 T5 (sec)
J+7 T6 (sec)
J+8 T7 (sec)
J+9 T8 (sec)
J+10 T9 (sec)
STATEs # Description
K First signal transducer
K+1 Second signal transducer
K+2 Washout
K+3 First lead-lag
K+4 Second lead-lag
K+5 Third lead-lag
VARs # Description
L Memory
L+1 Derivative of pu bus voltage, first bus
L+2 Memory
L+3 Derivative of pu bus voltage, second bus
L+4 Initial bus voltage (pu)
K1
Input
Signal #1 1 + sT1
+
sT3 1 + sT5 1 + sT7 1 + sT9
1 + sT4 1 + sT6 1 + sT8 1 + sT10
+
K2
Input
Signal #2 1 + sT2
Output Limiter
LSMAX
VS = VSS if VCU + VTO > VT > VCL + VTO
VS = 0 if VT < VTO + VCL VOTHSG
VSS
VS = 0 if VT > VTO + VCU
LSMIN
VT is the terminal voltage at bus IBUS.
VTO is the initial terminal voltage at bus IBUS.
3.15 STAB1
Speed Sensitive Stabilizing Model
J K/T (sec)-1
J+1 T (sec) (>0)
J+2 T1/T3
J+3 T3 (sec) (>0)
J+4 T2/T4
J+5 T4 (sec) (>0)
J+6 HLIM
STATEs # Description
K Washout
K+1 First lead-lag
K+2 Second lead-lag
HLIM
-HLIM
3.16 STAB2A
Power Sensitive Stabilizing Unit (ASEA)
J+4 K4
J+5 K5
J+6 T5 (sec) (>0)
J+7 HLIM
STATEs # Description
K Implicit
K+1 Integration
K+2 State
K+3 Variables
K3
1 + sT3 HLIM
+
Machine
Electrical K5 2
K 2 sT 2 3
Power on ------------------ ------------------ VOTHSG
MBASE 1 + sT2 1 + sT 5
Base + -HLIM
K4
3.17 STAB3
Power Sensitive Stabilizing Unit
STATEs # Description
K First time constant output
K+1 Second time constant output
K+2 Unlimited signal
VAR # Description
L Power reference signal
Pref = VAR(L)
VLIM
Machine
Electrical 1 + 1 -sKX
Power on VOTHSG
1 + sTt 1 + sTX1 1 + sTX2
MBASE
VLIM
3.18 STAB4
Power Sensitive Stabilizer
J+4 Ta (sec)
J+5 Tb (sec)
J+6 Tc (sec) (>0)
J+7 Td (sec)
J+8 Te (sec)
J+9 L1 (pu) low limit
J+10 L2 (pu) high limit
STATEs # Description
K Transducer output
K+1 Reset state
K+2 1st lead lag
K+3 2nd lead lag
K+4 5th state
K+5 Unlimited signal
VAR # Description
L Initial electrical power
Pref = VAR(L)
Limiter
Machine
Electrical + sKX 1 + sTa 1 + sTb 1 1 L2
1
Power on VOTHSG
1 + sTT 1 + sTX2 1 + sTX1 1 + sTc 1 + sTd 1 + sTe L1
MBASE
Base
3.19 STABNI
Power Sensitive Stabilizer Model Type NI (NVE)
STATEs # Description
K Filter
K+1 Filter
K+2 Filter
K+3 Filter
K+4 Output
+ LIMIT
2
K 1 + T ST S
-------------------- 1 0
PELEC(I) -------------------------------------------- 1 VOTHSG(I)
1+T S 4
2 1 + T S
0
LIMIT
3.20 STBSVC
WECC Supplementary Signal for Static var Compensator
J+8 KS2
J+9 TS10 (sec)
J+10 TS11 (sec)
J+11 TS12 (>0, if KS2 0) sec
STATEs # Description
K Filter for signal (1)
K+1 Lead-lag for signal (1)
K+2 Filter for signal (2)
K+3 Lead-lag for signal (2)
Wash out with time constant for both
K+4
signals
VAR # Description
L MW flow-through branch
KS1 1 + sTS8
Signal 1
1 + sTS7 1 + sTS9 VSCS
+
sTS13
KS3 VOTHSG
1 + sTS14
+
KS2 1 + sTS11 VSCS
Signal 2
1 + sTS10 1 + sTS12
Model Description
MNLEX1 Minimum excitation limiter model
MNLEX2 Minimum excitation limiter model
MNLEX3 Minimum excitation limiter model
UEL1 IEEE 421.5 2005 UEL1 under-excitation limiter
UEL2 IEEE 421.5 2005 UEL2 minimum excitation limiter
4.1 MNLEX1
Minimum Excitation Limiter
EFD
STATEs # Description
K MEL feedback integrator
K+1 MEL
VAR # Description
L PQSIG
MELMAX
+ KM + sKF2
IREAL EFD
PQSIG 1 + sTM 1 + sTF2
0 VUEL
1
K
XADIFD
4.2 MNLEX2
Minimum Excitation Limiter
STATEs # Description
K MEL feedback integrator
K+1 MEL
VAR # Description
L PQSIG
4.3 MNLEX3
Minimum Excitation Limiter
STATEs # Description
K MEL feedback integrator
K+1 MEL
VAR # Description
L PQSIG
Q
VT MELMAX
-
Qo + + + KM
VUEL Q/V
(1.0 pu) PQSIG 1 + sTM
+
0
sKF2
B
1 + sTF2 P/V
P Qo B = Slope
EFD (1.0 pu V)
VT
4.4 UEL1
IEEE 421.5 2005 UEL1 Under-Excitation Limiter
STATEs # Description
K Integrator
K+1 First lead-lag
K+2 Second lead-lag
VARs # Description
L Reference input signal
L+1 VUC
L+2 VUR
L+3 VUerr
IBUS, UEL1, ID, CON(J) to CON(J+14) /
4.5 UEL2
IEEE 421.5 2005 UEL2 Minimum Excitation Limiter
STATEs # Description
K Voltage filter output
K+1 Real power filter output
K+2 Reactive power filter output
K+3 Integrator
K+4 Reference feedback block
K+5 First lead-lag
K+6 Second lead-lag
VARs # Description
L Reference input signal
L+1 Q, normalized reactive power output for 1 pu voltage
L+2 QREF
Model Description
MAXEX1 Maximum excitation limiter model
MAXEX2 Maximum excitation limiter model
5.1 MAXEX1
Maximum Excitation Limiter
J+8 KMX
J+9 VLOW
VAR # Description
K Contact position
EFDDES * EFDRATED
+
0
KMX VOEL
EFD
VLOW
(EFD1, TIME1)
Time (sec)
(EFD2, TIME2)
(EFD3, TIME3)
5.2 MAXEX2
Maximum Excitation Limiter
J+8 KMX
J+9 VLOW (< 0)
VAR # Description
K Contact position
STATE # Description
L Reset integrator
EFDDES or IFDDES 0.
+
EFD KMX
or IFD VOEL
S
VLOW
(EFD1, TIME1)
or
(IFD1, TIME1)
Time (sec)
(EFD2, TIME2)
or
(IFD2, TIME2)
(EFD3, TIME3)
or
(IFD3, TIME3)
This chapter contains a collection of data sheets for the excitation system models contained in the
PSSE dynamics model library.
Model Description
AC7B IEEE 421.5 2005 AC7B excitation system
AC8B IEEE 421.5 2005 AC8B excitation system
BBSEX1 Brown-Boveri static excitation system model
BUDCZT Czech proportional/integral excitation system model
CELIN ELIN brushless excitation system model
DC3A IEEE 421.5 2005 DC3A excitation system
DC4B IEEE 421.5 2005 DC4B excitation system
EMAC1T AEP Rockport excitation system model
ESAC1A 1992 IEEE type AC1A excitation system model
ESAC2A 1992 IEEE type AC2A excitation system model
ESAC3A 1992 IEEE type AC3A excitation system model
ESAC4A 1992 IEEE type AC4A excitation system model
ESAC5A 1992 IEEE type AC5A excitation system model
ESAC6A 1992 IEEE type AC6A excitation system model
ESAC8B Basler DECS model
ESDC1A 1992 IEEE type DC1A excitation system model
ESDC2A 1992 IEEE type DC2A excitation system model
ESST1A 1992 IEEE type ST1A excitation system model
ESST2A 1992 IEEE type ST2A excitation system model
ESST3A 1992 IEEE type ST3A excitation system model
IEEE type ST4B potential or compounded source-controlled rectifier
ESST4B
exciter
ESURRY Modified IEEE Type AC1A excitation model
EX2000 EX2000 Excitation System
Model Description
EXAC1 1981 IEEE type AC1 excitation system model
EXAC1A Modified type AC1 excitation system model
EXAC2 1981 IEEE type AC2 excitation system model
EXAC3 1981 IEEE type AC3 excitation system model
EXAC4 1981 IEEE type AC4 excitation system model
EXBAS Basler static voltage regulator feeding dc or ac rotating exciter model
EXDC2 1981 IEEE type DC2 excitation system model
EXELI Static PI transformer fed excitation system model
Bus or solid fed SCR bridge excitation system model type NEBB
EXNEBB
(NVE)
EXNI Bus or solid fed SCR bridge excitation system model type NI (NVE)
EXPIC1 Proportional/integral excitation system model
EXST1 1981 IEEE type ST1 excitation system model
EXST2 1981 IEEE type ST2 excitation system model
EXST2A Modified 1981 IEEE type ST2 excitation system model
EXST3 1981 IEEE type ST3 excitation system model
IEEET1 1968 IEEE type 1 excitation system model
IEEET2 1968 IEEE type 2 excitation system model
IEEET3 1968 IEEE type 3 excitation system model
IEEET4 1968 IEEE type 4 excitation system model
IEEET5 Modified 1968 IEEE type 4 excitation system model
1979 IEEE type 1 excitation system model and 1981 IEEE type DC1
IEEEX1
model
IEEEX2 1979 IEEE type 2 excitation system model
IEEEX3 1979 IEEE type 3 excitation system model
1979 IEEE type 4 excitation system, 1981 IEEE type DC3 and 1992
IEEEX4
IEEE type DC3A models
IEET1A Modified 1968 IEEE type 1 excitation system model
IEET1B Modified 1968 IEEE type 1 excitation system model
IEET5A Modified 1968 IEEE type 4 excitation system model
IEEX2A 1979 IEEE type 2A excitation system model
IVOEX IVO excitation system model
Ontario Hydro IEEE Type ST1 excitation system with continuous and
OEX12T
bang bang terminal voltage limiter
Ontario Hydro IEEE Type ST1 excitation system with semicontinuous
OEX3T
and acting terminal voltage limiter
REXSYS General purpose rotating excitation system model
Model Description
REXSY1 General purpose rotating excitation system model
SCRX Bus or solid fed SCR bridge excitation system model
SEXS Simplified excitation system model
ST5B IEEE 421.5 2005 ST5B excitation system
ST6B IEEE 421.5 2005 ST6B excitation system
ST7B IEEE 421.5 2005 ST7B excitation system
URHIDT High dam excitation system model
URST5T IEEE proposed type ST5B excitation system
6.1 AC7B
IEEE 421.5 2005 AC7B Excitation System
J+11 KP (pu)1
J+12 KL (pu)
J+13 KF1 (pu)
J+14 KF2 (pu)
STATEs # Description
K Sensed Vt
K+1 Integral channel 1
K+2 Derivative channel 1
K+3 Integral channel 2
K+4 VE
K+5 Rate feedback
VARs # Description
L VR
L+1 VA
6.2 AC8B
IEEE 421.5 2005 AC8B Excitation System
STATEs # Description
K Sensed Vt
K+1 Integral channel PID
K+2 Derivative channel PID
K+3 VR
K+4 VE
VARs # Description
L VPID
L+1 FEX
L+2 VEMAX
6.3 BBSEX1
Brown Boveri Static Exciter
VOEL
J+4 T3 (sec)
J+5 T4 (sec)
J+6 VRMAX
J+7 VRMIN
J+8 EFDMAX
J+9 EFDMIN
J+10 Switch
STATEs # Description
K Sensed VT
K+1 Lead lag
K+2 Regulator feedback
VREF
+ VRMAX VT*EFDMAX
1 1 + sT3 T EFD
EC + 2 +
K ------ (pu)
(pu) 1 + sTF 1 + sT4 T
1
+ + VRMIN + V *EFD
T MIN
T
1- ------
1 1 ------------------
1 -
---
KT 1 + sT
2 2
0 Switch = 0
6.4 BUDCZT
Czech Proportion/Integral Exciter
STATEs # Description
K Transducer
K+1 PI regulator
K+2 Actuator
K+3 Exciter
VAR # Description
L Actuator input UREG
Regulator
VREF
Measuring KP
Transducer + +
1 URMAX URMAX
ECOMP UREG
1 + sTR
URMIN
+ + Actuator
1
VS sT1
EFDMAX
Exciter
URMIN
KA KE
VAR EFD
1 + sTA 1 + sTE
6.5 CELIN
ELIN Excitation System
J+2 TR3
J+3
J+4
J+5 TE2
J+6 Nominal full load EFD in IEEE pu1
J+7 KE2
J+8 TR4
J+9 T1
J+10 T2
J+11 T3
J+12 T4
J+13 T5
J+14 T6
J+15 K12
J+16 K2
J+17 p_PSS
J+18 a_PSS
J+19 Psslim
J+20 K1
J+21 KIEC
J+22 KD1
J+23 TB1 (>0)
J+24 T11
J+32 T13
J+33 K4
J+34 T14
J+35 KETB
J+36 TE
J+37 Xp
STATEs # Description
K Sensed Vt
K+1 Uw
K+2 Ub
K+3 Efd
K+4 Sensed lef
K+5 PSS_first lag
K+6 PSS_second lag
K+7 PSS_first washout
K+8 PSS_second washout
K+9 PSS_third washout
STATEs # Description
K+10 PSS_third lag
K+11 PID1_rate-lag
K+12 PID1_integrator
K+13 Spare
K+14 PID3_integrator
K+15 PID4_integrator
K+16 Converter_lag
VARs # Description
L IEF, pu
L+1 IEF_REF, pu
0 p_PSS 2
2 p_PSS 4
THYRISTOR CONVERTER
1ef min ref Vt Up+
Up+
+
1efref + Vr 1 + Vef
K2 KETB
1 + sTE
1ef '
+
Up- XP
1ef max 1 ref Vt Up Ief
XP
+3.56KIEC
1
sT13
0
+ +3.56KIEC
+ + BRUSHLESS EXCITATION
1ef min K3 1ef min ref
1ef ' 0
EXCITER FIELD CURRENT MAXIMUM LIMITER + 1
sTE2
Efd
+0
1
sT14 SE + KE2
Ief
3.56KIEC
+ +0
1ef max 1 + +
K4 1ef max 1 ref
1ef '
3.56KIEC
Ief 1
1 + sTR4
DT02_004
6.6 DC3A
IEEE 421.5 2005 DC3A Excitation System
STATEs # Description
K Sensed Ecomp
K+1 Rheostat setting
K+2 Exciter (EFD)
VARs # Description
L VERR
L+1 VR
6.7 DC4B
IEEE 421.5 2005 DC4B Excitation System
J+15 SE(E1)
J+16 E2 (pu)
J+17 SE(E2)
STATEs # Description
K Sensed VT
K+1 Integral channel
K+2 Derivative Channel
K+3 VR
K+4 EFD
K+5 Rate feedback
VARs # Description
L VPID
L+1 KE
6.8 EMAC1T
Modified IEEE Type AC1 Excitation System
(AEP Rockport Excitation Model)
J+2 T3 (sec)
J+3 KA
J+4 TA (sec)
J+5 VRMAX
J+6 VRMIN
J+7 TE > 0 (sec)
J+8 KF
STATEs # Description
K Sensed ET
K+1 2nd lead lag output
K+2 3rd lead lag output
K+3 Regulator output, VR
K+4 VE
K+5 Feedback output, VF
K+6 1st lead lag output
K+7 Rate feedback output
VARs # Description
L Feedback output, VF
L+1 2nd summer output
L+2 3rd lead lag output
L+3 VFE
L+4 2nd lead lag output
L+5 1st lead lag output
L+6 Rate feedback output
VREF VS
VRMAX
+ +
1 1 + sT1 1 + sT3 1 + sT5 KA VE
+ +
1
EC 1 + sTA VR EFD
(pu) 1 + sTR 1 + sT2 VC 1 + sT4 1 + sT6 sTE
0 FEX
Front End Filter PI Filter VRMIN
FEX = f(IN)
sKFE
VF VFE
1 + sTFE IN
Rate Feedback
+ Loop
sKF + KCIFD
KE + SE IN =
1 + sTF VFE VE
+
KD IFD
6.9 ESAC1A
IEEE Type AC1A Excitation System
VOEL
J+1 TB (sec)
J+2 TC (sec)
J+3 KA
J+4 TA (sec)
J+5 VAMAX
J+6 VAMIN
J+7 TE > 0 (sec)
J+8 KF
J+9 TF > 0 (sec)
J+10 KC
J+11 KD
J+12 KE
J+13 E1
J+14 SE(E1)
J+15 E2
J+16 SE(E2)
J+17 VRMAX
J+18 VRMIN
STATEs # Description
K Sensed ET
K+1 Lead lag
K+2 Regulator output
K+3 VE
K+4 Feedback output
VOTHSG
VAMAX
VUEL
+ VRMAX
EC 1 1 + sTC KA + VE EFD
1 + sTR HV
Gate
LV
Gate 1
(pu) 1 + sTB 1 + sTA VR sTE
+ VRMIN FEX
VAMIN 0
VREF VOEL
FEX = f(IN)
VX = VE SE (VE)
VX
VF + IN
+
KE KCIFD
IN =
+ VE
sKF
1 + sTF
VFE
+
KD IFD
If I 0 F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
If 0.433 < I < 0.75 F = 0.75 I 2
IN N EX N FEX
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.10 ESAC2A
IEEE Type AC2A Excitation System
J+4 TA (sec)
J+5 VAMAX
J+6 VAMIN
J+7 KB
J+8 VRMAX
J+9 VRMIN
J+10 TE > 0 (sec)
J+11 VFEMAX
J+12 KH
J+13 KF
STATEs # Description
K Sensed ET
K+1 Lead lag
K+2 Regulator output
K+3 VE
K+4 Feedback output
VFEMAX KDIFD
VOTHSG VUEL KE + SE(VE)
VAMAX
+ VRMAX
1 + sTC KA + + VE
EC 1 HV LV 1
1 + sTB 1 + sTA V KB Gate Gate EFD
(pu) 1 + sTR A VR sTE
+ VRMIN FEX
VREF VAMIN VOEL 0
FEX = f(IN)
VX = VE SE (VE)
VX
+ IN
VF VH
+ KCIFD
KE
IN =
+ VE
KH
sKF VFE +
KD IFD
1 + sTF
ESAC2A
6-29
Excitation System Model Data Sheets PSSE 32.0.5
ESAC3A
PSS E Model Library
6.11 ESAC3A
IEEE Type AC3A Excitation System
J+2 TC (sec)
J+3 KA
J+4 TA (sec)
J+5 VAMAX
J+6 VAMIN
J+7 TE > 0 (sec)
J+8 VEMIN
J+9 KR (>0)
J+10 KF
J+11 TF > 0 (sec)
J+12 KN
J+13 EFDN
J+14 KC
J+15 KD
J+16 KE
J+17 VFEMAX
J+18 E1
J+19 SE(E1)
J+20 E2
J+21 SE(E2)
STATEs # Description
K Sensed ET
K+1 Lead lag
K+2 Regulator output
K+3 VE
K+4 Feedback output
KR
VFEMAX - KD IFD
VS VUEL VAMAX KE + S E (VE)
+
1 + sTC + KA VE
1 HV + 1
1 + sTA V
EC EFD
(pu) 1 + sTR VC 1 + sTB Gate sTE
A VR
+ FEX
VAMIN VEMIN
VREF
VFE FEX = f(IN)
VX = VE SE (VE)
VX
+ IN
VF + +
KE KCIFD
IN =
+ VE
KD IFD
VN
s KN
VS = VOTHSG + VOEL 1 + sTF VN KF
EFD
EFDN
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
If 0.433 < I < 0.75 F = 0.75 I 2
IN N EX N FEX
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.12 ESAC4A
IEEE Type AC4A Excitation System
J+2 VIMIN
J+3 TC
J+4 TB (sec)
J+5 KA
J+6 TA
J+7 VRMAX
J+8 VRMIN
J+9 KC
STATEs # Description
K Vmeasured
K+1 Lead lag
K+2 VR
VS = VOTHSG + VOEL
6.13 ESAC5A
IEEE Type AC5A Excitation System
J+1 KA
J+2 TA (sec)
J+3 VRMAX or zero
J+4 VRMIN
J+5 KE or zero
J+6 TE > 0 (sec)
J+7 KF
J+8 TF1 > 0 (sec)
J+9 TF2 (sec)
J+10 TF3 (sec)
J+11 E1
J+12 SE(E1)
J+13 E2
J+14 SE(E2)
STATEs # Description
K Sensed VT
K+1 Regulator output, VR
K+2 Exciter output, EFD
K+3 First feedback integrator
K+4 Second feedback integrator
VAR # Description
L KE
VS
VRMAX
+
1 KA + 1
EC EFD
(pu) 1 + sTR 1 + sTA sTE
+
VREF VRMIN 0
+ KE
sKF (1 + sTF3)
(1 + sTF1)(1 + sTF2)
VX +
If TF2 = 0, then sTF3 = 0 VX = EFD*SE (EFD)
VS = VOTHSG + VUEL + VOEL
6.14 ESAC6A
IEEE Type AC6A Excitation System
J+3 TK (sec)
J+4 TB (sec)
J+5 TC (sec)
J+6 VAMAX
J+7 VAMIN
J+8 VRMAX
J+9 VRMIN
J+10 TE (>0) (sec)
J+11 VFELIM
J+12 KH
J+13 VHMAX
J+14 TH (sec)
J+15 TJ (sec)
J+16 KC
J+17 KD
J+18 KE
J+19 E1
J+20 SE(E1)
J+21 E2
J+22 SE(E2)
STATEs # Description
K Sensed ET
K+1 First block
K+2 Lead lag
K+3 VE
K+4 Feedback
VS V
UEL VAMAX
+ VT VRMAX
+ 1 + sTC +
1 KA(1 + sTK) + 1 VE
EC EFD
1 + sTR VC (1 + sTA) 1 + sTB VA VR sTE
+
VT VRMIN
VAMIN 0
VREF
FEX = f(IN)
VX = VE SE (VE)
VX
+
+ KE
VHMAX KCIFD
+ IN =
(1 + sTJ) + VE
KH
(1 + sTH) VH VFE
+ KD
0 IFD
VS = VOTHSG + VOEL VFELIM
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.15 ESAC8B
Basler DECS
J+3 KD
J+4 TD (sec)
J+5 KA
J+6 TA
J+7 VRMAX or zero
J+8 VRMIN
J+9 TE > 0 (sec)
J+10 KE or zero
J+11 E1
J+12 SE(E1)
J+13 E2
J+14 SE(E2)
STATEs # Description
K Sensed VT
K+1 Integral controller
K+2 Derivative controller
K+3 Voltage regulator
K+4 Exciter output, EFD
VAR # Description
L KE
VREF KP
VRMAX
+ +
1 KI + KA + 1
EFD
VC 1 + sTR s 1 +sTA VR sTE
+ +
sKD VRMIN 0
VS 1 + sTD +
KE
VX +
VS = VOTHSG + VUEL + VOEL VX = EFD SE (EFD)
6.16 ESDC1A
IEEE Type DC1A Excitation System
J+1 KA
J+2 TA (sec)
J+3 TB (sec)
J+4 TC (sec)
J+5 VRMAX or zero
J+6 VRMIN
J+7 KE or zero
J+8 TE (>0) (sec)
J+9 KF
J+10 TF1 (>0) (sec)
J+11 Switch
J+12 E1
J+13 SE(E1)
J+14 E2
J+15 SE(E2)
STATEs # Description
K Sensed VT
K+1 Lead lag
K+2 Regulator output, VR
K+3 Exciter output, EFD
K+4 Rate feedback integrator
VAR # Description
L KE
VS VUEL VRMAX
+
1 1 + sTC HV KA
EC + 1
1 + sTR VC Gate 1 + sTA EFD
(pu) 1 + sTB VR sTE
+
VREF VRMIN VFE 0
+
VF KE
+
VX = EFD SE (EFD)
sKF
1 + sTF1
VS = VOTHSG + VOEL
6.17 ESDC2A
IEEE Type DC2A Excitation System
J+1 KA
J+2 TA (sec)
J+3 TB (sec)
J+4 TC (sec)
J+5 VRMAX or zero
J+6 VRMIN
J+7 KE or zero
J+8 TE (>0) (sec)
J+9 KF
J+10 TF1 (>0) (sec)
J+11 Switch
J+12 E1
J+13 SE(E1)
J+14 E2
J+15 SE(E2)
STATEs # Description
K Sensed VT
K+1 Lead lag output
K+2 Regulator output, VR
K+3 Exciter output, EFD
K+4 Rate feedback integrator
VAR # Description
L KE
VS VUEL VTVRMAX
+
1 1 + sTC HV KA + 1
EC
(pu) 1 + sTR VC Gate EFD
1 + sTB 1 + sTA VR sTE
+
VREF VTVRMIN VFE
VF + KE
+
VX
VX = EFD SE (EFD)
sKF
1 + sTF
VS = VOTHSG + VOEL
6.18 ESST1A
IEEE Type ST1A Excitation System
J+1 VIMAX
J+2 VIMIN
J+3 TC (sec)
J+4 TB (sec)
J+5 TC1 (sec)
J+6 TB1 (sec)
J+7 KA
J+8 TA (sec)
J+9 VAMAX
J+10 VAMIN
J+11 VRMAX
J+12 VRMIN
J+13 KC
J+14 KF
J+15 TF > 0 (sec)
J+16 KLR
J+17 ILR
STATEs # Description
K Vmeasured
K+1 First lead lag
K+2 Second lead lag
K+3 VA
K+4 Feedback
VUEL VUEL
UEL=1 Alternate UEL=3
UEL Inputs
VOTHSG UEL = 2 VOTHSG
VOS=1 Alternate VOS=2
Stabilizer
Inputs
VAMAX
VUEL
+ + VTVRMAX KCIFD
+ VIMAX KA
EC 1 HV 1 + sTC 1 + sTC1 + HV LV
(pu) 1 + sTR Gate 1 + sTB 1 + sTB1 Gate Gate EFD
VI 1 + sTA VA
+ VIMIN VTVRMIN
VREF VAMIN VOEL
VF
sKF
1 + sTF
+
KLR IFD
0
ILR
6.19 ESST2A
Modified IEEE Type ST2A Excitation System
J+1 KA
J+2 TA (sec)
J+3 VRMAX
J+4 VRMIN
J+5 KE
J+6 TE (>0) (sec)
J+7 KF
J+8 TF (>0) (sec)
J+9 KP
J+10 KI
J+11 KC
J+12 EFDMAX
STATEs # Description
K Sensed VT
K+1 Regulator output, VR
K+2 Exciter output, EFD
K+3 Rate feedback integral
VAR # Description
L KI
VT VE
VE = |KP VT+ jKIIT|
IT
KC IFD
IN = FEX = f(IN)
IFD VE IN FEX
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
VS = VOTHSG + VOEL
If KP = 0 and KI = 0, VB = 1
6.20 ESST3A
IEEE Type ST3A Excitation System
J+3 KM
J+4 TC (sec)
J+5 TB (sec)
J+6 KA
J+7 TA (sec)
J+8 VRMAX
J+9 VRMIN
J+10 KG
J+11 KP
J+12 KI
J+13 VBMAX
J+14 KC
J+15 XL
J+16 VGMAX
J+17 P (degrees)
J+18 TM (sec)
J+19 VMMAX
J+20 VMMIN
STATEs # Description
K Sensed VT
K+1 VA
K+2 VR
K+3 VM
VGMAX
KG
VS
VUEL VRMAX VG VMMAX
+ VIMAX
1 HV 1 + sTC KA
+ KM
EC
VI Gate EFD
(pu) 1 + sTR 1 + sTB VA 1 + sTA VR 1 + sTM VM
+ VIMIN
VRMIN VMMIN
VB
VREF VBMAX
VT VE
V = K P V T + j K + K P X I T
IT E I L
VS = VOTHSG + VOEL
j KC IFD
KP = K P IN = FEX = f(IN)
P IFD VE IN FEX
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.21 ESST4B
IEEE Type ST4B Potential or Compounded Source-Controlled Rectifier Exciter
STATEs # Description
K Sensed VT
K+1 Regulator integrator
K+2 Regulator output, VR
K+3 VM
KG
VS
VUEL VRMAX VMMAX VOEL
+ +
K 1 K
EC 1
IR VR +
K
IM
+ ------------
LV EFD
K + ----------- PM S Gate
1 + sTR PR S 1 + sTA
+
VRMIN VMMIN
VB
VREF VBMAX
VT VE
V = K P V T + j K + K P X I T
IT E I L
VS = VOTHSG
I
FD
I = K ---------- FEX = f(IN)
K P = K THETAP IFD N CV FEX
P E
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.22 ESURRY
Modified IEEE Type AC1A Excitation System
J+1 TA (sec)
J+2 TB (sec)
J+3 TC (sec)
J+4 TD (sec)
J+5 K10
J+6 T1 (sec)
J+7 K16
J+8 KF
J+9 TF > 0 (sec)
J+10 VRMAX
J+11 VRMIN
J+12 TE > 0 (sec)
J+13 E1
J+14 S(E1)
J+15 E2
J+16 S(E2)
J+17 KC (0<KC1)
J+18 KD
J+19 KE
STATEs # Description
K Sensor
K+1 1st lead lag
K+2 2nd lead lag
K+3 Exciter field current sensor
K+4 Feed forward output
K+5 Exciter
VAR # Description
L Exciter field current reference
Vref (pu)
+
1 1 + sTA 1 + sTC
ECOMP
1 + sTR
1 + sTB 1 + sTD
K10
+
VRMAX
Vs (pu) + VR VE
1 EFD (pu)
(PSS input)
+
Iref + sTE
VRMIN
+ 0.
1
1 + sT1
K16
VX = VE SE (VE) FEX = f(IN)
+
VUEL
(Underexcition +
Limiter Signal) KCIFD
KE IN =
+ VE
KFs
1 + TFs
+
IFD (pu)
KD
+
VFE
DT02_002
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
If 0.433 < I < 0.75 F = 0.75 I 2
IN N EX N FEX
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.23 EX2000
EX2000 Excitation System
also represents
IEEE Type AC7B Alternator-Rectifier Excitation System
(Under Excitation Limiter is not included)
J+16 KF2
J+17 E1, exciter flux at knee of curve
J+18 S(E1), saturation factor at knee of curve
J+19 E2, maximum exciter flux
J+20 S(E2), saturation factor at maximum exciter flux
The values are given in per unit unless the unit is shown. For field current references and inverse
timing constants the value of the current is in per unit of the generator Air Gap Line base.
STATEs # Description
K Voltage Transducer
K+1 1st PI controller
K+2 2nd PI controller
K+3 Exciter field voltage
K+4 3rd PI controller (Field Current Limiter)
K+5 Lead-lag element (Field Voltage Limiter)
VARs # Description
Inverse Timing Function Memory
L <1: Latch Gate 2 signal is 0
1: Latch Gate 2 signal is 1
ICONs # Description
0: Field Current Limiter is excluded
(and upper limit VEMAX is on)
M
1: Field Current Limiter is included
(and upper limit VEMAX is off)
0: Minimum Gate 2 is excluded.
M+1
1: Minimum Gate 2 is included.
Memory. Set to 0.
M+2 0: Latch Gate 1 signal is 0
1: Latch Gate 1 signal is 1
Memory. Set to 0.
M+3 0: Field Current Limiter Timer is not active
1: Field Current Limiter Timer is active
VE
1
EC
1
K
KPR + IR
+
KPA +
KIA Minimum
Gate 1
+
sTE
EFD
1 + sTR s s
VA
Voltage + VR VF VFE FEX
Transducer VRMIN VAMIN -KLVFE VEMIN
1st PI Controller 2nd PI Controller
FEX = f [IE]
Siemens Energy, Inc., Power Technologies International
VX
VX = VE SE [VE]
+
KF2
Reference
+ +
Signal
+ +
KE
KCIFD
IN =
+ VE
KD IFD
KF1
PSSE 32.0.5
PSSE 32.0.5 Excitation System Model Data Sheets
PSSE Model Library EX2000
Frequency KVHZ
Reactive
SBASE 1 Current
QELEC KRCC
MBASE ETERM
VREF REFLIMP
+
Minimum VR
+ Gate 2
VUEL
+
VOTHSG DT01_003
Reference Signal
To represent IEEE Type AC7B System you need to set KVHZ = 0 and KRCC = 0, to set ICON(M+1)
= 0 (to exclude Minimum Gate 2) and to set TR = 0 (to exclude the Voltage Transducer).
Inverse Timing
IFDREF2 Output = 1 if
(I1, T1) timing expired Latch OR
(I2, T2) Gate 2
(I3, T3)
(I4, T4)
IFD
IFDLIMP
A C A C
IFDREF3 To
+ KIIFD
D KPIFD + D Minimum
s
IFDREF4 Gate 1
B B
IFDLIMN
3rd PI Controller
1 + s TLEAD Switch Operation:
Output D = B if C = 0
1 + s TLAG Output D = A if C = 1
IFDADVLIM
To represent IEEE Type AC7B System you need to set ICON(M) = 0 (to exclude this limiter).
6.24 EXAC1
IEEE Type AC1 Excitation System
VOEL
J+2 TC (sec)
J+3 KA
J+4 TA (sec)
J+5 VRMAX
J+6 VRMIN
J+7 TE > 0 (sec)
J+8 KF
STATEs # Description
K Sensed ET
K+1 Lead lag
K+2 Regulator output
K+3 VE
K+4 Feedback output
VREF VS
VRMAX
+ +
1 + 1 + sTC KA + 1 VE
EC EFD
(pu) 1 + sTR VC 1 + sTB 1 + sTA VR sTE
FEX
VRMIN 0
FEX = f(IN)
VF
IN
KCIFD
KE + SE IN =
+ VE
sKF
1 + sTF VFE
+
KD IFD
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.25 EXAC1A
IEEE Modified Type AC1 Excitation System
VOEL
J+2 TC (sec)
J+3 KA
J+4 TA (sec)
J+5 VRMAX
J+6 VRMIN
J+7 TE > 0 (sec)
J+8 KF
STATEs # Description
K Sensed ET
K+1 Lead lag
K+2 Regulator output
K+3 VE
K+4 Feedback output
VREF VS
VRMAX
+ +
1 + 1 + sTC KA + 1 VE
EC EFD
(pu) 1 + sTR VC 1 + sTB 1 + sTA VR sTE
FEX
VRMIN 0
FEX = f(IN)
VF VFE
IN
KCIFD
KE + SE IN = V
+ E
sKF
1 + sTF
+
KD IFD
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.26 EXAC2
IEEE Type AC2 Excitation System
VOEL
J+2 TC (sec)
J+3 KA
J+4 TA (sec)
J+5 VAMAX
J+6 VAMIN
J+7 KB
J+8 VRMAX
J+9 VRMIN
J+10 TE > 0 (sec)
J+11 KL
J+12 KH
J+13 KF
J+14 TF > 0 (sec)
J+15 KC
J+16 KD
J+17 KE
J+18 VLR
J+19 E1
J+20 SE(E1)
J+21 E2
J+22 SE(E2)
STATEs # Description
K Sensed ET
K+1 Lead lag
K+2 Regulator output
K+3 VE
K+4 Feedback output
VREF VS
VAMAX
+ + VRMAX
1 + 1 + sTC KA + VE
EC + LV 1
(pu) 1 + sTR V 1 + sTB 1 + sTA V Gate KB EFD
C A VR sTE
VRMIN
VL FEX
VAMIN 0
KL FEX = f(IN)
VF VH
+
VLR IN
KH
K I
KE + SE IN = C FD
+ VE
sKF
1 + sTF VFE
+
KD IFD
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.27 EXAC3
IEEE Type AC3 Excitation System
VOEL
J+2 TC (sec)
J+3 KA
J+4 TA (sec)
J+5 VAMAX
J+6 VAMIN
J+7 TE > 0 (sec)
J+8 KLV
J+9 KR (>0)
J+10 KF
J+11 TF > 0 (sec)
J+12 KN
J+13 EFDN
J+14 KC
J+15 KD
J+16 KE
J+17 VLV
J+18 E1
J+19 SE(E1)
J+20 E2
J+21 SE(E2)
STATEs # Description
K Sensed ET
K+1 Lead lag
K+2 Regulator output
K+3 VE
K+4 Feedback output
KLV
HV +
Gate
VLV
VREF VS VAMAX
+ +
1 1 + sTC KA + 1 VE
EC + EFD
(pu) 1 + sTR VC VERR 1 + sTB 1 + sTA VA VR sTE
FEX
VAMIN 0
KR VFE FEX = f(IN)
+
KE + SE
VF IN
+ KCIFD
IN =
VE
KD IFD
VN
KN
s
1 + sTF VN KF
EFD
EFDN
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.28 EXAC4
IEEE Type AC4 Excitation System
VOEL
J+2 VIMIN
J+3 TC
J+4 TB (sec)
J+5 KA
J+6 TA
J+7 VRMAX
J+8 VRMIN
J+9 KC
STATEs # Description
K Vmeasured
K+1 Lead lag
K+2 VR
VREF VS
VIMAX VRMAX KC IIFD
+ +
1 + S 1 + sTC KA
EC S EFD
1 + sTR VERR 1 + sTB 1 + sTA
VIMIN VRMIN KC IIFD
6.29 EXBAS
Basler Static Voltage Regulator Feeding dc or ac Rotating Exciter
VOEL
STATEs # Description
K Sensed ET
K+1 Integral gain
K+2 Lead lag
K+3 Regulator output
K+4 VE
K+5 Feedback washout
K+6 Feedback lead lag
VREF VOTHSG
VRMAX
+ +
1 K1 1 + sTC KA + 1 VE
EC KP + EFD
(pu) 1 + sTR s 1 + sTB 1 + sTA sTE
+ +
FEX
VUEL VOEL VRMIN
FEX = f(IN)
IN
KCIFD
K E + SE
+ VE
sKF 1 + sTF1
1 + sTF 1 + sTF2
+
KD IFD
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.30 EXDC2
IEEE Type DC2 Excitation System
J+1 KA
J+2 TA (sec)
J+3 TB (sec)
J+4 TC (sec)
J+5 VRMAX or zero
J+6 VRMIN
J+7 KE or zero
J+8 TE (>0) (sec)
J+9 KF
J+10 TF1 (>0) (sec)
J+11 0 Switch
J+12 E1
J+13 SE(E1)
J+14 E2
J+15 SE(E2)
STATEs # Description
K Sensed VT
K+1 Lead lag output
K+2 Regulator output, VR
K+3 Exciter output, EFD
K+4 Rate feedback integrator
VAR # Description
L KE
VREF VS VRMAX*VT
Regulator
+ +
1 + 1 + sTC KA + 1 EFD
EC
(pu) 1 + sTR VERR 1 + sTB 1 + sTA VR sTE (pu)
VFB VRMIN*VT SE + KE
sKF
1 + sTF1
6.31 EXELI
Static PI Transformer Fed Excitation System
STATEs # Description
K First washout stabilizer state
K+1 Lag stabilizer state
K+2 Negative washout stabilizer state
K+3 Sensed voltage state
K+4 Sensed field current state
K+5 Controlled voltage state
K+6 Second washout stabilizer state
K+7 Third washout stabilizer state
VAR # Description
L Stabilizer signal
Ks1
+ SMAX
sT W 3 sTs2
PGEN ---------------------
1 + sT W 1 + sTs2
+ SMAX
Ks2
1 + sTs1
+ EFDMAX
1 + 1 + +
VCOMP VPU VPI EFD
1 + sTFV sTNU
+ + EFDMIN
VREF
XE
VPNF
+ 1
LADIFD
1 + sTFI
DPNF
6.32 EXNEBB
Bus or Solid Fed SCR Bridge Excitation System Model Type NEBB (NVE)
STATEs # Description
K Measuring circuit
K+1 1st amplifier
K+2 1st amplifier output
K+3 2nd amplifier
K+4 2nd amplifier output
VARs # Description
L For tests
L+1 Field current limiter
IFMAX or
I or
VREF(I) IREF = FMIN
V
{ REF(I) or
0
+ + VRMAX
1 K1(1 + T11s) K2(1 + T21s)
VT Efd
1 + TRs (1 + T12s)(1 + T13s) + (1 + T22s)(1 + T23s)
+ + VRMIN
VAR(L) IFMAX
IFMIN
VS
XADIFD(I)
6.33 EXNI
Bus or Solid Fed SCR Bridge Excitation System Model Type NI (NVE)
J+1 KA > 0
J+2 TA 0 (sec)
J+3 VRMAX pu
J+4 VRMIN pu
J+5 KF 0
J+6 TF1 > 0 (sec)
J+7 TF2 0 (sec)
J+8 SWITCH1
J+9 R = rc / rfd2
1 SWITCH = 0 for bus fed, 1 for solid fed
2 r /
c rfd = 0 for exciter with negative current capability
> 0 without (typical = 10)
STATEs # Description
K Measuring circuit
K+1 Amplifier
K+2 Feedback
K+3 Feedback output
VAR # Description
L For tests
VREF(I)
+ VRMAX
VT 1 KA
1 + TRs 1 + TAs
Neg.
+ + VRMIN Current Efd
Logic
VS sKF
(1 + TF2s)(1 + TF1s) XADIFD(I)
VAR(L)
6.34 EXPIC1
Proportional/Integral Excitation System
J+4 VR2
J+5 TA2 (sec)
J+6 TA3 (sec)
J+7 TA4 (sec)
J+8 VRMAX
J+9 VRMIN
J+10 KF
J+11 TF1 (>0) (sec)
J+12 TF2 (sec)
J+13 EFDMAX
J+14 EFDMIN
J+15 KE
J+16 TE (sec)
J+17 E1
J+18 SE1
J+19 E2
J+20 SE2
J+21 KP
J+22 KI
STATEs # Description
K Sensed ET
K+1 First regulator, VA
K+2 Second regulator
K+3 Third regulator, VR
K+4 Exciter output, EFD
K+5 First feedback integrator
K+6 Second feedback integrator
KE + SE
VREF
VR1
+ VRMAX EFDMAX
EC 1 + KA(1 + sTA1) 1 + sTA3 + 1
(pu) EFD
1 + sTR ET S VA (1 + sTA2)(1 + sTA4) VR E0 sTE
+ VRMIN EFDMIN
VR2
VS
sKF
(1 + sTF1)(1 + sTF2) VB
VT
V
E
= K V T + jK I
P I T
I
T
FEX
IFD
IN = KC FEX = f(IN)
IFD VE
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.35 EXST1
IEEE Type ST1 Excitation System
J+4 TB (sec)
J+5 KA
J+6 TA (sec)
J+7 VRMAX
J+8 VRMIN
J+9 KC
J+10 KF
J+11 TF (> 0) (sec)
STATEs # Description
K Vmeasured
K+1 Lead lag
K+2 VR
K+3 Feedback
VREF VS
+ + VIMAX VT VRMAX KC IIFD
1 + 1 + sTC KA
EC EFD
1 + sTR VERR 1 + sTB 1 + sTA
VIMIN VT VRMIN KC IIFD
sKF
1 + sTF
6.36 EXST2
IEEE Type ST2 Excitation System
STATEs # Description
K Sensed VT
K+1 Regulator output, VR
K+2 Exciter output, EFD
K+3 Rate feedback integral
VAR # Description
L KI
VREF VS
VRMAX EFDMAX
+ +
KA
1 + + + 1
EC 1 + sTA EFD
1 + sTR VERR VR sTE
+
VRMIN 0
VF VB
KE
sKF
1 + sTF
V VE
T V
E
= K V T + jK I
P I T
I
T
IFD
IN = KC FEX = f(IN)
IFD VE IN FEX
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
If KP = 0 and KI = 0, VB = 1
6.37 EXST2A
Modified IEEE Type ST2 Excitation System
STATEs # Description
K Sensed VT
K+1 Regulator output, VR
K+2 Exciter output, EFD
K+3 Rate feedback integral
VAR # Description
L KI
VREF VS
VRMAX EFDMAX
+ +
KA
1 + + 1
EC 1 + sTA
EFD
1 + sTR VERR VR sTE
VRMIN 0
VF VB
KE
sKF
1 + sTF
V V = K V T + jK I VE
T
I
E P I T
T
IFD
IN = KC FEX = f(IN)
IFD VE IN FEX
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.38 EXST3
IEEE Type ST3 Excitation System
J+5 TB (sec)
J+6 KA
J+7 TA (sec)
J+8 VRMAX
J+9 VRMIN
J+10 KG
J+11 KP
J+12 KI
J+13 EFDMAX
J+14 KC
J+15 XL
J+16 VGMAX
J+17 P (degrees)
STATEs # Description
K Sensed VT
K+1 VA
K+2 VR
VGMAX
KG
VREF VS VG
VRMAX
+ + VIMAX EFDMAX
1 + sTC KA
1 + +
EC V KJ EFD
1 + sTR ERR 1 + sTB VA 1 + sTA VR
VIMIN
VRMIN VB
V VE
T V = K P V T + j K + K p X I
I E I L T
T
IFD
I N = KC FEX = f(IN)
IFD VE IN FEX
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
j
KP = K P
P
VS = VOTHSG + VUEL + VOEL
6.39 IEEET1
IEEE Type 1 Excitation System
J+2 TA (sec)
J+3 VRMAX or zero
J+4 VRMIN
J+5 KE or zero
J+13 SE(E2)
STATEs # Description
K Sensed VT
K+1 Regulator output, VR
K+2 Exciter output, EFD
K+3 Rate feedback integrator
VAR # Description
L KE
VE = SE EFD
VE
+
+
KE
VREF VRMAX
+
EC 1 KA VR 1
+ EFD
1 + sTA (pu)
(pu) 1 + sTR + sTE
+
VRMIN
VS
sKF
1 + sTF
6.40 IEEET2
IEEE Type 2 Excitation System
J+2 TA (sec)
J+3 VRMAX or zero
J+4 VRMIN
J+5 KE
STATEs # Description
K Sensed VT
K+1 Regulator output, VR
K+2 Exciter output, EFD
K+3 First feedback integrator
K+4 Second feedback integrator
VAR # Description
L KE
VE = SE EFD
VE
+
+
KE
VREF VRMAX
+
EC 1 + KA VR 1 EFD
(pu) 1 + sTR 1 + sTA + sTE (pu)
+
VS VRMIN
1 sKF
1 + sTF2 (1 + sTF1)
6.41 IEEET3
IEEE Type 3 Excitation System
J+8 KP (>0)
J+9 KI or zero
J+10 VBMAX (pu voltage base)
J+11 KE
STATEs # Description
K Sensed VT
K+1 Regulator output, VR
K+2 Exciter output, EFD
K+3 Rate feedback internal
VAR # Description
L KI
VREF VRMAX
VBMAX
+
EC 1 + KA + 1 EFD
1 + sTR 1 + sTA VR
KE + sTE (pu)
(pu) VB
o
+ +
VRMIN
VS sKF
1 + sTF
VT
I V THEV = K P V T + jK I I T MULT
T
LadIfd 1A
2
0.78 Lad Ifd
A = -----------------------------------
-
VTHEV
If A > 1, VB = 0
6.42 IEEET4
IEEE Type 4 Excitation System
J+8 SE(E1)
J+9 E2
J+10 SE(E2)
STATEs # Description
K VRH
K+1 EFD
VAR # Description
L KE
SE
X
VREF VRMAX
+
1 |V|<KV
V -KR 1 + 1 EFD
EC
(pu) KR sTRH VRH VR KE + sTE (pu)
-1
VRMIN
|V|>KV
VRMAX
KV
KV
VRMIN
6.43 IEEET5
Modified IEEE Type 4 Excitation System
J+5 KE
J+6 E1
J+7 SE(E1)
J+8 E2
J+9 SE(E2)
STATEs # Description
K VRH
K+1 EFD
VAR # Description
L KE
SE
X
VREF
VRMAX
+
V 1 |V|<KV 1 EFD
+
EC
(pu) sTRH
KE + sTE (pu)
VRH VR
VRMIN
|V|>KV
VRMAX
KV
KV
VRMIN
6.44 IEEEX1
IEEE Type 1 Excitation System
J+2 TA (sec)
J+3 TB (sec)
J+4 TC (sec)
J+5 VRMAX or zero
J+6 VRMIN
J+7 KE or zero
J+8 TE (>0) (sec)
J+9 KF
J+10 TF1 (>0) (sec)
J+11 Switch
J+12 E1
J+13 SE(E1)
J+14 E2
J+15 SE(E2)
STATEs # Description
K Sensed VT
K+1 Lead lag
K+2 Regulator output, VR
K+3 Exciter output, EFD
K+4 Rate feedback integrator
VAR # Description
L KE
VREF VS
VRMAX
Regulator
+ +
1 + sTC KA 1
1 + + EFD
EC (pu)
(pu) 1 + sTR VERR 1 + sTB 1 + sTA VR sTE
VFB VRMIN
SE + KE
sKF
1 + sTF1
6.45 IEEEX2
IEEE Type 2 Excitation System
J+12 E1
J+13 SE(E1)
J+14 E2
J+15 SE(E2)
STATEs # Description
K Sensed VT
K+1 Lead lag
K+2 Regulator output, VR
K+3 Exciter output, EFD
K+4 First feedback integrator
K+5 Second feedback integrator
VAR # Description
L KE
VREF VS
VRMAX
Regulator Exciter
+ +
1 + 1 + sTC KA + 1 EFD 0
EC
(pu) 1 + sTR VERR
sTE (pu)
1 + sTB 1 + sTA VR
VFB VRMIN
sKF
SE + KE
(1 + sTF1) (1 + sTF2)
Damping
VS = VOTHSG + VUEL + VOEL
6.46 IEEEX3
IEEE Type 3 Excitation System
J+9 KI or zero
J+10 VBMAX (pu voltage base)
J+11 KE
STATEs # Description
K Sensed VT
K+1 Regulator output, VR
K+2 Exciter output, EFD
K+3 Rate feedback integrator
VAR # Description
L KI
VREF VS
VRMAX
+ + Regulator
1 + KA + 1 EFD
EC
(pu) 1 + sTR VERR 1 + sTA VR KE + sTE (pu)
+
VRMIN 0
VFB
Damping
sKF
1 + sTF
VBMAX
VT VTH
V
TH
= K V T + jK I
P I T V 2 TH 0.78L I 2
IT ad fd VB
0
LadIfd
6.47 IEEEX4
IEEE Type 4 Excitation System
J+8 SE(E1)
J+9 E2
J+10 SE(E2)
STATEs # Description
K Sensed VT
K+1 VRH
K+2 EFD
VAR # Description
L KE
VREF
VRMAX
+ KV
1 VERR VRMAX - VRMIN
EC
(pu) 1 + sTR sKVTRH
KV VRH
VRMIN
6.48 IEET1A
Modified IEEE Type 1 Excitation System
J+6 KF
J+7 TF (>0) (sec)
J+8 EFDMIN
J+9 E1
J+10 SE(E1)
J+11 EFDMAX
J+12 SE(EFDMAX)
STATEs # Description
K Regulator output
K+1 Exciter output, EFD
K+2 Rate feedback integrator
VREF VRMAX
EFDMAX
+
+ KA + 1 EFD
EC
(pu) 1 + sTA sTE (pu)
+
EFDMIN
VS VRMIN
sKF
SE + KE
1 + sTF
6.49 IEET1B
Modified Type 1 Excitation System
J+2 VSMIN
J+3 KA
J+4 TA1 (sec)
J+5 VRMAX or zero
J+6 VRMIN
J+7 TA2 (sec)
J+8 KF1
STATEs # Description
K Sensed VT
K+1 Amplified output, VR
K+2 Regulator output, VREG
K+3 Feedback integrator
K+4 Exciter output, EFD
VARs # Description
L KE
L+1 Bias
sKF1 Switch = 1
1 + sTF1
Switch = 0 SE
VREF
Bias X
IMAG Xe VRMAX
VSMAX
+ + +
+ 1 + + KA 1 + 1 EFD
EC
(pu) 1 + sTR VT 1 + sTA1 VR1 + sTA2 V sTE (pu)
REG
+ +
VSMIN
VRMIN
VS
KE
VS = VOTHSG + VUEL + VOEL
6.50 IEET5A
Modified IEEE Type 4 Excitation System
J+8 SE(E1)
J+9 E2
J+10 SE(E2)
J+11 EFDMAX
J+12 EFDMIN
STATEs # Description
K VRH
K+1 Exciter output
VARs # Description
L KE
L+1 VTO
SE
X
VREF
VRMAX
EFDMAX
+
*
KA |V|<KV + 1
EC EFD
(pu) 1 + sTRH VR KE + sTE
EFDMIN
VTO VRMIN
|V|>KV
+ VRMAX
EC KV
(pu)
VValue at kPAUSE
VRMIN
KV =1
KA
*If TRH equals zero, block becomes
s
6.51 IEEX2A
IEEE Type 2A Excitation System
J+2 TA (sec)
J+3 TB (sec)
J+4 TC (sec)
J+5 VRMAX or zero
J+6 VRMIN
J+7 KE or zero
J+8 TE (>0) (sec)
J+9 KF
J+10 TF1 (>0) (sec)
J+11 E1
J+12 SE(E1)
J+13 E2
J+14 SE(E2)
STATEs # Description
K Sensed VT
K+1 Lead lag
K+2 Regulator output, VR
K+3 Exciter output, EFD
K+4 Rate feedback integrator
VAR # Description
L KE
VREF VS VRMAX
Regulator Exciter
+ +
EC 1 + 1 + sTC KA + 1 EFD
sTE (pu)
(pu) 1 + sTR VERR 1 + sTB 1 + sTA VR
VFB VRMIN 0
sKF
SE + KE
1 + sTF1
VS = VOTHSG + VUEL + VOEL
6.52 IVOEX
IVO Excitation Model
J+1 A1
J+2 A2
J+3 T1
J+4 T2
J+5 MAX1
J+6 MIN1
J+7 K3
J+8 A3
J+9 A4
J+10 T3
J+11 T4
J+12 MAX3
J+13 MIN3
J+14 K5
J+15 A5
J+16 A6
J+17 T5
J+18 T6
J+19 MAX5
J+20 MIN5
STATEs # Description
K Integrator 1
K+1 Integrator 2
K+2 Integrator 3
VREF
MAX1 MAX3
+ MAX5
A +T S A +T S A +T S
EC 1 1 3 3 5 5 EFD
K ------------------------ K ------------------------ K ------------------------
(pu) 1A + T S 3A + T S 5A + T S (pu)
2 2 4 4 6 6
+ MIN5
VS MIN1 MIN3
6.53 OEX12T
Ontario Hydro IEEE Type ST1 Excitation System With Continuous
and Bang Bang Terminal Voltage Limiter
J+2 VIMIN
J+3 TC
J+4 TB (>0) (sec)
J+5 KA
J+6 TA (sec)
J+7 VRMAX
J+8 VRMIN
J+9 KC
J+10 KF
J+11 TF (>0) (sec)
J+12 ETMIN
J+13 VTMAX
J+14 VTMIN
J+15 LIMOUT
J+16 ACON
J+17 BCON
J+18 VEMAX
J+19 VEMIN
J+20 IFLMT
J+21 KIFL
Note: Parameters (J+23) through (J+27) are for the continuous voltage limiter.
STATEs # Description
K Voltage sensing block
K+1 Lead lag TC/TB block
K+2 Regulator TA block
K+3 TF feedback block
K+4 Voltage limiter TL1/TL2
VARs # Description
L Limiter status
L+1 Period of decay
L+2 Monitored voltage Vm1
L+3 Monitored voltage Vm2
L+4 Monitored voltage Vm3
IFLMT
IFD + KIFL
IFD
V2
VEMAX
VS + +
Vm2 Vm3
VEMIN
Vm4 V3
VT VRMAX KCIFD
+ VIMAX +
1 + sTC + KA If ET <
EC 1 +
ETMIN EFD
1 + sTR Vm5 1 + sTB 1 + sTA EFD EFD = 0
+ + VIMIN
VSUM
VT VRMIN + KCIFD
VREF
sKF
1 + sTF
ETLMT VOMX
+ 1 + sT
L1
K ---------------------------- 0
ETL 1 + sT
L2
V 2 = V m1
VOMN V2
LIMOUT < 0.5 V SUM = 0.
V = 0.
3
Select V 2 = 0.
ET VSUM
High Vm1 0.5 < LIMOUT < 1.5 V SUM = V m1
V = 0.
3
If E > V
T
V = V
TMAX O OMX V 2 = 0. V3
1.5 < LIMOUT V SUM = 0.
V <E <V V = V
VMIN T TMAX 3 m1
If V O = V OMX
and V = V
O OMX
If E < V V = V
T TMIN O OD
B
CON
t = t + ------------------
3 2 A
CON
Voltage Limiter
6.54 OEX3T
Ontario Hydro IEEE Type ST1 Excitation System
With Semicontinuous and Acting Terminal Voltage Limiter
J+2 T2 (sec)
J+3 T3 (sec)
J+4 T4 (sec)
J+5 KA
J+6 T5 (sec)
J+7 T6 (sec) (<T5)
J+8 VRMAX
J+9 VRMIN
J+10 TE (>0) (sec)
J+11 KF
J+12 TF (>0) (sec)
J+13 KC
J+14 KD
J+15 KE
J+16 E1
J+17 SE(E1)
J+18 E2 (E2 > E1)
J+19 SE(E2)
STATEs # Description
K Voltage sensing block
K+1 Lead lag T2/T1 block
K+2 Lead lag T4/T3 block
VAR # Description
L Input to VREF junction
IFD
KCIFD
VREF IFD (pu) IN =
VTH
+ IN
KD
EC 1 +
VAR(L)
(pu) 1 + sTR VRMAX FEX = f(IN)
+ FEX
1 + sT2 1 + sT6 1 + sT4 + 1 VE
VS + EFD
KA
1 + sT1 1 + sT5 1 + sT3 sTE VTH (pu)
VRMIN 0
SE + K E
sKF
1 + sTF
A EX EXP B EX V E
F EX = 1.0 0.58 I N for I N 0.433 S E = -------------------------------------------------------
-
VE
6.55 REXSY1
General-Purpose Rotating Excitation System Model
STATEs # Description
K Sense voltage
K+1 Proportional voltage
K+2 Regulator lead-lag, first stage
K+3 Regulator output
K+4 Feedback lead-lag
K+5 Feedback state
K+6 Proportional field current
K+7 VE
K+8 Regulator lead-lag, second state
K+9 Exciter field current regulator output
1
1 + sTR
+ +
VS VREF
F * VRMAX
+ VIMAX
K 1 + sT 1 + sT 1
VI C1 C2
K + ----------- --------------------------------------------------------- VR
VP s 1 + sT 1 + sT 1 + sTA
B1 B2
-VIMAX
F * VRMIN
0
1 + sT sK
F1 F-
---------------------- ------------------ 1 IFE
1 + sT 1 + sT
F2 F
2
ITERM
Exciter Field Current Regulator
XC
Rotating Exciter
F * VFMAX
VCMAX
+ VE
VR K 1 + 1 EFD
+ II ------------------- ----------
K + --------- 1 + sT sT
IP S P E
F * VFMIN
KH FEX = f(IN)
IFE IN
+ K L I
C ad fd
KE + SE ---------------------------
V
E
+ LadIfd
KD
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.56 REXSYS
General-Purpose Rotating Excitation System Model
ECOMP
This model is located at system bus #____ IBUS, XADIFD
Machine identifier #____ ID, VOTHSG EFD
REXSYS
This model uses CONs starting with #____ J,
VUEL
and STATEs starting with #____ K.
VOEL
STATEs # Description
K Sense voltage
K+1 Proportional voltage
K+2 Regulator lead-lag, first stage
K+3 Regulator output
K+4 Feedback lead-lag
K+5 Feedback state
K+6 Proportional field current
K+7 VE
K+8 Regulator lead-lag, second stage
K+9 Exciter field current regulator output
1
1 + sTR
+ +
VS VREF
F * VRMAX
+ VIMAX
K 1 + sT 1 + sT 1
VI C1 C2
K + ----------- --------------------------------------------------------- VR
VP s 1 + sT 1 + sT 1 + sTA
B1 B2
-VIMAX
F * VRMIN
0
1 + sT sK
F1 F
---------------------- ------------------- 1 IFE
1 + sT 1 + sT
F2 F
2
VR K 1 1 VE EFD
+ II ------------------- + ----------
K + --------- 1 + sT sT
IP S P E
F * VFMIN
KH FEX = f(IN)
IFE IN
+ K L I
C ad fd
KE +SE ---------------------------
V
E
+ LadIfd
KD
If I 0. F = 1
N EX
If I 0.433 F = 1 0.577 I
N EX N
IN If 0.433 < I < 0.75 F 0.75 I 2
= FEX
N EX N
If I 0.75 F = 1.732 1 I
N EX N
If I >1 F = 0
N EX
6.57 SCRX
Bus Fed or Solid Fed Static Exciter
ECOMP
This model is located at system bus #_______ IBUS,
VOTHSG
Machine identifier #_______ ID,
VUEL
This model uses CONs starting with #_______ J, EFD
VOEL SCRX
and STATEs starting with #_______ K.
XADIFD
ETERM
J+6 CSWITCH1
J+7 rc / rfd2
1 Set C
SWITCH = 0 for bus fed.
Set CSWITCH = 1 for solid fed.
2 Set CON(J+7) = 0 for exciter with negative field current capability.
Set CON(J+7) > 0 for exciter without negative field current capability.
(Typical CON(J+7) = 10)
STATEs # Description
K First integrator
K+1 Second integrator
CSWITCH = 0 CSWITCH = 1
VREF
EMAX Et 1.0
+
Ebridge
1 + TAs K
EC X
(pu) 1 + TBs 1 + TEs Negative
EFD
Current Logic
LadIfd
+
EMIN
VS
6.58 SEXS
Simplified Excitation System
STATEs # Description
K First integrator
K+1 Second integrator
VREF EMAX
EC 1 + TAs K
EFD
(pu) 1 + TBs 1 + TEs
+
EMIN
VS
6.59 ST5B
IEEE 421.5 2005 ST5B Excitation System
STATEs # Description
K Sensed VT
K+1 First lead-lag (voltage regulator channel)
K+2 Second lead-lag (voltage regulator channel)
K+3 EFD
K+4 First lead-lag (under-excitation channel)
K+5 Second lead-lag (under-excitation channel)
K+6 First lead-lag (over-excitation channel)
K+7 Second lead-lag (over-excitation channel)
VARs # Description
L V1
L+1 V2
L+2 V3
6.60 ST6B
IEEE 421.5 2005 ST6B Excitation System
STATEs # Description
K Sensed VT
K+1 Integral channel
K+2 Derivative channel
K+3 VG
VARs # Description
L VA
L+1 VR
L+2 VI
6.61 ST7B
IEEE 421.5 2005 ST7B Excitation System
J+12 KIA (pu) (>0) gain of the first order feedback block
TIA (>0) time constant of the first order feedback block
J+13
(sec)
STATEs # Description
K Sensed VT
K+1 Lead-lag block 1
K+2 Lead-lag block 2
K+3 First order feedback block
VARs # Description
L V1
L+1 V2
L+2 Vref_FB
6.62 URHIDT
High Dam Excitation Model
J+2 Ki
J+3 Tdi (> 0)
J+4 Tie
J+5 Kdi
J+6 Kd2i
J+7 Kdifd
J+8 Tdifd (> 0)
J+9 Tr
J+10 Vimax
J+11 Vimin
J+12 Tb
J+13 Tc
J+14 Tb1
J+15 Tc1
J+16 Ka
J+17 Taw (> 0)
J+18 Vamax
J+19 Vamin
J+20 a
J+21 Tb2 (> 0)
J+22 Kir
J+25 Vlothrsh
J+26 Tlodelay
J+27 Taf
J+28 Vhithrsh
J+29 b
STATEs # Description
K Compensating voltage
K+1 First exciter stabilizing
K+2 Second exciter stabilizing
K+3 Regulator
K+4 Feedback
K+5 Voltage stabilizer
K+6 First current
K+7 Current filter
K+8 Second current
K+9 Field current stabilization
VARs # Description
L Initial current
L+1 Current flow
L+2 Timer
sK T
VT dv dv
------------------------
1 + sT
dv
I Ki
sT 1
di
---------------------
1 + sT
--------------------
1 + sT Kdi
di ie
sT
di
--------------------- Kd2i
1 + sT
di
sK T
Lad Ifd difd difd
---------------------------------
1 + sT
difd
Vref Vs
Vamax
Vimax
+ +
+
VT 1 - 1 + sT 1 + sT K + +
V + I R ----------------- c c1 a
IT T T comp
+ jX
comp 1 + sT -------------------
1 + sT
----------------------
1 + sT
------------------
1 + sT
Efd
Ec r b b1 a
Vimin Vamin
a + sbT
b2
------------------------- Xe
1 + sT
b2
K +
ir Lad Ifd
0
Ilr
Forcing Before Operation:
Vterr = Vref Ec
Working Bridge Operation:
Ta = Taw If Vterr > Vlothrsh, start low-voltage timer
If timer > Tlodelay,
Ta = forcing bridge time constant (Taf)
Input of regulator (ds2) = Vamax/Ta
Reset to normal regulator when Vterr > Vhithrsh for Tlodelay
6.63 URST5T
IEEE Proposed Type ST5B Excitation System
J+7 VRMIN
J+8 T1
J+9 KC
STATEs # Description
K Sensed VT
K+1 First lead lag
K+2 Second lead lag
K+3 Final filter
VUEL VOEL
VRMAX/KR VRMAX/KR VRMAX VRMAX * VT
1 HV LV + 1 + sTC1 1 + sTC2 1 +
EC EFD
Gate Gate KR
(pu) 1 + sTr 1 + sTB1 1 + sTB2 1 + sT1
+ +
This chapter contains a collection of data sheets for the turbine-governor models contained in the
PSSE dynamics model library.
Model Description
BBGOV1 Brown-Boveri turbine-governor model
CRCMGV Cross compound turbine-governor model
DEGOV Woodward diesel governor model
DEGOV1 Woodward diesel governor model
GAST Gas turbine-governor model
GAST2A Gas turbine-governor model
GASTWD Gas turbine-governor model
GGOV1 GE general purpose turbine-governor model
HYGOV Hydro turbine-governor model
HYGOV2 Hydro turbine-governor model
HYGOVM Hydro turbine-governor lumped parameter model
HYGOVT Hydro turbine-governor traveling wave model
IEEEG1 1981 IEEE type 1 turbine-governor model
IEEEG2 1981 IEEE type 2 turbine-governor model
IEEEG3 1981 IEEE type 3 turbine-governor model
IEESGO 1973 IEEE standard turbine-governor model
IVOGO IVO turbine-governor model
PIDGOV Hydro turbine and governor model
SHAF25 Torsional-elastic shaft model for 25 masses
TGOV1 Steam turbine-governor model
TGOV2 Steam turbine-governor model with fast valving
TGOV3 Modified IEEE type 1 turbine-governor model with fast valving
TGOV4 Modified IEEE type 1 speed governing model with PLU and EVA
TGOV5 Modified IEEE type 1 turbine-governor model with boiler controls
Model Description
TURCZT Czech hydro or steam turbine-governor model
TWDM1T Tail water depression hydro governor model 1
TWDM2T Tail water depression hydro governor model 2
URCSCT Combined cycle, single shaft turbine-governor model
URGS3T WECC gas turbine governor model
WEHGOV Woodward electronic hydro governor model
WESGOV Westinghouse digital governor for gas turbine
WPIDHY Woodward PID hydro governor model
WSHYDD WECC double derivative hydro governor model
WSHYGP WECC GP hydro governor plus turbine model
WSIEG1 WECC modified 1981 IEEE type 1 turbine-governor model
7.1 BBGOV1
European Governor Model
J+9 K2
J+10 T5 (sec)
J+11 K3
J+12 T6 (sec)
J+13 T1 (sec)
J+14 SWITCH
J+15 PMAX
J+16 PMIN
STATEs # Description
K Step and gradient limiter
K+1 PI controller
K+2 Valve output
K+3 Steam output
K+4 Turbine power
K+5 Turbine power
K+6 Electrical damping feedback
VAR # Description
L Reference, Po
PELEC
SWITCH = 0
SWITCH 0
1
Po
1 + sT1
+ PMAX
-fcut -KLS
+ 1 KD
Speed
KS KP (1+ ) 1 + sTD
fcut KLS sTN
+ PMIN
1 KG
S KLS
1 1 - K2 +
PMECH
1 + sT4
+ +
1 - K3
K2
1 + sT5
K3
1 + sT6
7.2 CRCMGV
Cross Compound Turbine-Governor
J PMAX (HP)1
J+1 R (HP)
J+2 T1 (HP) (>0)
J+3 T3 (HP) (>0)
STATEs # Description
K
K+1
High-pressure unit
K+2
K+3
K+4
K+5
Low-pressure unit
K+6
K+7
VARs # Description
L PMECH1 REF
L+1 PMECH2 REF
Reference
VAR(L)
PMAX
+
1/R 1 + sFT5 +
SPEEDHP PMECHHP
1 + sT1 (1 + sT3) (1 + sT4) (1 + sT5)
PMIN = 0
High-Pressure Unit
(DH) (ET-HP)2
Reference
VAR(L+1) PMAX
+ +
1/R 1 + sFT5 +
SPEEDLP PMECHLP
1 + sT1 (1 + sT3) (1 + sT4) (1 + sT5)
PMIN = 0
Low-Pressure Unit
(DH) (ET-HP)2
7.3 DEGOV
Woodward Diesel Governor
J+6 T6 (sec)
J+9 TMIN
STATEs # Description
K Electric control box 1
K+1 Electric control box 2
K+2 Actuator 1
K+3 Actuator 2
K+4 Actuator 3
VARs # Description
L
L+1
. Delay table
.
.
L+12
1 + Speed
TMAX
Actuator
7.4 DEGOV1
Woodward Diesel Governor
J+9 TMIN
J+10 DROOP
J+11 TE
STATEs # Description
K Electric control box 1
K+1 Electric control box 2
K+2 Actuator 1
K+3 Actuator 2
K+4 Actuator 3
K+5 Power transducer
VARs # Description
L Reference
L+1
.
. Delay table
.
L+13
VAR(L)
TMAX 1 + Speed
+
(1 + T3s) K(1 + T4s)
e-sTD X PMECH
Speed 1 + T1s + T2T1s2 s(1 + T5s) (1 +T6s)
TMIN Engine
Electric Control Box
Actuator
ICON(M)=0
DROOP
1 SBASE
ICON(M)=1 PELEC
1+sTE MBASE
7.5 GAST
Gas Turbine-Governor
J+8 Dturb
STATEs # Description
K Fuel valve
K+1 Fuel flow
K+2 Exhaust temperature
VAR # Description
L Load reference
Speed Dturb
SPEED
1
R VMAX
Load + Low 1 1 +
Reference Value PMECH
VAR(L) Gate 1 + T1s 1 + T2s
VMIN
+ 1
KT
1 + T3s
+ +
Load Limit
7.6 GAST2A
Gas Turbine Model
STATEs # Description
K Speed governor
K+1 Valve positioner
K+2 Fuel system
K+3 Radiation shield
K+4 Thermocouple
K+5 Temperature control
K+6 Gas turbine dynamics
K+7 Combustor
K+8 Combustor
K+9 Turbine/exhaust
K+10 Turbine/exhaust
K+11 Fuel controller delay
K+12 Fuel controller delay
VARs # Description
L Governor reference
L+1 Temperature reference flag
L+2 Low value select output
L+3 Output of temperature control
MAX TC Radiation
Thermocouple Shield
+ Turbine
Temperature T5s + 1 1 K5
f1
K4 +
Control* t s T4s + 1 T3s + 1
Wf1 Turbine Exhaust
Reference
VAR(L) e-sETD
MAX K6
Valve Fuel
Fuel Positioner System
+ + Wf
Control Fuel Combustor
W(Xs+1) Low
Flow
e-sECR
+ 1
e-sT
a
Value X K3 bs + c fs + 1
Ys + Z Select
Speed Speed
MIN Governor Control
Kf
Gas Turbine
Dynamics
1
TCDS + 1
SPEED Turbine
PMECH TRATE Wf2
(pu deviation)
X f2
+ MBASE
+
1.0 N
*Temperature control output is set to output of speed governor when temperature control input changes from positive to negative.
7.7 GASTWD
Woodward Gas Turbine-Governor Model
J+11 K3
J+12 a (> 0) valve positioner
J+13 b (sec) (> 0) valve positioner
J+14 c valve positioner
J+15 f (sec) (> 0)
J+16 Kf
J+17 K5
J+18 K4
J+19 T3 (sec) (> 0)
J+20 T4 (sec) (> 0)
J+21 t (> 0)
J+22 T5 (sec) (> 0)
J+23 af1
J+24 bf1
J+27 cf2
STATEs # Description
K Speed governor
K+1 Valve positioner
K+2 Fuel system
K+3 Radiation shield
K+4 Thermocouple
K+5 Temperature control
K+6 Gas turbine dynamics
K+7 Combustor
K+8 Combustor
K+9 Turbine/exhaust
K+10 Turbine/exhaust
K+11 Fuel controller delay
K+12 Fuel controller delay
K+13 Power transducer
VARs # Description
L Governor reference
L+1 Temperature reference flag
L+2 Low value select output
L+3 Output of temperature control
L+4 Derivative control
Pelec
TC Setpoint for
Temperature Control
MAX
SBASE Thermocouple Radiation Shield
TRATE + Turbine
Temperature T5s + 1 1 K5
Control* K4 + f1
Pe ts T4s + 1 T3s + 1
e-sETD
KP K6
Valve Fuel
Fuel Positioner System Wf
+ Control + Fuel Combustor
Speed Low
+ Flow
Reference +
KI
Value X K3 e-sT
+ a 1
e-sECR
VAR (L)
s
Select bs + c fs + 1
+
Speed
sKD Control Kf
Gas Turbine
Dynamics
MIN 1
TCDs + 1
SPEED Turbine
(pu deviation) Wf2
PMECH TRATE f2
X
+ MBASE
+
1.0
N
*Temperature control output is set to output of speed governor when temperature control input changes from positive to negative.
7.8 GGOV1
GE General Governor/Turbine Model
STATEs # Description
K Machine Electrical Power Measurement
K+1 Governor Differential Control
K+2 Governor Integral Control
K+3 Turbine Actuator
K+4 Turbine Lead-Lag
K+5 Turbine load limiter measurement
K+6 Turbine Load Limiter Integral Control
K+7 Supervisory Load Control
K+8 Acceleration Control
K+9 Temperature Detection Lead-Lag
VARs # Description
L Load Reference
L+1 Output of Load Limiter PI Control
L+2 Output of Governor PID Control
L+3 Low Value Select Output
L+4 Output of Turbine Actuator
L+5 Output of Turbine Lead-Lag
L+6 Supervisory Load Controller Setpoint, Pmwset
L+7
.
. Delay Table
.
L+19
L+20 Dead Band
Notes:
a. This model can be used to represent a variety of prime movers controlled by PID
governors. It is suitable, for example, for representation of:
gas turbine and single shaft combined cycle turbines
diesel engines with modern electronic or digital governors
steam turbines where steam is supplied from a large boiler drum or a large
header whose pressure is substantially constant over the period under study
simple hydro turbines in dam configurations where the water column length is
short and water inertia effects are minimal
b. Per unit parameters are on base of the turbine MW base (Trate). If no value is
entered for Trate, parameters are specified on generator MVA base.
c. The range of fuel valve travel and of fuel flow is unity. Thus the largest possible
value of Vmax is 1.0 and the smallest possible value of Vmin is zero. Vmax may,
however, be reduced below unity to represent a loading limit that may be imposed
by the operator or a supervisory control system. For gas turbines Vmin should nor-
mally be greater than zero and less than wfnl to represent a minimum firing limit.
The value of fuel flow at maximum output must be less than, or equal to unity,
depending on the value of kturb.
d. The parameter Teng is provided for use in representing diesel engines where there
is a small but measurable transport delay between a change in fuel flow setting and
the development of torque. In the majority of cases Teng should be zero.
e. The parameter Flag is provided to recognize that fuel flow, for a given fuel valve
stroke, can be proportional to engine speed. This is the case for GE gas turbines
and for diesel engines with positive displacement fuel injectors. Flag should be set
to unity for all GE gas turbines and most diesel engines. Flag should be set to zero
where it is known that the fuel control system keeps fuel flow independent of engine
speed.
f. The load limiter module may be used to impose a maximum output limit such as an
exhaust temperature limit. To do this the time constant Tfload should be set to rep-
resent the time constant in the measurement of temperature (or other signal), and
the gains of the limiter, Kpload, Kiload, should be set to give prompt stable control
when on limit. The load limit can be deactivated by setting the parameter Ldref to a
high value.
g. The parameter Dm can represent either the variation of engine power with shaft
speed or the variation of maximum power capability with shaft speed.
If Dm is positive it describes the falling slope of the engine speed versus power
characteristic as speed increases. A slightly falling characteristic is typical for recip-
rocating engines and some aeroderivative turbines.
Pmwset is given a value automatically when the model is initialized and stored in
VAR(L+6), and can be changed thereafter. The load controller must be adjusted to
respond gently relative to the speed governor. A typical value for Kimw is 0.01, cor-
responding to a reset time of 100 seconds. Setting Kimw to 0.001 corresponds to
a relatively slow acting load controller.
i. The parameters Aset, Ka, and Ta describe an acceleration limiter. These parame-
ters may be omitted from the data list if the limiter is not active.
j. The parameter db is the speed governor dead band. This parameter is in terms of
per unit speed.
k. Tsa and Tsb are provided to augment the exhaust gas temperature measurement
subsystem in gas turbines.
l. Rup and Rdown specify the maximum rate of increase and decrease of the output
of the load limit controller (Kpload/Kiload).
7.9 HYGOV
Hydro Turbine-Governor
STATEs # Description
K e, filter output
K+1 c, desired gate
K+2 g, gate opening
K+3 q, turbine flow
VARs # Description
L Speed reference
L+1 h, turbine head
VAR(L) + 1 e 1 + T rs c 1 g
nref 1 + Tfs rTrs 1 + Tgs
Velocity and
Speed + Position Limits
SPEED SPEED
R Dturb
X
g 1 q +
X X At PMECH
Tws +
q h
+
1 qNL
7.10 HYGOV2
Hydro Turbine-Governor
J+1 Ki
J+2 KA
J+3 T1
J+4 T2
J+5 T3 (> 0)
J+6 T4 (> 0)
J+7 T5
J+8 T6 (> 0)
J+9 TR (> 0)
J+10 r, temporary droop
J+11 R, permanent droop
J+12 +VGMAX
J+13 Maximum gate position, GMAX
J+14 Minimum gate position, GMIN
J+15 PMAX
STATEs # Description
K Filter
K+1 Governor
K+2 Governor speed
K+3 Droop
K+4 Gate position
K+5 Penstock
VAR # Description
L Reference
7.11 HYGOVM
Hydro Turbine-Governor Lumped Parameter Model
STATEs # Description
K e, filter output
K+1 c, desired gate
K+2 g, gate opening
K+3 Relief valve opening or jet deflector position
K+4 QPEN, penstock flow (cfs or cms)
K+5 QTUN, tunnel flow (cfs or cms)
K+6 HSCH, surge chamber head (ft or m)
VARs # Description
L Speed reference
L+1 Turbine head (ft or m)
L+2 Turbine flow (cfs or cms)
Relieve valve flow or deflected jet flow
L+3
(cfs or cms)
L+4 Head at surge chamber base (ft or m)
L+5 Internal memory
HSCH
SCHARE
(V)
HLAKE
SURGE
(V) QSCH CHAMBER
TUNNEL
TUNL/A, TUNLOS
QTUN SCHLOS
HBSCH PENSTOCK
PENL/A, PENLOS
QPEN
TURBINE HTAIL
(V)
Q
2
PEN X
At PENLOS
2
QPEN At
Gate + +
Relief Valve X O
2 O
2 gv QPEN
INPUT s PENL/A OUTPUT
+ +
+
HBSCH
HTAIL
HBSCH
HLAKE
S +
+
HSCH +
TUNLOS
gv
1 2
s TUNL/A Q
SCHLOS s SCHARE TUN
X
2
Q SCH
X QSCH
+
QTUN
QPEN
LEGEND
gv Gravitational acceleration At Turbine flow gain
TUNL/A Summation of length/cross section of tunnel O Gate + relief valve opening
SCHARE Surge chamber cross section HSCH Water level in surge chamber
PENLOS Penstock head loss coefficient QPEN Penstock flow
TUNLOS Tunnel head loss coefficient QTUN Tunnel flow
FSCH Surge chamber orifice head loss coefficient QSCH Surge chamber flow
Summation of length/cross section of penstock,
PENL/A
scroll case and draft tube
Jet Deflector
MXJDOR
+ 1 1
s
Tg Deflector
Position
+ MXJDCR
0.01
+
Governor Gate Servo
Speed GMAX
MXGTOR or
MXBGOR
Speed + 1 1 + Trs + 1 1
S S
Reference 1 + Tfs r Trs Tg s Gate
Opening
MXGTCR or
GMIN MXBGCR
R
+ RVLMAX
RVLVCR
1
s Relief Valve
Opening
0
Relief Valve
LEGEND
R Permanent droop MXBGCR Maximum buffered gate closing rate
r Temporary droop GMAX Maximum gate limit
Tr Governor time constant GMIN Minimum gate limit
Tf Filter time constant RVLVCR Relief valve closing rate
Tg Servo time constant RVLMAX Maximum relief valve limit
MXGTOR Maximum gate opening rate MXJDOR Maximum jet deflector opening rate
MXGTCR Maximum gate closing rate MXJDCR Maximum jet deflector closing rate
MXBGOR Maximum buffered gate opening rate
7.12 HYGOVT
Hydro Turbine-Governor Traveling Wave Model
STATEs # Description
K e, filter output
K+1 c, desired gate
K+2 g, gate opening
K+3 Relief valve opening or jet deflector position
K+4 QPEN, Penstock flow at the surge chamber end
K+5 QTUN, Tunnel flow at the surge chamber end
K+6 HSCH, surge chamber head (ft or m)
VARs # Description
L Speed reference
L+1 Turbine head (ft or m)
L+2 Turbine flow (cfs or cms)
L+3 Relieve valve flow or deflected jet flow (cfs or cms)
L+4 Head at surge chamber base (ft or m)
L+5 Internal memory
L+6 Penstock flow at surge chamber ends (cfs or cms)
L+7
.
Flows along the penstock
.
(cfs or cms)
.
L+25
L+26
.
Heads along the penstock
.
(ft or m)
.
L+45
L+46 Penstock head at surge chamber end (ft or m)
L+47
.
Flows along the tunnel
.
(cfs or cms)
.
L+65
L+66 Tunnel head at lake end (ft or m)
L+67
.
Heads along the tunnel
.
(ft or m)
.
L+85
HSCH
SCHARE
(V)
HLAKE
SURGE
(V) QSCH CHAMBER
TUNNEL
QTUN SCHLOS
HBSCH
PENSTOCK
QPEN
TURBINE HTAIL
(V)
Time
TUNNEL
(TUNLGTH, TUNSPD, TUNARE, TUNLOS)
Tunnel Inlet
Constraints
Surge Chamber
Constraints
DELT*ICON(M+3)
Space
Flows VAR(L+46) VAR(L+45 + ICON(M+2)) = QTUN
TUNLGTH/(ICON(M+2)+1)
Heads VAR(L+66) VAR(L+65 + ICON(M+2)) = HBSCH
Surge Chamber
+ 1 +
QTUN s SCHARE HBSCH
QSCH HSCH
+
QPEN X SCHLOS
Q2SCH
Time
PENSTOCK
(PENLGTH, PENSPD, PENARE, PENLOS)
Surge Chamber Turbine
Constraints Constraints
DELT*ICON(M+1)
Space
Flows VAR(L+6) = QPEN VAR(L+55 + ICON(M))
PENLGTH/(ICON(M)+1)
Heads VAR(L+26) = HBSCH VAR(L+25 + ICON(M))
Jet Deflector
MXJDOR
+ 1 1 Deflector
s Position
Tg
+ MXJDCR
0.01
1 Relief Valve
s Opening
0
Relief Valve
LEGEND:
7.13 IEEEG1
IEEE Type 1 Speed-Governing Model
J+18 K7
J+19 K8
STATEs # Description
K First governor integrator
K+1 Governor output
K+2 First turbine integrator
K+3 Second turbine integrator
K+4 Third turbine integrator
K+5 Fourth turbine integrator
VARs # Description
L Reference, P0
L+1 Internal memory
+ + +
P PMECHHP
M1
Po + + +
PMAX K1 K3 K5 K7
+ Uo
K(1 + sT2) 1 1 1 1 1 1
T3 S 1 + sT4 1 + sT5 1 + sT7
SPEEDHP 1 + sT1 1 + sT6
Uc
PMIN K2 K4 K6 K8
+ + +
+ + +
PMECHLP
PM2
7.14 IEEEG2
IEEE Type 2 Speed-Governing Model
STATEs # Description
K First integrator
K+1 Second integrator
K+2 Hydro turbine
VAR # Description
L Reference, P0
Po
+ PMAX
PMIN
7.15 IEEEG3
IEEE Type 3 Speed-Governing Model
STATEs # Description
K Servomotor position
K+1 Gate position
K+2 Transient droop compensation
K+3 Hydroturbine
VAR # Description
L Reference, P0
Po Uo PMAX
+
a a
13 21
1 1 a 1 + a ------------------ sT PM
23 11 a W
SPEED 23 PMECH
TG(1 + sTP) S ---------------------------------------------------------------------------
1 + a sT
11 W
Uc PMIN
+
sTR
1 + sTR
7.16 IEESGO
IEEE Standard Model
STATEs # Description
K Filter output
K+1 Valve or gate servo output
K+2 Turbine powers
K+3 Turbine powers
K+4 Turbine powers
VAR # Description
L Reference, Po
Po
+
K1 (1 + sT2) PMAX 1 +
SPEED 1 K2 PMECH
(1 + sT1) (1 + sT3) PMIN 1 + sT4
+ +
1 K3
K2 K3
1 + sT5 1 + sT6
Turbine
7.17 IVOGO
IVO Governor Model
J+5 MAX1
J+6 MIN1
J+7 K3
J+8 A3
J+9 A4
J+10 T3
J+11 T4
J+12 MAX3
J+13 MIN3
J+14 K5
J+15 A5
J+16 A6
J+17 T5
J+18 T6
J+19 MAX5
J+20 MIN5
STATEs # Description
K Integrator 1
K+1 Integrator 2
K+2 Integrator 3
VAR # Description
L Reference
REF
MAX1 MAX3
MAX5
+
A +T S A +T S A +T S
1 1 3 3 5 5
SPEED K ------------------------ K ------------------------ K ------------------------ PMECH
1A + T S 3A + T S 5A + T S
2 2 4 4 6 6
MIN5
MIN1 MIN3
7.18 PIDGOV
Hydro Turbine-Governor
STATEs # Description
K Input sensor
K+1 PI controller
K+2 First regulator
K+3 Derivative controller
K+4 Second regulator
K+5 Gate position
K+6 Water inertia
VAR # Description
L Reference
+
VAR(L) = Pref
Flag
sKd
1 + sTa
Velmax Gmax
Power
3
+ 1 1 1 - sTz +
PMECH
Tb s 2 1 + sTz/2
1 Gate
0
Tz = (Atw) * Tw
Velmin Gmin
Dturb
DT01_005
7.19 SHAF25
Torsional Shaft Model for 25 Masses
STATEs # Description
K Slip at mass 1
K+1 Slip at mass 2
K+2 Slip at mass 3
K+3 Slip at mass 4
K+4 Slip at mass 5
K+5 Slip at mass 6
K+6 Slip at mass 7
K+7 Slip at mass 8
K+8 Slip at mass 9
K+9 Slip at mass 10
K+10 Slip at mass 11
K+11 Slip at mass 12
K+12 Slip at mass 13
K+13 Slip at mass 14
K+14 Slip at mass 15
K+15 Slip at mass 16
K+16 Slip at mass 17
K+17 Slip at mass 18
K+18 Slip at mass 19
K+19 Slip at mass 20
K+20 Slip at mass 21
K+21 Slip at mass 22
K+22 Slip at mass 23
K+23 Slip at mass 24
K+24 Slip at mass 25
VARs # Description
L T electrical of exciter
L+1 T shaft 1-2
L+2 T shaft 2-3
L+3 T shaft 3-4
L+4 T shaft 4-5
L+5 T shaft 5-6
L+6 T shaft 6-7
L+7 T shaft 7-8
L+8 T shaft 8-9
L+9 T shaft 9-10
L+10 T shaft 10-11
L+11 T shaft 11-12
L+12 T shaft 12-13
L+13 T shaft 13-14
L+14 T shaft 14-15
L+15 T shaft 15-16
L+16 T shaft 16-17
L+17 T shaft 17-18
L+18 T shaft 18-19
L+19 T shaft 19-20
L+20 T shaft 20-21
L+21 T shaft 21-22
L+22 T shaft 22-23
L+23 T shaft 23-24
L+24 T shaft 24-25
L+25 Angle at mass 1
L+26 Angle at mass 2
L+27 Angle at mass 3
L+28 Angle at mass 4
L+29 Angle at mass 5
L+30 Angle at mass 6
L+31 Angle at mass 7
L+32 Angle at mass 8
L+33 Angle at mass 9
L+34 Angle at mass 10
VARs # Description
L+35 Angle at mass 11
L+36 Angle at mass 12
L+37 Angle at mass 13
L+38 Angle at mass 14
L+39 Angle at mass 15
L+40 Angle at mass 16
L+41 Angle at mass 17
L+42 Angle at mass 18
L+43 Angle at mass 19
L+44 Angle at mass 20
L+45 Angle at mass 21
L+46 Angle at mass 22
L+47 Angle at mass 23
L+48 Angle at mass 24
L+49 Angle at mass 25
L+50
L+51
L+52
. Working storage locations
.
.
L+74
7.20 TGOV1
Steam Turbine-Governor
J+2 VMAX1
J+3 VMIN1
J+4 T2 (sec)2
J+6 Dt1
1 V
MAX, VMIN, Dt are in per unit on generator base.
2 T /T = high-pressure fraction.
2 3
3 T = reheater time constant.
3
STATEs # Description
K Valve opening
K+1 Turbine power
VARs # Description
L Reference
VMAX
+ 1 1 1 + T2s +
Reference
VAR(L) PMECH
R 1 + T1s 1 + T3s
VMIN
Dt
SPEED
7.21 TGOV2
Steam Turbine-Governor With Fast Valving
STATEs # Description
K Throttle
K+1 Reheat pressure
K+2 Reheat power
K+3 Intercept valve position, V
VARs # Description
L Speed reference
L+1 Fast valving initial time, TI
K
VMAX
+
+ 1 1 1-K v +
Reference PMECH
VAR(L) R 1 + T1s 1 + T3s 1 + Tts
VMIN
Dt
SPEED
TC
7.22 TGOV3
Modified IEEE Type 1 Speed-Governing Model With Fast Valving
J+7 PMIN
J+8 T4 (sec)
J+9 K1
STATEs # Description
K First governor integrator
K+1 Governor output
K+2 First turbine integrator
K+3 Second turbine integrator
K+4 Third turbine integrator
K+5 Intercept valve position, v
VARs # Description
L Reference
L+1 Fast valving initial time, TI
+ +
PMECH
+ +
Po K1 PRMAX K2 K3
+ Uo PMAX
0.8
K(1 + sT2) 1 1
Flow
1 1 + 1
SPEED V
(1 + sT1) T3 S 1 + sT4 T5s 1 + sT6
0 0.3
Uc PMIN Intercept Valve
Position
Siemens Energy, Inc., Power Technologies International
TC
PSSE 32.0.5
PSSE 32.0.5 Turbine-Governor Model Data Sheets
PSSE Model Library TGOV4
7.23 TGOV4
Modified IEEE Type 1 Speed-Governing Model With PLU and EVA
J+4 Uo
J+5 Uc (< 0)
J+6 KCAL
J+7 T4 (sec)
J+8 K1
J+9 T5 (> 0) (sec)
J+10 K2
J+11 T6 (sec)
J+12 PRMAX
J+13 KP
J+14 KI
J+15 TFuel (sec)
J+16 TFD1 (sec)
J+17 TFD2 (sec)
J+18 Kb
J+19 Cb (> 0) (sec)
J+20 TIV (> 0) (sec)
J+21 UOIV
J+22 UCIV
J+23 R (>0)
STATEs # Description
K CV speed controller integrator
K+1 CV #1 valve position
K+2 CV #2 valve position
K+3 CV #3 valve position
K+4 CV #4 valve position
K+5 HP steam flow ( m SHP )
VARs # Description
L Load reference
L+1 Boiler pressure reference
L+2 IV load reference
L+3 Boiler pressure
L+4 CV flow area
L+5 IV flow area
L+6 KCV
L+7 KIV
L+8 CV position demand characteristic, K
L+9 CV position demand characteristic, A
L+10 IV position demand characteristic, K
L+11 IV position demand characteristic, A
L+12 CV valve characteristic, K
L+13 CV valve characteristic, A
L+14 IV valve characteristic, K
VARs # Description
L+15 IV valve characteristic, A
L+16 Generator current (pu on machine base)
L+17 PLU rate output signal
L+18 Time when TIMER initialized
L+19 PLU unbalance signal
L+20 EVA unbalance signal
L+21 EVA rate output signal
L+22 Time of CV signal to close
L+23 Time of IV signal to close
L+24 Time when CVs closed
L+25 Time when IVs closed
Uo 1
+ 1 Pmech
1
T3 s
K1 + +
Uc 0
m SIP +
Uo 1
K2
+ 1 1
1 K 1 K2
T3 s
PRMAX m
+ SIP
Uc 0 + m
K(1 + sT2) 1 + 1 1 SLP
KC Uo 1 KCAL
(1 + sT1) 1 + sT4 T 5s 1 + sT6
+ + 1 + + Reheat
1 IV Flow Area
T3 Pressure
s Flow + +
Load
Reference Area
Uc 0 Boiler
1 Pressure
Uo
+ 1 1
T3 s 1 1
s s
Uc 0 UCIV UCIV
K 1 1 1 +
I
K + ------ 1 + sTFuel 1 + sTFD1 1 + sTFD2
p s
KIV
1
R
+
IV Load +
Reference
TGOV4
+
7-69
Offset
TGOV4
Turbine-Governor Model Data Sheets
7-70
TIV1 IV#1
AND
OR
TIV2 IV#2
EVA > Y
Unbalance
Level
+
Reheat Pressure
Siemens Energy, Inc., Power Technologies International
TCV1 CV#1
AND LATCH
TCV3 CV#3
+
PLU
Y
> Unbalance
Level
TCV4 CV#4
N
7.24 TGOV5
IEEE Type 1 Speed-Governing Model Modified to Include Boiler Controls
J+2 T2 (sec)
J+3 T3 (>0) (sec)
J+4 Uo
J+5 Uc (<0)
J+6 VMAX
J+7 VMIN
J+8 T4 (sec)
J+9 K1
J+10 K2
J+11 T5 (sec)
J+12 K3
J+13 K4
J+14 T6 (sec)
J+15 K5
J+16 K6
J+17 T7 (sec)
J+18 K7
J+19 K8
J+20 K9
J+21 K10
J+22 K11
J+27 RMIN
J+28 LMAX
J+29 LMIN
J+30 C1
J+31 C2
J+32 C3
J+33 B
J+34 CB (>0) (sec)
J+35 KI
J+36 TI (sec)
J+37 TR (sec)
J+38 TR1 (sec)
J+39 CMAX
J+40 CMIN
J+41 TD (sec)
J+42 TF (sec)
J+43 TW (sec)
J+44 Psp (initial) (>0)
J+45 TMW (sec)
J+46 KL (0.0 or 1.0)
J+47 KMW (0.0 or 1.0)
J+48 PE (pu pressure)
STATEs # Description
K First governor integrator
K+1 Valve area
K+2 First turbine integrator, m s
STATEs # Description
K+4 Third turbine integrator
K+5 Fourth turbine integrator
K+6 Po
K+7 Drum pressure, PD
K+8 First controller integrator
K+9 Second controller integrator
K+10 Fuel
K+11 Water walls
K+12 First delay integrator
K+13 Second delay integrator
K+14 Third delay integrator
K+14 Fourth delay integrator
K+16 Measured MW
VARs # Description
L Internal memory
L+1 Pressure setpoint, Psp
L+2 MW demand
L+3 Pressure error, PE
L+4 Throttle pressure, PT
L+5 C2 VAR
L+6 C3 VAR
+ + + PMECHHP
PM1
+ + +
K1 K3 K5 K7
VMAX
Uo
K(1 + sT )
2 1 1 1 ms 1 1 1
x
SPEEDHP 1 + sT1 T3 S 1 + sT4 1 + sT5 1 + sT6 1 + sT7
+ Uc
Po VMIN PT K2 K4 K6 K8
+ + +
PELEC + PMECHLP
+ +
f
PM2
KMW
B 1 + sTMW LMAX
RMAX
+ + + 1 Po
K14
MW Desired S
Demand MW RMIN
C2 + x LMIN
K13 +
PE KL
K12 (Pressure Error)
+
Dead Band m s
PSP
x
PE
+ PE x
Po
C3
PSP x
CMAX
Controller +
KI(1 + sTI) (1 + sTR)
PT
s(1 + sTR1) PE
CMAX
PD + K9 + C
1
1
CBs
Fuel Dynamics
+ e-sTD +
m s
(1 + sTF) (1 + sTW)
+
+
K11 K10
Desired MW
7.25 TURCZT
Czech Hydro and Steam Governor
STATEs # Description
K Transducer
K+1 PI regulator
K+2 Hydro converter
K+3 Regulation valves
K+4 Hydro unit/HP part
K+5 Reheater
VARs # Description
L NTREF
L+1 dFREF
L+2 YREG
Frequency Bias
Power Regulator
fMAX
+
BSFREQ fDEAD KKOR KP
fMIN Hydro Converter
+
1 +
dFREF NTREF + NTMAX YREG
1 + sTEHP
+
1
SBASE 1
PELEC KM sTI
MBASE 1 + sTC
sDEAD KSTAT
SPEED
Governor
Turbine
7.26 TWDM1T
Tail Water Depression Hydro Governor Model 1
STATEs # Description
K e, filter output
K+1 e, filter output
K+2 c, desired Gate
K+3 g, gate opening
K+4 q, turbine flow
K+5 GMAX state
VARs # Description
L NREF, speed reference
L+1 h, turbine head
L+2 Internal memory
L+3 Internal memory
L+4 Measured frequency rate
+ 1 1 1 1
NREF 1 + Trs
1 + Tfs e rTr s c 1 + Tgs g
+
SPEED VELM CLOSE GATE MIN
+
1 + +
X X At 1.0 PMECH
h TWs q
+
q 0
1 qNL
Dturb
SPEED
Tail Water Depression Model 1
f < F2
Trip Tail
1 Water
FREQ sf < sF2 TF2 LATCH Depression
1 + sTft f
Measured Frequency
7.27 TWDM2T
Tail Water Depression Hydro Governor Model 2
J+4 KD
J+5 TA (sec) (> 0)
J+6 TB (sec) (> 0)
J+7 VELMX (pu/sec)
J+8 VELMN (pu/sec) (> 0)
J+9 GATMX (pu)
J+10 GATMN (pu)
J+11 TW (sec) (> 0)
J+12 At, turbine gain
J+13 qNL, no power flow
STATEs # Description
K Measured electrical power deviation
K+1 PID controller
K+2 First lag
K+3 Second lag
K+4 Rate
K+5 Rate
K+6 q, turbine flow
K+7 Measured frequency
VARs # Description
L PREF, electrical power reference
L+1 h, turbine head
L+2 Internal memory
L+3 Internal memory
L+4 Measured frequency rate
IBUS, TWDM2T, ID, ICON (M) and ICON (M+1), CON(J) to CON(J+21) /
PREF
+
PELECT
KP
Reg
1 + sTREG
TWD Lock MAX VELMX GATMX
+ +
KI + 1 1 1
W LOGIC
SPEED s (1 + TAs)2 1 + TBs s
+
Two
TWD Lock MIN Trip VELMN GATMN
sKD
1 + +
X X At 1.0 PMECH
h TWs q
+
q 1 qNL 0
f < F2
Trip Tail
1 Water
FREQ sf < sF2 TF2 LATCH Depression
1 + sTft f
Measured Frequency
7.28 URCSCT
Combined Cycle on Single Shaft
Note: CON(J+37) and CON(J+38) of the URCST model (which are PMAX and PMIN values corre-
sponding to the IEEEG1 model) are the pu on steam turbine MW rating specified in CON(J+51).
STATEs # Description
K
Refer to model GAST2A STATEs
K+12
K+13
Refer to model IEEEG1 STATEs
K+18
VARs # Description
L
Refer to model GAST2A VARs
L+3
L+4
Refer to model IEEEG1 VARs
L+5
7.29 URGS3T
WECC Gas Turbine Model
STATEs # Description
K Governor output
K+1 Engine output
K+2 Exhaust temperature delay
K+3 Load limit
K+4 Governor lead/lag
VARs # Description
L Reference
L+1 Deadband, In
L+2 Deadband, Out
L+3 Deadband2, In
1
----------------------
1 + sT
ltr
If (Dv > Linc), then Rlim = Ltrat +
else, Rlim = Rmax Dv
Vmax
Rlim
PGV
+ Ka 1 + sT + 1 + 1 + asT +
Siemens Energy, Inc., Power Technologies International
err LV 2 +
Pref 4 --------- ---------------------- Pmech
------------------------------- sT
db1 1 + sT Gate 1 1 + bsT db2
5 2
GV
Fidle
Vmin
1 + + 1
---- Fidle Kt -------------------
R 1 + sT
3
+
Lmax
Speed Dturb
7.30 WEHGOV
Woodward Electric Hydro Governor Model
J R-PERM-GATE1
J+1 R-PERM-PE1
J+2 TPE (sec)
J+3 Kp
J+4 KI
J+5 KD
J+6 TD (sec)
J+7 TP (sec)
J+8 TDV (sec)
J+9 Tg (sec)
J+10 GTMXOP
J+11 GTMXCL
J+12 GMAX
J+13 GMIN
J+14 DTURB
J+15 TW (sec)
J+16 Speed Dead Band (DBAND)
J+17 DPV
J+18 DICN
J+19 GATE 1
J+20 GATE 2
J+21 GATE 3
J+22 GATE 4
J+23 GATE 5
STATEs # Description
K Pilot valve position
K+1 Distribution valve position
K+2 Gate position
K+3 Turbine flow
K+4 Derivative controller
K+5 Integral controller
K+6 PE transducer output
VARs # Description
L Reference
L+1 Turbine head
L+2 Controller output
L+3 Gate position
N or Derivative Control
Speed (I)
In KDS Out
1 + sTD Pilot Valve Distribution Valve
GMAX + DPV GTMXOP*Tg
Reference +
VAR(L) + ERR + + 1 + 1
KP
1 + sTP
Siemens Energy, Inc., Power Technologies International
1 sTDV
+ VAR(L+2)
0 STATE(K) STATE(K+1)
Dead Band GMAX + DICN
ICON(M)=1 GMIN DDPV GTMXCL*Tg
CON(J+16)
ICON(M)=0 KI
R - PERM - PE s STATE(K+5) ICON(M)=1
1 + sTPE GMAX
GMIN DICN
g, Gate Position 1 1
R PERM GATE s
SBASE ICON(M)=0 Tg
MBASE(I) STATE(K+2)
or VAR(L+3) GMIN
PELEC(I)
PSSE 32.0.5
PSSE Model Library
PSSE 32.0.5
Siemens Energy, Inc., Power Technologies International
Gate Flow
Steady-State
Position, g Flow, qss Turbine Flow, q
Gate
N
q
qss
DTURB
X
Turbine Head,
h = VAR(L+1)
+ g X
Ho = 1
Pmss
1 Pmss
Turbine Flow +
Tws X
PMECH
STATE(K+3) Flow
WEHGOV
7-93
Turbine-Governor Model Data Sheets PSSE 32.0.5
WESGOV
PSS E Model Library
7.31 WESGOV
Westinghouse Digital Governor for Gas Turbine
STATEs # Description
K PE transducer
K+1 Valve position
K+2 PMECH
VARs # Description
L References
L+1 PI output
L+2 Integration for PI
L+3 Integration for PI
L+4 PE transducer output
L+5 Speed measurement
*
Speed KP +
Reference + 1
(1 + T1s) (1 + T2s)
PMECH
1 +
1 ** Droop
PELEC sTI
1 + sTpe
Digital Control***
7.32 WPIDHY
Woodward PID Hydro Governor
J+1 REG1
J+2 KP
J+3 KI
J+4 KD
J+5 TA (>0) (sec)
J+6 TB (>0) (sec)
J+7 VELMX
J+8 VELMN (<0)
J+9 GATMX
J+10 GATMN
J+11 TW (>0) (sec)
J+12 PMAX
J+13 PMIN
J+14 D
J+15 G0
J+16 G1
J+17 P1
J+18 G2
J+19 P2
J+20 P3
1 REG has to be input as a negative value because the input to
REG block is PELEC - PREF instead of PREF - PELEC.
STATEs # Description
K Measured electrical power deviation
K+1 PID controller
K+2 First lag
K+3 Second lag
K+4 Rate
K+5 Gate
K+6 Mechanical power
VAR # Description
L Electrical power reference
(1, P3)
(MBASE)
(G2, P2)
(G1, P1)
PREF
+
PELEC
REG
1 + sTREG
KP
PMECH
7.33 WSHYDD
WECC Double-Derivative Hydro Governor
J+18 GV2
J+19 PGV2
J+20 GV3
J+21 PGV3
J+22 GV4
J+25 PGV5
J+26 Aturb
J+27 Bturb (> 0)
J+28 Tturb (> 0) (sec)
J+29 Trate
STATEs # Description
K Output, Td
K+1 K1 state
K+2 K2 first
K+3 K2 second
K+4 CV
K+5 Valve speed
K+6 Gate position
K+7 Generator power
K+8 Turbine
VARs # Description
L Reference
L+1 Deadband1 In
REF
+ +
err 1 - sK
SW ------------------- 1 + K
1 + sT
----------------- ------P-
db1 D 1 + sT f S
(Speed)
+
Tt = 0
2
s KD 1 PE
-------------------------
- R -----------------
2 1 + sT PELEC
1 + sT t
f SW
(Tt > 0)
Siemens Energy, Inc., Power Technologies International
VELOPEN PMAX
VELCLOSE PMIN
7.34 WSHYGP
WECC GP Hydro Governor Plus Turbine
J+3 KI
J+4 Tf (sec)
J+5 KD
J+6 KP
J+7 R
J+8 Tt
J+9 KG
J+10 TP (sec)
J+11 VELOPEN
J+12 VELCLOSE
J+13 PMAX
J+14 PMIN
J+15 db2
J+16 GV1
J+17 PGV1
J+18 GV2
J+19 PGV2
J+20 GV3
J+21 PGV3
J+22 GV4
STATEs # Description
K Output, Td
K+1 Integrator state
K+2 Derivative state
K+3 Valve speed
K+4 Gate position
K+5 Generator power
K+6 Turbine
VARs # Description
L Reference
L+1 Deadband1 In
KP
PREF
+ +
SW
err 1 K + CV
(Speed) ------------------ I
------
db1 1 + sT d
S
+
(Tt = 0)
sK D
-----------------
1 + sT f
1 PE
R -----------------
1 + sT PELEC
t
(Tt > 0)
VELOPEN PMAX
VELCLOSE PMIN
7.35 WSIEG1
WECC Modified IEEE Type 1 Speed-Governing Model
J+24 PGV1
J+25 GV2
J+26 PGV2
J+27 GV3
J+28 PGV3
J+29 GV4
J+30 PGV4
J+31 GV5
J+32 PGV5
J+33 IBLOCK
STATEs # Description
K 1st governor integrator
K+1 Governor output
K+2 1st turbine integrator
K+3 2nd turbine integrator
K+4 3rd turbine integrator
K+5 4th turbine integrator
VARs # Description
L Reference
L+1 Internal memory
L+2 Deadband1 in
L+3 Deadband1 out
L+4 PMAX
L+5 PMIN
L+6 Deadband2 in
L+7 Deadband2 out
At initialization:
GV0
PMAX
+ Uo
err 1 + sT2 1 1 GV PGV
K
db1 1 + sT1 T3 S GVdes db2 NGV
CV
Uc
PMIN
+ + +
PMECHHP
PM1
+ + +
K1 K3 K5 K7
1 1 1 1
1 + sT5
1 + sT4 1 + sT6 1 + sT7
K2 K4 K6 K8
+ + +
+ + +
PMECHLP
PM2
Model Description
LCFB1 Turbine load controller model
8.1 LCFB1
Turbine Load Controller Model
PELEC
This model uses CONs starting with #_______ J,
reference
and STATEs starting with #_______ K, LCFB1
SPEED
and VARs starting with #_______ L,
#_______
and ICONs starting with M.
STATEs # Description
K Measured power
K+1 Integrator
VARs # Description
L Deadband input
L+1 Deadband output
L+2 Pref 0
This model can be used with the following turbine governor models.
Model Description
ACMTBLU1, ACMTOWU1, ACMTZNU1, User written performance based model of
ACMTARU1, ACMTALU1 single phase air conditioner motor.
CIM5BL, CIM5OW, CIM5ZN, CIM5AR, CIM5AL Induction motor model.
CIM6BL, CIM6OW, CIM6ZN, CIM6AR, CIM6AL Induction motor model.
CIMWBL, CIMWOW, CIMWZN, CIMWAR, CIMWAL Induction motor model (WECC).
CLODBL, CLODOW, CLODZN, CLODAR, CLODAL Complex load model.
CMLDBLU1, CMLDOWU1, CMLDZNU1,
User-written composite load model
CMLDARU1, CMLDALU1
EXTLBL, EXTLOW, EXTLZN, EXTLAR, EXTLAL Extended-term load reset model.
IEELBL, IEELOW, IEELZN, IEELAR, IEELAL IEEE load model.
LDFRBL, LDFROW, LDFRZN, LDFRAR, LDFRAL Load frequency model.
4 The motor run state is characterized by an exponential characteristic. The run characteristic
is divided into two states as a function of bus voltage, State 1 for Bus voltage Vbrk, and State
2 for Vstall < Bus Voltage < Vbrk.
State 0, corresponds to 1.0 p.u. Bus voltage
P0=1-Kp1*(1-Vbrk)**Np1
Q0=((1-CompPF**2)/CompPF)-Kq1*(1-Vbrk)**Nq1
State 1 for Bus voltage Vbrk
P=P0+Kp1*(V-Vbrk)**Np1
Q=Q0+Kq1*(V-Vbrk)**Nq1
State 2 for Vstall < Bus Voltage < Vbrk
P=P0+Kp2*(Vbrk-V)**Np2
Q=Q0+Kq2*(Vbrk-V)**Nq2
5 See Compressor Unit Model Structure, below.
Motor A once stalled remains stalled.
Motor B can restart if the voltage recovers above Vrst level.
Frst is the fraction of motors that are capable of restart.
6 Frequency dependency of the load is defined by following characteristics:
P(f)=P*(1+CmpKpf*f)
Q(f)=Q*(1+CmpKqf*f/(1-CompPF**2))
7 See Thermal Relay Model, below.
Thermal relay is modelled by the following characteristics:
If Th2t is equal to zero or if Th1t is greater than or equal to Th2t, all motors are tripped
instantaneously when temperature reaches Th1t.
STATEs # Description
K Bus Voltage (pu)
K+1 Bus Frequency (pu)
K+2 Compressor Motor A Temperature
K+3 Compressor Motor B Temperature
K+4 U/V Relay Timer 1
K+5 U/V Relay Timer 2
K+6 Motor A Stall Timer
K+7 Motor B Stall Timer
K+8 Motor B Restart Timer
VARs # Description
L Bus Voltage (pu)
L+1 Bus Frequency (pu)
L+2 Aggregated AC unit real power (MW)
L+3 Aggregated AC unit reactive power (MVAr)
L+4 Aggregated AC unit current (pu on system MVA base)
Terminal current component in phase with voltage (in pu on Motor MVA
L+5
Base)
VARs # Description
L+6 Terminal current component lagging voltage (in pu on Motor MVA Base)
L+7 Terminal current comp on network real axis on system MVA base (pu)
L+8 Terminal current comp on network imag axis on system MVA base (pu)
L+9 Motor A and B Initial Temperature
L+10 Fraction of motors not tripped by U/V Relay - gain Kuv
Reserved
Value Description
ICONs
Motor A Run/Stall Status, Run=1,
N
Stall=0
Motor B Run, Restart, Stall Status,
N+1
Run=1, Restart=2, Stall=0
Under Voltage Relay Trip Status, Non-
N+2
Trip=1, Trip=0
Under Voltage Relay First Pick Up
N+3
Flag, Becomes 0 on Pick Up
Reserved
Value Description
ICONs
Under Voltage Relay Second Pick Up
N+4
Flag, Becomes 0 on Pick Up
Thermal Relay Trip 1 Status for Motor
N+5
A, Non-trip=1. Trip=0
Thermal Relay Trip 2 Status for Motor
N+6
A, Non-trip=1. Trip=0
Thermal Relay Trip 1 Status for Motor
N+7
B, Non-trip=1. Trip=0
Thermal Relay Trip 2 Status for Motor
N+8
B, Non-trip=1. Trip=0
Contactors Started to Drop Out Flag,
N+9 Not Started to Drop Out=1, Started to
Drop Out=0
All Contactors Dropped out Flag, All
N+10
Not Dropped Out=1, All Dropped Out=0
Contactors Started to Reclose Flag,
N+11 Not Started to Reclose=1, Started to
Reclose=0
All Contactors Reclosed Flag, All Not
N+12
Reclosed=1, All Reclosed=0
Motor A Stall Relay Pick Up Flag,
N+13
Becomes 0 on Pick Up
Motor B Stall Relay Pick Up Flag,
N+14
Becomes 0 on Pick Up
Motor B Restart Relay Pick Up Flag,
N+15
Becomes 0 on Pick Up
Real Power
6
4 S TALL
Real Power (per uni t)
STALL RUN
1
0
0 0.2 0. 4 0.6 0. 8 1 1.2
V oltage (per unit)
Reacti ve Power
6
5
Reactive Power (per unit)
4 STALL
STA LL
1
RUN
0
0 0. 2 0.4 0.6 0.8 1 1.2
Voltage (per unit)
[1] AC Unit Model specifications", WECC Load Modeling task Force, April 2008
J+2 Xm > 0
J+3 R1 > 0
J+4 X1 > 0
J+10 S(E2)
J+11 MBASE2
J+12 PMULT
J+13 H (inertia, per unit motor base)
J+14 VI (pu)3
J+15 TI (cycles)4
J+16 TB (cycles)
J+17 D (load damping factor)
Tnom, Load torque at 1 pu speed
J+18
(used for motor starting only) (0)
1 To model single cage motor: set R = X = 0.
2 2
2 When MBASE = 0, motor MVA base = PMULT x MW load. When
MBASE > 0, motor MVA base = MBASE.
3 V is the per unit voltage level below which the relay to trip the
I
motor will begin timing. To disable relay, set VI = 0.
4 T is the time in cycles for which the voltage must remain below
I
the threshold for the relay to trip. TB is the breaker delay time
cycles.
K+2 Eq
K+3 Ed
K+4 speed (pu)
K+5 Angle deviation
Reserved
Value Description
ICONs
N Relay action code
N+1 Relay trip flag
N+2 Breaker action code
N+3 Breaker trip flag
LID is an explicit load identifier or may be for application to loads of any ID associated with the
subsystem type.
Type 1 Type 2
RA + jXA RA + jXA jX1
J+8 S(E1)
J+9 E2
J+10 S(E2)
J+11 MBASE2
J+12 PMULT
J+13 H (inertia, per unit motor base)
J+14 VI (pu)3
J+15 TI (cycles)4
J+16 TB (cycles)
J+17 A
J+18 B
J+19 D
J+20 E
J+21 C0
Tnom, Load torque at 1 pu speed (used
J+22
for motor starting only) ( 0)
1 To model single cage motor: set R = X = 0.
2 2
L+6 ID
L+7 Motor current (pu motor base)
L+8 Relay trip time
L+9 Breaker trip time
L+10 MVA rating
L+11 TL (pu load torque)
1 Load torque, T = T (A2 +B + C + DE)
L o
2 For motor starting, T=T
nom is specified by the user in CON (J+22).
For motor online studies, T=To is calculated in the code during
initialization and stored in VAR (L+4).
Reserved
Value Description
ICONs
N Relay action code
N+1 Relay trip flag
N+2 Breaker action code
N+3 Breaker trip flag
Type 1 Type 2
RA + jXA RA + jXA jX1
J+2 Xm > 0
J+3 R1 > 0
J+4 X1 > 0
J+10 S(E2)
J+11 MBASE2
J+12 PMULT
J+13 H (inertia, per unit motor base)
J+14 VI (pu)3
J+15 TI (cycles)4
J+16 TB (cycles)
J+17 A
J+18 B
J+19 D
J+20 E
1 To model single cage motor: set R = X = 0.
2 2
2 When MBASE = 0, motor MVA base = PMULT x MW load. When
MBASE > 0, motor MVA base = MBASE.
3 V is the per unit voltage level below which the relay to trip the
I
motor will begin timing. To disable relay, set VI = 0.
4 T is the time in cycles for which the voltage must remain below the
I
threshold for the relay to trip. TB is the breaker delay time cycles.
L+5 IQ
L+6 ID
L+7 Motor current (pu motor base)
L+8 Relay trip time
L+9 Breaker trip time
L+10 MVA rating
L+11 Co
1 Load torque T = T (A2 +B + C + DE)
L o o
where Co = 1 - Ao2 - Bo - DoE.
2 This model cannot be used for motor starting studies. T is calculated
o
in the code during initialization and stored in VAR (L+4).
Reserved
Value Description
ICONs
N Relay action code
N+1 Relay trip flag
N+2 Breaker action code
N+3 Breaker trip flag
Type 1 Type 2
RA + jXA RA + jXA jX1
Reserved
Value Description
ICON
N Service status memory
P + jQ
Tap
R + jX
----------------
Po
Po = Load MW in pu on system base
K
I I Constant P = P RO V P
M M
V
MVA Q = Q RO V 2
V
J+1
Substation shunt B (pu on Load
MVA base)
J+2
Rfdr - Feeder R (pu on Load MVA
base)
Xfdr - Feeder X (pu on Load MVA
J+3
base)2
J+4
Fb - Fraction of Feeder
Compensation at substation end
Xxf - Transformer Reactance - pu
J+5
on load MVA base3
J+6
Tfixhs - High side fixed transformer
tap
J+7
Tfixls - Low side fixed transformer
tap
J+8 LTC - LTC flag (1 active, 0 inactive)
J+9 Tmin - LTC min tap (on low side)
J+10 Tmax - LTC max tap (on low side)
J+11 Step - LTC Tstep (on low side)
J+12 Vmin - LTC Vmin tap (low side pu)
J+13 Vmax - LTC Vmax tap (low side pu)
J+14 TD - LTC Control time delay (sec)
J+15
TC - LTC Tap adjustment time
delay (sec)
J+16
Rcmp - LTC Rcomp (pu on load
MVA base)
J+17
Xcmp - LTC Xcomp (pu on load
MVA base)
J+18 FmA - Motor A Fraction
J+19 FmB - Motor B Fraction
J+20 FmC - Motor C Fraction
J+21 FmD - Motor D Fraction
J+22 Fel - Electronic Load Fraction4
J+23 PFel - PF of Electronic Loads
J+24
Vd1 - Voltage at which elect. loads
start to drop
J+25
Vd2 - Voltage at which all elect.load
have dropped
J+26 PFs - Static Load Power Factor
J+27
P1e - P1 exponent5
J+28 P1c - P1 coefficient
J+29 P2e - P2 exponent
J+30 P2c - P2 coefficient
J+31 Pfrq - Frequency sensitivity
J+32 Q1e - Q1 exponent
J+33 Q1c - Q1 coefficient
J+34 Q2e - Q2 exponent
J+35 Q2c - Q2 coefficient
J+36 Qfrq - Frequency sensitivity
J+37 MtypA - Motor type6
J+38
LFmA - Loading factor (MW/MVA
rating)
J+39 RaA - Stator resistance
J+40 LsA - Synchronous reactance
J+41 LpA - Transient reactance
J+42 LppA - Sub-transient reactance
J+43
TpoA - Transient open circuit time
constant
J+44
TppoA - Sub-transient open circuit
time constant
J+45 HA - Inertia constant
J+46 etrqA - Torque speed exponent
J+47 Vtr1A - U/V Trip1 V (pu)
J+48 Ttr1A - U/V Trip1 Time (sec)
J+49 Ftr1A - U/V Trip1 fraction
J+50 Vrc1A - U/V Trip1 reclose V (pu)
J+51
Trc1A - U/V Trip1 reclose Time
(sec)
J+52 Vtr2A - U/V Trip2 V (pu)
J+53 Ttr2A - U/V Trip2 Time (sec)
J+54 Ftr2A - U/V Trip2 fraction
J+55 Vrc2A - U/V Trip2 reclose V (pu)
J+56
Trc2A - U/V Trip2 reclose Time
(sec)
J+57 MtypB - Motor type
J+58
LFmB - Loading factor (MW/MVA
rating)
J+59 RaB - Stator resistance
J+60 LsB - Synchronous reactance
J+61 LpB - Transient reactance
J+62 LppB - Sub-transient reactance
J+63
TpoB - Transient open circuit time
constant
J+64
TppoB - Sub-transient open circuit
time constant
J+65 HB - Inertia constant
J+66 etrqB - Torque speed exponent
J+67 Vtr1B - U/V Trip1 V (pu)
J+68 Ttr1B - U/V Trip1 Time (sec)
J+71
Trc1B - U/V Trip1 reclose Time
(sec)
J+72 Vtr2B - U/V Trip2 V (pu)
J+73 Ttr2B - U/V Trip2 Time (sec)
J+74 Ftr2B - U/V Trip2 fraction
J+75 Vrc2B - U/V Trip2 reclose V (pu)
J+76
Trc2B - U/V Trip2 reclose Time
(sec)
J+77 MtypC - Motor type
J+78
LFmC - Loading factor (MW/MVA
rating)
J+79 RaC - Stator resistance
J+80 LsC - Synchronous reactance
J+81 LpC - Transient reactance
J+82 LppC - Sub-transient reactance
J+83
TpoC - Transient open circuit time
constant
J+84
TppoC - Sub-transient open circuit
time constant
J+85 HC - Inertia constant
J+86 etrqC - Torque speed exponent
J+87 Vtr1C - U/V Trip1 V (pu)
J+88 Ttr1C - U/V Trip1 Time (sec)
J+89 Ftr1C - U/V Trip1 fraction
J+90 Vrc1C - U/V Trip1 reclose V (pu)
J+91
Trc1C - U/V Trip1 reclose Time
(sec)
J+92 Vtr2C - U/V Trip2 V (pu)
J+93 Ttr2C - U/V Trip2 Time (sec)
J+94 Ftr2C - U/V Trip2 fraction
J+95 Vrc2C - U/V Trip2 reclose V (pu)
J+96
Trc2C - U/V Trip2 reclose Time
(sec)
J+97 Tstall - stall delay (sec)7
J+98 Trestart - restart delay (sec)
J+99
Tv - voltage input time
constant(sec)
J+100
Tf - frequency input time
constant(sec)
CompLF - compressor load factor,
J+101
p.u. of rated power8
J+102
CompPF - compressor power factor
at 1.0 p.u. voltage
J+103
Vstall - compressor stall voltage at
base condition (p.u.)
Rstall - compressor motor res. with
J+104
1.0 p.u. current9
J+105
Xstall - compressor motor stall
reactance - unsat.
LFadj - Load factor adjustment to
J+106
the stall voltage10
Kp1 - real power constant for
J+107
running state 111
J+108
Np1 - real power exponent for
running state 1
J+109
Kq1 - reactive power constant for
running state 1
J+110
Nq1 - reactive power exponent for
running state 1
J+111
Kp2 - real power constant for
running state 2
J+112
Np2 - real power exponent for
running state 2
J+113
Kq2 - reactive power constant for
running state 2
J+114
Nq2 - reactive power exponent for
running state 2
J+115
Vbrk - compressor motor "break-
down" voltage (p.u.)
J+116
Frst - fraction of motors capable of
restart
J+117
Vrst - voltage at which motors can
restart (p.u.)
CmpKpf - real power constant for
J+118
freq dependency12
J+119
CmpKqf - reactive power constnt for
freq dependency
J+120
Vc1off - Voltage 1 at which
contactors start dropping out (p.u.)
J+121
Vc2off - Voltage 2 at which all
contactors drop out (p.u.)
J+122
Vc1on - Voltage 1 at which all
contactors reclose (p.u.)
J+123
Vc2on - Voltage 2 at which
contactors start reclosing (p.u.)
Tth - compressor motor heating
J+124
time constant(sec)13
J+125
Th1t - temp at which comp. motor
begin tripping
J+126
Th2t - temp at which comp. all
motors are tripped
J+127
Fuvr - fraction of comp. motors with
U/V relays
J+128 UVtr1 - 1st voltage pick-up (p.u.)
J+129
Ttr1 - 1st definite time voltage pick-
up (sec)
J+130 UVtr2 - 2nd voltage pick-up (p.u.)
J+131
Ttr2 - 2nd definite time voltage pick-
up (sec)
4 If sum of load fractions FmA, FmB, FmC, FmD, Fel is <1, remainder
is static load;
If sum of fractions FmA, FmB, FmC, FmD, Fel is >1, fractions are
normalized to 1 and there will be no static load
10 Lfadj factor is used to update the Vstall and Vbrk as defined below:
Vstall(adj)=Vstall*(1+Lfadj*(CompLF-1))
Vbrk(adj)=Vbrk*(1+Lfadj*(CompLF-1))
K Motor A: E'q
K+1 Motor A: E'd
K+2 Motor A: E"q
K+3 Motor A: E"d
K+4 Motor A: speed deviation (pu)
K+5 Motor A: angle deviation
K+6 Motor B: E'q
K+7 Motor B: E'd
K+8 Motor B: E"q
K+9 Motor B: E"d
K+10 Motor B: speed deviation (pu)
K+11 Motor B: angle deviation
K+12 Motor C:: E'q
K+13 Motor C:: E'd
K+14 Motor C:: E"q
K+15 Motor C:: E"d
K+16 Motor C:: speed deviation (pu)
K+17 Motor C: angle deviation
K+20
Motor D: non-restartable compressor motor A
temperature
K+21
Motor D: restartable compressor motor B
temperature
K+22 Motor D: U/V relay timer 1
K+23 Motor D: U/V relay timer 2
K+24 Motor D: non-restartable motor A stall timer
K+25 Motor D: restartable Motor B stall timer
K+26 Motor D: restartable Motor B restart timer
VARs Description
L Load MVA base
L+1 Motor A fraction
L+2 Motor B fraction
L+3 Motor C fraction
L+4 Motor D: fraction
L+5 Electronic load fraction
L+6 Static load fraction
L+7 Initial value of static load real part (pu on system MVA base)
L+8 Initial value of static load reactive part (pu on system MVA base)
L+9 P3 component of static load
L+10 Q3 component of static load
L+11 Calculated substation shunt compensation (pu on system MVA base)
L+12 Transformer tap
L+13 Transformer low side voltage real part
L+14 Transformer low side voltage imaginary part
L+15 Load bus voltage real part
L+16 Load bus voltage imaginary part
L+17 Initial value of load bus voltage magnitude
L+18 Feeder resistance (pu on system MVA base)
VARs Description
L+19 Feeder reactance (pu on system MVA base)
L+20
Sum of substation shunt admittance and feeder compensation admittance
at substation end
L+21 Substation shunt admittance
L+22 Initial value of electronic load real part (pu on system MVA base)
L+23 Initial value of electronic load reactive part (pu on system MVA base)
L+24 Transformer reactance (pu on system MVA base)
L+25 Static load real part (pu on system MVA base)
L+26 Static load reactive part (pu on system MVA base)
L+27 Electronic load real part (pu on system MVA base)
L+28 Electronic load reactive part (pu on system MVA base)
L+29 Load bus voltage magnitude
L+30 Low side bus voltage magnitude
L+31 Motor A P (pu on system MVA base)
L+32 Motor A Q (pu on system MVA base)
L+33 Motor B P (pu on system MVA base)
L+34 Motor B Q (pu on system MVA base)
L+35 Motor C P (pu on system MVA base)
L+36 Motor C Q (pu on system MVA base)
L+37 Motor D P (pu on system MVA base)
L+38 Motor D Q (pu on system MVA base)
L+39 Transformer controlled bus voltage
L+40 Initial value of feeder resistance (pu on system MVA base)
L+41 Initial value of feeder reactance (pu on system MVA base)
L+42 Composite load real before load shed (pu on system MVA base)
L+43
Real part of composite load shed in a particular stage (pu on system MVA
base)
L+44
Real part of composite load shed upto a particular stage (pu on system
MVA base)
L+45 LTC control time delay counter
L+46 Tap changer timer
L+47 Initial value of Motor A P (pu on system MVA base)
VARs Description
L+48 Initial value of Motor A Q (pu on system MVA base)
L+49 Initial value of Motor B P (pu on system MVA base)
L+50 Initial value of Motor B Q (pu on system MVA base)
L+51 Initial value of Motor C P (pu on system MVA base)
L+52 Initial value of Motor C Q (pu on system MVA base)
L+53 Initial value of Motor D P (pu on system MVA base)
L+54 Initial value of Motor D Q (pu on system MVA base)
L+55 Feeder compensation admittance at substation end
L+56 Feeder compensation admittance at far end
L+57 Static load conductance
L+58 Static load susceptance
L+59 Spare
L+60 Spare
L+61 Real component of current injection at system load bus
L+62 Reactive component of current injection at system load bus
L+63 Initial value of Motor A MVA base
L+64 Initial value of Motor B MVA base
L+65 Initial value of Motor C MVA base
L+66 Initial value of Motor D MVA base
L+67 Initial value of feeder compensation admittance at substation end
L+68 Initial value of feeder compensation admittance at far end
L+69 Motor A: Admittance of initial condition MVAr difference
L+70 Motor A: Q
L+71 Motor A: Tele (pu on motor MVA base)
L+72 Motor A: Speed deviation
L+73 Motor A: Initial load torque (pu on motor MVA base)
L+74 Motor A: Iq
L+75 Motor A: Id
L+76 Motor A: Current (pu on motor MVA base)
L+77 Motor A: UV relay1 trip time
L+78 Motor A: UV relay2 trip time
VARs Description
L+79 Motor A: MVA base
L+80 Motor A: TL - Load torque (pu)
L+81 Motor A: UV relay1 reclose time
L+82 Motor A: UV relay2 reclose time
L+83 Motor A: Trip-reclose factor
L+84 Motor A: Nominal load torque
L+85 Motor B: Admittance of initial condition MVAr difference
L+86 Motor B: Q
L+87 Motor B: Tele (pu on motor MVA base)
L+88 Motor B: Speed deviation
L+89 Motor B: Initial load torque (pu on motor MVA base)
L+90 Motor B: Iq
L+91 Motor B: Id
L+92 Motor B: Current (pu on motor MVA base)
L+93 Motor B: UV relay1 trip time
L+94 Motor B: UV relay2 trip time
L+95 Motor B: MVA base
L+96 Motor B: TL - Load torque (pu)
L+97 Motor B: UV relay1 reclose time
L+98 Motor B: UV relay2 reclose time
L+99 Motor B: Trip-reclose factor
L+100 Motor B: Nominal load torque
L+101 Motor C: Admittance of initial condition MVAr difference
L+102 Motor C: Q
L+103 Motor C: Tele (pu on motor MVA base)
L+104 Motor C: Speed deviation
L+105 Motor C: Initial load torque (pu on motor MVA base)
L+106 Motor C: Iq
L+107 Motor C: Id
L+108 Motor C: Current (pu on motor MVA base)
L+109 Motor C: UV relay1 trip time
VARs Description
L+110 Motor C: UV relay2 trip time
L+111 Motor C: MVA base
L+112 Motor C: TL - Load torque (pu)
L+113 Motor C: UV relay1 reclose time
L+114 Motor C: UV relay2 reclose time
L+115 Motor C: Trip-reclose factor
L+116 Motor C: Nominal load torque
L+117 Motor D: Bus voltage (pu)
L+118 Motor D: Bus frequency (pu)
L+119 Motor D: Aggregated AC unit real power (MW)
L+120 Motor D: Aggregated AC unit reactive power (MVAr)
L+121 Motor D: Aggregated AC unit current (pu on system MVA base)
L+122
Motor D: Terminal current component in phase with voltage (in pu on
motor MVA base)
L+123
Motor D: Terminal current component lagging voltage (in pu on motor
MVA base)
L+124
Motor D: Terminal current component on network real axis on system
MVA base (pu)
L+125
Motor D: Terminal current comp on network imaginary axis on system
MVA base (pu)
L+126
Motor D: non-restartable motor A and restartable motor B Initial
Temperature
L+127 Motor D: Fraction of motors not tripped by U/V relay - gain Kuv
L+128 Motor D: Fraction of motors not tripped by contactors - gain Kcon
L+129 Motor D: Contactor status for compressor voltage calculation 0=off, 1=on
L+130 Motor D: Input voltage from a previous step (pu)
L+131
Motor D: KthA non-restartable compressor motor A fraction not tripped by
thermal protection
L+132
Motor D: Shunt admittance (in pu on motor MVA base), computed during
the initialization
L+133 Motor D: non-restartable Motor A run / stall state (run=1/stall=0)
L+134 Motor D: restartable Motor B run / stall state (run=1/stall=0)
VARs Description
L+135
Motor D: KthB restartable compressor motor B fraction not tripped by
thermal protection
L+136
Motor D: Internal variable used for determining non-restartable motor A
temperature
L+137
Motor D: Internal variable used for determining restartable motor B
temperature
L+138 Motor D: Real component of voltage at pervious time step (pu)
L+139 Motor D: Reactive component of voltage at previous time step (pu)
L+140 Motor D: Time instant at which the model was called previous time
L+141 Motor D: Internal variable, P0 for active power at 1.0 pu voltage4
L+142 Motor D: Internal variable, Q0 for reactive power at 1.0 pu voltage4
L+143 Motor D: Computed motor MVA base
L+144 Motor D: Adjusted Vstall based on load factor (pu)
L+145 Motor D: Adjusted Vbrk based on load factor (pu)
Reserved
Description
ICONs
N+1 LTC control delay flag
N+2 LTC control timeout flag
N+3 Tap adjustment timer status flag
N+4 Static load admittance storage status flag
N+5 Motor A: UV trip relay1 flag (0=Reset timer, 1=Start timer, 2=Test timer)
N+6
Motor A: UV trip relay1 status (1=Delay complete, motor should be
tripped)
N+7 Motor A: UV trip relay2 flag (0=Reset timer, 1=Start timer, 2=Test timer)
N+8
Motor A: UV trip relay2 status (1=Delay complete, motor should be
tripped)
N+9
Motor A: UV reclose relay1 flag (0=Reset timer, 1=Start timer, 2=Test
timer)
N+10
Motor A: UV reclose relay1 status (1=Delay complete, motor should be
reclosed)
N+11
Motor A: UV reclose relay2 flag (0=Reset timer, 1=Start timer, 2=Test
timer)
Reserved
Description
ICONs
N+12
Motor A: UV reclose relay2 status (1=Delay complete, motor should be
reclosed)
N+13 Motor A: starting status (1=starting phase, 0=already started)
N+14 Motor B: UV trip relay1 flag (0=Reset timer, 1=Start timer, 2=Test timer)
N+15
Motor B: UV trip relay1 status (1=Delay complete, motor should be
tripped)
N+16 Motor B: UV trip relay2 flag (0=Reset timer, 1=Start timer, 2=Test timer)
N+17
Motor B: UV trip relay2 status (1=Delay complete, motor should be
tripped)
N+18
Motor B: UV reclose relay1 flag (0=Reset timer, 1=Start timer, 2=Test
timer)
N+19
Motor B: UV reclose relay1 status (1=Delay complete, motor should be
reclosed)
N+20
Motor B: UV reclose relay2 flag (0=Reset timer, 1=Start timer, 2=Test
timer)
N+21
Motor B: UV reclose relay2 status (1=Delay complete, motor should be
reclosed)
N+22 Motor B: starting status (1=starting phase, 0=already started)
N+23 Motor C: UV trip relay1 flag (0=Reset timer, 1=Start timer, 2=Test timer)
N+24
Motor C: UV trip relay1 status (1=Delay complete, motor should be
tripped)
N+25 Motor C: UV trip relay2 flag (0=Reset timer, 1=Start timer, 2=Test timer)
N+26
Motor C: UV trip relay2 status (1=Delay complete, motor should be
tripped)
N+27
Motor C: UV reclose relay1 flag (0=Reset timer, 1=Start timer, 2=Test
timer)
N+28
Motor C: UV reclose relay1 status (1=Delay complete, motor should be
reclosed)
N+29
Motor C: UV reclose relay2 flag (0=Reset timer, 1=Start timer, 2=Test
timer)
N+30
Motor C: UV reclose relay2 status (1=Delay complete, motor should be
reclosed)
N+31 Motor C: starting status (1=starting phase, 0=already started)
N+32 Motor D: non-restartable Motor A Run/Stall status, Run=1, Stall=0
Reserved
Description
ICONs
N+33
Motor D: restartable Motor B Run, Restart, Stall status, Run=1,
Restart=2, Stall=0
N+34 Motor D: Under voltage relay trip status, Non-Trip=1, Trip=0
N+35 Motor D: Under voltage relay first pick up flag, becomes 0 on Pick Up
N+36 Motor D: Under voltage relay second pick up flag, becomes 0 on Pick Up
N+37
Motor D: Thermal relay trip 1 status for non-restartable motor A, Non-
trip=1. Trip=0
N+38
Motor D: Thermal relay trip 2 status for non-restartable motor A, Non-
trip=1. Trip=0
N+39
Motor D: Thermal relay trip 1 status for restartable motor B, Non-trip=1.
Trip=0
N+40
Motor D: Thermal relay Trip 2 status for restartable motor B, Non-trip=1.
Trip=0
N+41
Motor D: Contactors sarted to drop out flag, Not started to drop out=1,
Started to drop out=0
N+42
Motor D: All contactors dropped out flag, All not dropped out=1, All
dropped out=0
N+43
Motor D: Contactors started to reclose flag, Not started to reclose=1,
Started to reclose=0
N+44 Motor D: All Contactors reclosed flag, All not reclosed=1, All reclosed=0
N+45
Motor D: non-restartable motor A stall relay pick up flag, becomes 0 on
pick up
N+46
Motor D: restartable motor B stall relay pick up flag, becomes 0 on pick
up
N+47
Motor D: restartable motor B restart relay pick up flag, becomes 0 on pick
up
I, 'USRLOD', LID, 'CMLDxxU1', 12, IT, 0, 132, 27, 146, 48, CON(J) to CON(J+131) /
LID is an explicit load identifier or may be * for application to loads of any ID associated with the
subsystem type.
"IT"
Model suffix
Description "I" Description
"xx"
BL 1 Bus number
OW 2 Owner number
ZN 3 Zone number
AR 4 Area number
AL 5 0
Note: CMLDBL internally uses induction motor model to simulate three phase motors. In case of
non-convergence, number of iterations may be increased and time step may be reduced.
K+1 QMULT
Reserved
Value Description
ICON
N Service status memory
Pinitial Qinitial
PMLTMX QMLTMX
+ +
1 KP 1 KQ
X X
Pactual Pinitial S PMULT Qactual Qinitial S QMULT
PMLTMN QMLTMN
J+6 a7
J+7 a8
J+8 n1
J+9 n2
J+10 n3
J+11 n4
J+12 n5
J+13 n6
n n n
P = P load a 1 v 1 + a 2 v 2 + a 3 v 3 1 + a 7 f
n n n
Q = Q load a 4 v 4 + a 5 v 5 + a 6 v 6 1 + a 8 f
The constant power and constant current load components are made sensitive to bus frequency
according to:
m
P = P o -------
o
n
Q = Q o -------
o
r
I p = I po -------
o
s
I q = I qo -------
o
This chapter contains a collection of data sheets for the load relay models contained in the PSSE
dynamics model library.
Model Description
DLSHBL, DLSHOW, DLSHZN, DLSHAR, DLSHAL Rate of frequency load shedding model
Underfrequency load shedding model with
LDS3BL, LDS3OW, LDS3ZN, LDS3AR, LDS3AL
transfer trip
LDSHBL, LDSHOW, LDSHZN, LDSHAR, LDSHAL Underfrequency load shedding model
LDSTBL, LDSTOW, LDSTZN, LDSTAR, LDSTAL Time underfrequency load shedding model
Undervoltage load shedding model with
LVS3BL, LVS3OW, LVS3ZN, LVS3AR, LVS3AL
transfer trip
LVSHBL, LVSHOW, LVSHZN, LVSHAR, LVSHAL Undervoltage load shedding model
UVUFBLU1, UVUFOWU1, UVUFZNU1, User written under-voltage and under-
UVUFARU1, UVUFALU1 frequencey load shedding model
Reserved
Value Description
ICONs
N First point delay flag
N+1 First point timeout flag
N+2 First timer status
N+3 Second point delay flag
N+4 Second point timeout flag
N+5 Second timer status
N+6 Third point delay flag
N+7 Third point timeout flag
N+8 Third timer status
Reserved
Value Description
ICONs
N First point delay flag
N+1 First point timeout flag
N+2 First point timer status
N+3 Second point delay flag
N+4 Second point timeout flag
N+5 Second point timer status
N+6 Third point delay flag
N+7 Third point timeout flag
N+8 Third point timer status
N+9 Fourth point delay flag
N+10 Fourth point timeout flag
N+11 Fourth point timer status
N+12 Fifth point delay flag
N+13 Fifth point timeout flag
N+14 Fifth point timer status
N+15 Transfer trip breaker status
N+16 Transfer trip timer status
Reserved
Value Description
ICONs
N First point delay flag
N+1 First point timeout flag
N+2 First timer status
N+3 Second point delay flag
N+4 Second point timeout flag
N+5 Second timer status
N+6 Third point delay flag
N+7 Third point timeout flag
N+8 Third timer status
LID is an explicit load identifier or may be for application to loads of any ID associated with the
subsystem type.
Reserved
Value Description
ICONs
N Relay status
N+1 Breaker timer flag
N+2 Breaker timeout flag
Zero
f1 f2 f3 f4 Frequency
Rated
Frequency Frequency (Hz)
Reserved
Value Description
ICONs
N First point delay flag
N+1 First point timeout flag
N+2 First point timer status
N+3 Second point delay flag
N+4 Second point timeout flag
N+5 Second point timer status
N+6 Third point delay flag
N+7 Third point timeout flag
N+8 Third point timer status
N+9 Fourth point delay flag
N+10 Fourth point timeout flag
N+11 Fourth point timer status
N+12 Fifth point delay flag
N+13 Fifth point timeout flag
N+14 Fifth point timer status
Reserved
Value Description
ICONs
N+15 First transfer trip breaker status
N+16 First transfer trip timer status
N+17 Second transfer trip breaker status
N+18 Second transfer trip timer status
Reserved
Value Description
ICONs
N First point delay flag
N+1 First point timeout flag
N+2 First timer status
N+3 Second point delay flag
N+4 Second point timeout flag
Reserved
Value Description
ICONs
N+5 Second timer status
N+6 Third point delay flag
N+7 Third point timeout flag
N+8 Third point status
VARs # Description
L First voltage-based timer memory
Second voltage-based timer memory
L+1
(pu)
L+2 Third voltage-based timer memory
L+3 First frequncy-based timer memory
L+4 Second frequncy-based timer memory
L+5 Third frequncy-based timer memory
Load fractions already shed in previous
L+6
stages
Reserved
# Description
ICONs
Reserved
# Description
ICONs
N+9 First frequncy-based point delay flag
N+10 First frequncy-based point timeout flag
N+11 First frequncy-based timer status
Second frequncy-based point delay
N+12
flag
Second frequncy-based point timeout
N+13
flag
N+14 Second frequncy-based timer status
N+15 Third frequncy-based point delay flag
N+16 Third frequncy-based point timeout flag
N+17 Third frequncy-based timer status
"IT"
Model suffix
Description "I" Description
"xx"
BL 1 Bus number
OW 2 Owner number
ZN 3 Zone number
AR 4 Area number
AL 5 0
This chapter contains a collection of data sheets for the line relay models contained in the PSSE
dynamics model library.
Model Description
CIROS1 Double circle or lens out-of-step tripping or blocking relay
DISTR1 mho, impedance, or reactance distance relay
DPDTR1 Rate of change of power relay
RXR1 RXR distance relay
SCGAP2 Series capacitor gap relay
SLLP1 SLLP tripping relay
SLNOS1 Straight line blinder out-of-step relay
SLYPN1 G.E. directional comparison and overcurrent relay
TIOCR1 Time inverse overcurrent relay
11.1 CIROS1
Double Circle or Lens Out-of-Step Tripping or Blocking Relay
X Outer Zone
Inner Zone
Outer Zone
Inner Zone
R
R
X
X
+1
Rotation
-2
+2
R R
-1
Outer Zone
Inner Zone
11.2 DISTR1
mho, Impedance, or Reactance Distance Relay
Diameter
Centerline
Angle
Center
Distance
R
Zone Reach
Zone 3
Zone 2
Zone 1
mho Distance
Zone 3
Reach
Zone 3
Center
Distance
Zone 3 Zone 2
Centerline Zone 1 Reach
Angle Reach
Reactance Distance
Zone 3
Zone 2
Zone 1
R
Directional
Element
Impedance Distance
Inactive Area X
2
1
X R
Intercept
R
-1 -2
R R
Blinder Types
Directional
Element
Angle
R
11.3 DPDTR1
Rate of Change of Power Relay
11.4 RXR1
RXR Distance Relay
X
R13,X13 R12,X12
R9,X9
R8,X8
R10,X10
Zone 3
R5,X5 Zone 2
R3,X3 R4,X4
R2,X2
R6,X5 R1,X1
Zone 1 R7,X7
Zone 4
R14,X14 R11,X11
11.5 SCGAP2
Series Capacitor Gap Relay
11.6 SLLP1
SLLP Tripping Relay
T4 T3 T2 T1
X
(R1,X1)
(Rm,Xm) P2
P1
P3
(R2,X2)
11.7 SLNOS1
Straight Line Blinder Out-of-Step Relay
Inactive
Area
Intercept
1
-2 2
-1 Rotation
X X
4 3 2 1
2 1
R
Angle
R
Intercept
2nd Pair
1st Pair
11.8 SLYPN1
G.E. Directional Comparison and Overcurrent Relay
Zone 1
Diameter
Zone 1
Centerline
Angle
Zone 1
Center
Distance
Center Point
Zone 2
Zone 2 Radius
Forward
Reach
Center Point
Zone 2
Centerline
Angle
Zone 2
Reverse
Reach
Reverse
Reaching
Centerline
Angle
Reverse
Reaching Reverse Reaching
Center Diameter
Distance
11.9 TIOCR1
Time Inverse Overcurrent Relay
This chapter contains a collection of data sheets for the auxiliary-signal models contained in the
PSSE dynamics model library.
Model Description
CHAAUT Chateauguay auxiliary signal model
CPAAUT Frequency sensitive auxiliary signal model
DCCAUT Comerford auxiliary signal model
DCVRFT HVDC ac voltage controller model
HVDCAT General purpose auxiliary signal model
PAUX1T Frequency sensitive auxiliary signal model
PAUX2T Bus voltage angle sensitive auxiliary signal model
RBKELT Runback model (can be used only with two-terminal dc line models)
dc line auxiliary signal model (can be used only with two-terminal dc
SQBAUT
line models)
12.1 CHAAUT
Chateauguay Auxiliary Signal Model
STATEs # Description
K Integrator
K+1 Integrator
K+2 Integrator
K+3 Integrator
K+4 Transducer 1
K+5 Transducer 2
VAR # Description
L Signal, MW
fo
P1POS
FN1 MP1 KP1 + KD1s
Frequency (Hz) 1 +
ICON(M) 1 + sTM1 FP1 (1 + T1s) (1 + T2s)
MN1
*
P1NEG PMAX VAR(L)
Auxiliary
Power Signal
P2POS (MW)
PMIN
*
FN2 MP2 KP2 + KD2s
Frequency (Hz) 1 +
ICON(M+1) FP2
1 + sTM2 (1 + T3s) (1 + T4s)
MN2
P2NEG
fo
12.2 CPAAUT
Frequency Sensitive Auxiliary Signal Model
STATEs # Description
K Washout
K+1 Time constant
VAR # Description
L Signal, MW
ICON # Description
M Bus number
PMAX
VAR(L)
Frequency sTB 1 Auxiliary
Cm Power Signal
Deviation (pu) 1 + sTB 1 + sTA
at Bus ICON(M) PMIN (MW)
12.3 DCCAUT
Comerford Auxiliary Signal Model
STATEs # Description
K Integrator
K+1 Integrator
K+2 Integrator
K+3 Integrator
K+4 Transducer 1
K+5 Transducer 2
VAR # Description
L Signal, MW
fo P1POS
DPDTMX
Frequency (Hz) 1 FN1 MP1 KP1 + KD1s
+
ICON(M) 1 + sTM1 Rate
FP1 (1 + T1s) (1 + T2s)
MN1 Limit
*
DPDTMN VAR(L)
P1NEG Auxiliary
P2POS Power Signal
(MW)
*
Frequency (Hz) 1 FN2 MP2 KP2 + KD2s
+
ICON(M+1) 1 + sTM2
FP2 (1 + T3s) (1 + T4s)
MN2
P2NEG
fo
12.4 DCVRFT
HVDC ac Voltage Controller
J+4 TB (sec)
J+5 KA
J+6 TA (sec)
J+7 VRMAX
J+8 VRMIN
STATEs # Description
K Vmeasured
K+1 Lead lag
K+2 VR
VARs # Description
L HVDC DCV delta
L+1 Reference voltage
VAR(L+1)
VRMAX
+ VIMAX
1 (1 + sTC) KA
ICON(M) VAR(L)
(V) 1 + sTR VERR (1 + sTB) (1 + sTA)
VIMIN
VRMIN
12.5 HVDCAT
General Purpose Auxiliary Signal Model
J+6 T3 (sec)
J+7 B (0 or 1)
J+8 T4 (sec)
J+9 T5 (sec)
J+10 C
J+11 D
J+12 E
J+13 F
J+14 MINOUT
J+15 MAXOUT
STATEs # Description
K Lag block
K+1 First lead-lag
K+2 Second lead-lag
K+3 2nd order block
K+4 2nd order block
VARs # Description
L Signal
L+1 Internal
L+2 Storage
ICONs # Description
Input code:
1 Current on branch (pu)
2 Power on branch (pu)
M 3 Frequency difference busi - busj (pu)
4 Voltage busi (pu)
5 Frequency busi (pu)
M+1 Bus i number
M+2 Bus j number or zero for input 4 and 5
Branch ID or zero for inputs 3, 4, and 5, or -
M+3
1 for sum of parallel line flows
Input
Signal0
MAXIN MAXOUT
Ks A + sT2 B + sT4 s2 + sC + D VAR(L)
Input + Auxiliary
Signal 1 + sT1 1 + sT3 1 + sT5 s2 + sE + F Signal
MININ MINOUT
12.6 PAUX1T
Frequency Sensitive Auxiliary Signal Model
STATE # Description
K Sensor
VARs # Description
L Signal, MW
L+1
.
. Delay table
.
L+10
ICON # Description
M Bus number
MAX VAR(L)
Frequency 1 Auxiliary
Deviation (pu) -sTD KC Power Signal
1 + sTR e
at Bus ICON(M) (MW)
MIN
12.7 PAUX2T
Bus Voltage Angle Sensitive Auxiliary Signal Model
J+2 KC
J+3 T1 (>0) (sec)
J+4 T2 (>0) (sec)
J+5 T3 (>0) (sec)
STATEs # Description
K Sensor
K+1 Washout
K+2 Washout
VARs # Description
L Signal, MW
L+1
.
. Delay table
.
L+9
L+10 Memory
L+11 Reference
ICON # Description
M Bus number
Angle
Reference
VAR(L+11)
MAX
VAR(L)
Voltage Angle + 1 sT1 KCsT2 Auxiliary
at Bus ICON(M)
1 + sTR e -sTD 1 + sT3 1 + sT4 Power Signal
(rad) (MW)
MIN
12.8 RBKELT
Eel River Runback
(can be used with two-terminal dc line models only)
STATE # Description
K Output signal (MW)
VARs # Description
L Memory
L+1 Memory
12.9 SQBAUT
Frequency Sensitive dc Line Auxiliary Signal Model
(can be used with two-terminal dc lines only)
J+4 A2
J+5 B1
J+6 B2 (>0)
J+7 IMAX (amps)
J+8 IMIN (amps)
J+9 Current step (amps)
J+10 Td Communication delay (sec) <10 time steps
J+11 TL (sec)
STATEs # Description
K Input filter
K+1 First notch filter STATE
K+2 Second notch filter STATE
K+3 First lag
K+4 Second lag
VARs # Description
L Signal, MW
L+1
.
. Delay table
.
L+10
STATE(K+1)
STATE(K) STATE(K+2) IMAX
Frequency 1 + A1s + A2s2
Deviation (pu)
KDC + KACsT2 1 2
------------------
1 + T L s
at Bus ICON(M) 1 + sT2 1 + B1s + B2s2
IMIN CL
Input Filter Notch Filter
= min VAR(L)
T s dc Auxiliary
e d X
CUR Power Signal
Communication (MW)
Delay
Current Step
Function
Model Description
CDC1T Two-terminal dc line model
CDC4T Two-terminal dc line model
CDC6T Two-terminal dc line model
CDC6TA Two-terminal dc line model
CDC7T dc line model
CDCABT ABB dc line model for Kontek line
New Eel River dc line and auxiliaries model. This model internally uses
CEELT the following models: CHAAUT (auxiliary-signal model), CEEL2T (two-
terminal dc line model), and RUNBK (dc line runback model).
CEEL2T New Eel River dc line model
13.1 CDC1T
Two-terminal dc Line Model
STATEs # Description
K Measured inverter dc voltage
K+1 Measured line dc current
VARs # Description
L Other signals (MW) [DC2SIG(1,I)]
L+1 VPCR, rectifier dc voltage
L+2 VDCI, inverter dc voltage
L+3 SETVAL, current (amps) or power (MW) demand
L+4 DC, dc current (amps)
L+5 ALPHA, alpha-rectifier (degrees)
L+6 GAMMA, gamma-inverter (degrees)
L+7 PACR, rectifier ac real power (pu)
L+8 QACR, rectifier ac reactive power (pu)
VARs # Description
L+9 PACI, inverter ac real power (pu)
L+10 QACI, inverter ac reactive power (pu)
L+11 KF, ramping factor
L+12 TON, unblocking time
ICON # Description
Control mode:1
0 Blocked
M
1 Power
2 Current
1 Not intended to be changed by user.
Note: If GAMMIN = GAMMX in power flow, line is assumed to be in GAMMA control. This model
uses auxiliary signal output stored in DC2SIG(1,I) (i.e., auxiliary signal index 1).
13.2 CDC4T
Two-terminal dc Line Model
STATEs # Description
K Measured inverter dc voltage (V)
K+1 Measured inverter dc current (amps)
VARs # Description
L Other signals, MW [DC2SIG(1,I)]
RESTR, time unblocks or )
L+1
unbypasses (sec
L+2 VRF, voltage ramping factor
L+3 CRF, current ramping factor
L+4 VCOMP, compensating dc voltage (V)
L+5 PACR, rectifier ac real power (pu)
L+6 QACR, rectifier ac reactive power (pu)
L+7 PACI, inverter ac real power (pu)
L+8 QACI, inverter ac reactive power (pu)
L+9 VDCI, inverter dc voltage (V)
L+10 VDCR, rectifier dc voltage (V)
L+11 DC, dc current (amps)
L+12 ALFA, alpha (degrees)
L+13 GAMA, gamma (degrees)
L+14 TIME, reswitches mode
ICONs # Description
Note: This model uses auxiliary signal output stored in DC2SIG(1,I) (i.e., auxiliary signal index 1).
dc Current
V1, C1
C
Minimum dc Current (amps)
13.3 CDC6T
Two-terminal dc Line Model
STATEs # Description
K Measured inverter dc voltage (V)
K+1 Measured inverter dc current (amps)
K+2 Measured rectifier dc voltage (V)
VARs # Description
L Other signals, MW [DC2SIG(1,I)]
RESTR, time unblocks or
L+1
unbypasses (sec)
L+2 VRF, voltage ramping factor
L+3 CRF, current ramping factor
L+4 VCOMP, compensating dc voltage (V)
L+5 PACR, rectifier ac real power (pu)
L+6 QACR, rectifier ac reactive power (pu)
L+7 PACI, inverter ac real power (pu)
L+8 QACI, inverter ac reactive power (pu)
L+9 VDCI, inverter dc voltage (V)
L+10 VDCR, rectifier dc voltage (V)
L+11 DC, dc current (amps)
L+12 ALFA, alpha (degrees)
L+13 GAMA, gamma (degrees)
L+14 TIME, reswitches mode
TIMER, rectifier blocking and
L+15
unblocking timer
VARs # Description
TIMEI, inverter blocking and
L+16
unblocking timer
TIBYP, inverter bypass and unbypass
L+17
timer
ICONs # Description
Note: This model uses auxiliary signal output stored in DC2SIG(1,I) (i.e., auxiliary signal index 1).
13.4 CDC6TA
Two-terminal dc Line Model
STATEs # Description
K Measured inverter dc voltage (V)
K+1 Measured inverter dc current (amps)
K+2 Measured rectifier dc voltage (V)
VARs # Description
L Other signals, MW [DC2SIG(1,I)]
L+1 RESTR, time unblocks or unbypasses (sec)
L+2 VRF, voltage ramping factor
L+3 CRF, current ramping factor
L+4 VCOMP, compensating dc voltage (V)
L+5 PACR, rectifier ac real power (pu)
L+6 QACR, rectifier ac reactive power (pu)
L+7 PACI, inverter ac real power (pu)
L+8 QACI, inverter ac reactive power (pu)
L+9 VDCI, inverter dc voltage (V)
L+10 VDCR, rectifier dc voltage (V)
L+11 DC, dc current (amps)
L+12 ALFA, alpha (degrees)
L+13 GAMA, gamma (degrees)
L+14 TIME, reswitches mode
L+15 TIMER, rectifier blocking and unblocking, timer
L+16 TIMEI, inverter blocking and unblocking, timer
L+17 TIBYP, inverter bypass and unbypass timer
VARs # Description
L+18 Imeasured current in amps (Ir)
L+19 Idesired before VDCL in amps (IDESr)
L+20 VDCL output in amps IMAXr)
ICONs # Description
Note: This model uses auxiliary signal outputs stored in DC2SIG(1,I) through DC2SIG(4,I)
(i.e., auxiliary signal index 1 through 4).
13.5 CDC7T
dc Line Model
STATEs # Description
K Measured dc voltage, inverter, V
K+1 Measured dc current, inverter, A
K+2 Measured dc voltage, rectifier, V
K+3 Measured dc current, rectifier, A
K+4 IDCR, Rectifier dc current, A
K+5 IDCI, Inverter dc current, A
K+6 VCDC, DC line capacitor voltage, V
K+7 Rectifier VDComp filter, pu
K+8 Inverter VDComp filter, pu
K+9 Rectifier VDComp measured, pu
K+10 Inverter VDComp measured, pu
K+11 PI controller integrator, rectifier, rad
K+12 PI controller integrator, inverter, rad
K+13 IF1, fault current dc fault 1
K+14 IF2, fault current dc fault 2
K+15 IF3, fault current dc fault 3
K+16 VDC filter for power order calculation
VARs # Description
VARs # Description
L+8 GAMA, degrees
L+9 Initial rectifier DC current order, A
L+10 Rectifier current order, limited by VDCL, pu
L+11 Inverter current order, limited by VDCL, pu
L+12 Current controller output, rectifier
L+13 Current controller output, inverter
L+14 Voltage controller output, rectifier
L+15 Voltage controller output, inverter
L+16 Gamma controller output, inverter
L+17 Selected controller output, rectifier
L+18 Selected controller output, inverter
L+19 Inverter Alpha, degrees
L+20 Initial VDComp (compensated dc voltage)
L+21 DC current order for block/unblock and overload, A
L+22 IDC1, sending end dc current, A
L+23 IDC2, receiving end dc current, A
L+24 PORD, power order, pu
ICONs # Description
Blocking and Unblocking Simulation Flag:
0 none
M
1 blocking
2 unblocking
Overload Simulation Flag:
M+1 0 none
1 overload
M+2 Control configuration: 1, 2, or 31
1 cable or cable + overhead
M+3
2 overhead
1 ICON(M+2) = 1 : Rectifier in dc current control; inverter in gamma control
ICON(M+2) = 2 : Rectifier in dc current control; inverter in dc voltage control
ICON(M+2) = 3 : Rectifier in dc voltage control; inverter in dc current control
13.6 CDCABT
Kontek ABB dc Line Model
STATEs # Description
K IDC_R, rectifier dc current (amps)
K+1 IM_R, rectifier dc current measurement (amps)
K+2 VM_R, rectifier dc voltage measurement (V)
K+3 IDC_I, inverter dc current (amps)
K+4 IM_I, inverter dc current measurement (amps)
STATEs # Description
K+5 VM_I, inverter dc voltage measurement (V)
K+6 VC, cable voltage (V)
K+7 UVDCOL_R, rectifier voltage measurement VDCL (V)
K+8 UVDCOL_I, inverter voltage measurement VDCL (V)
K+9 AINT_R, rectifier integral part of alpha-order CCA
K+10 AINT_I, inverter integral part of alpha-order CCA
K+11 Rectifier alpha integrator CFC (rad)
K+12 Inverter alpha integrator CFC (rad)
K+13 S1_R, rectifier state 1, alpha-max limitation
K+14 S1_I, inverter state 1, alpha-max limitation
K+15 S2_R, rectifier state 2, alpha-max limitation
K+16 S1_I, inverter state 2, alpha-max limitation
K+17 Inverter ac voltage measurement (pu)
K+18 Inverter transient controller state (rad)
K+19 FREQ_R, rectifier frequency control (MW)
K+20 FREQ_I, inverter frequency control (MW)
K+21 DAMP1_R, rectifier power modulation state 1
K+22 DAMP2_R, rectifier power modulation state 2
K+23 DAMP1_I, inverter power modulation state 1
K+24 DAMP2_I, inverter power modulation state 2
K+25 Master dc voltage rectifier (V)
K+26 Master dc voltage inverter (V)
K+27 Phase shift correction rectifier (rad)
K+28 Phase shift correction inverter (rad)
K+29 Dynamic current compound inverter state 1 (rad)
K+30 Dynamic current compound inverter state 2 (rad)
K+31 Current order filter rectifier alpha-max (amps)
K+32 Current order filter inverter alpha-max (amps)
K+33 Voltage control for long cables (rad)
VARs # Description
L PRECT, rectifier dc active power (W)
L+1 QRECT, inverter dc reactive power (var)
L+2 PINVRT, inverter dc active power (W)
L+3 QINVRT, inverter dc reactive power (var)
L+4 UDC_R, rectifier dc voltage (V)
VARs # Description
L+5 UDC_I, inverter dc voltage (V)
L+6 MU_I, inverter overlap angle (rad)
L+7 GAMA_I, inverter gamma (rad)
L+8 IC, current in cable capacitance (amps)
L+9 PORDER, power order master controller (W)
L+10 IOO, current order master controller (amps)
L+11 TMASTER_R, master voltage time constant if rectifier is master (sec)
L+12 TMASTER_I, master voltage time constant if inverter is master (sec)
L+13 T_R, rectifier time constant VDCL
L+14 IOMAX_R, rectifier maximum current (amps)
L+15 IORDER_R, rectifier current order from VDCL (amps)
L+16 T_I, inverter time constant VDCL
L+17 IOMAX_I, inverter maximum current order VDCL (amps)
L+18 IORDER_I, inverter current order from VDCL (amps)
L+19 I_ERROR_R, rectifier current error CCA (amps)
L+20 APROP_R, rectifier proportional part of alpha CCA (rad)
L+21 ALPHA_ORDER_R, rectifier alpha order from CCA (rad)
L+22 I_ERROR_I, inverter current error CCA (amps)
L+23 APROP_I, inverter proportional part of alpha CCA (rad)
L+24 ALFA_ORDER_I, inverter alpha order from CCA (rad)
L+25 ALFA_MAX_ORDER_R, rectifier alpha maximum segment (rad)
L+26 ALFA_MAX_ORDER_I, inverter alpha maximum segment (rad)
L+27 GAMMIN_I, inverter minimum gamma in CFC (rad)
L+28 DELT_ALFA_MAX_R, rectifier upper limit of alpha error CFC (rad)
L+29 DELT_ALFA_MIN_R, rectifier lower limit of alpha error CFC (rad)
L+30 DELT_ALFA_MAX_I, inverter upper limit of alpha error CFC (rad)
L+31 DELT_ALFA_MIN_I, inverter lower limit of alpha error CFC (rad)
L+32 ALFA_MIN_R, rectifier lower limit of alpha order CFC (rad)
L+33 ALFA_MAX_I, inverter maximum limit of alpha order CFC (rad)
L+34 ALFA_R, alpha from rectifier CFC to the converter equations (rad)
L+35 ALFA_I, alpha from inverter CFC to the converter equations (rad)
L+36 DANG_R, rectifier phase shift correction contribution to alpha (rad)
L+37 DANG_I, inverter phase shift correction contribution to alpha (rad)
TRCONR_AORDER_MIN_R, rectifier transient controller added to the
L+38
lower limit on alpha in CCA
L+39 TRCONI_T, inverter transient controller time constant (sec)
VARs # Description
DELT_PO_FREQ_R, rectifier active power modulation from frequency
L+40
controller (W)
DELT_PO_FREQ_I, inverter active power modulation from frequency
L+41
controller (W)
DELT_PO_DAMP_R, rectifier active power modulation from power
L+42
modulation (W)
DELT_PO_DAMP_I, inverter active power modulation from power
L+43
modulation (W)
L+44 EPC_POWER_R, rectifier EPC power (W)
L+45 EPC_POWER_I, inverter EPC power (W)
L+46 EPC_POWER, total EPC power (W)
L+47 DALFA_VC, inverter voltage control contribution to alpha (rad)
L+48
to Model internal memory
L+158
ICONs # Description
CURRENT DIRECTION, current from:
M 1 rectifier
0 inverter
Rectifier frequency control:
M+1 1 enable
0 disable
Inverter frequency control:
M+2 1 enable
0 disable
Rectifier power modulation:
M+3 1 enable
0 disable
Inverter power modulation:
M+4 1 enable
0 disable
Rectifier emergency power control:
M+5 1 enable
0 disable
Inverter emergency power control:
M+6 1 enable
0 disable
ICONs # Description
Inverter voltage control:
M+7 1 enable
0 disable
Rectifier phase shift correction:
M+8 1 enable
0 disable
Inverter phase shift correction:
M+9 1 enable
0 disable
Note: This model does not use auxiliary signal model outputs.
13.7 CEELT
Eel River dc Line and Auxiliaries Model
(combines CHAAUT, CEEL2T and RUNBK models)
1. This model uses the following ICON, CON, STATE, and VAR assignments:
4. 4. Initially the model sets ICON(M+7) to 0. When the user wants to initiate runback of
the dc line, ICON(M+7) has to be set to 1.
5. Since CEELT has an in-built auxiliary signal model, do not attach any other external
auxiliary signal model.
13.8 CEEL2T
Eel River dc Line Model
STATEs # Description
K Power controller dc voltage (V), VDCP
K+1 Current order (amps)
VARs # Description
L Other signals, MW [DC2SIG(1,I)]
L+1 RESTR, time unblocks or unbypasses (sec)
L+2 VRF, voltage setpoint multiplier
L+3 CRF, current setpoint multiplier
L+4 VCOMP, compensated dc voltage (V)
L+5 PACR, rectifier ac real power (pu)
L+6 QACR, rectifier ac reactive power (pu)
L+7 PACI, inverter ac real power (pu)
L+8 QACI, inverter ac reactive power (pu)
L+9 VDCI, inverter dc voltage (V)
L+10 VDCR, rectifier dc voltage (V)
L+11 DC, dc current (amps)
VARs # Description
L+12 ALFA, alpha (degrees)
L+13 GAMA, gamma (degrees)
L+14 Other VDC signals (kV) [DC2SIG(2,I)]
L+15 TIMER, rectifier blocking and unblocking, timer
L+16 TIMEI, inverter blocking and unblocking, timer
L+17 TIBYP, inverter bypass and unbypass timer
L+18 TDELAY, reference time for current limit delay
L+19 TSAMPL, reference time for current limit sampling
L+20 DCLVAC, current limit (amps)
L+21 VACIN, voltage which determines current limit
ICONs # Description
Inverter status:1
0 Normal
M
1 Blocked
2 Ramping
Rectifier status:1
0 Normal
M+1
1 Blocked
2 Ramping
1. When this model is called directly (i.e., not via model CEELT), the current limit uses
inverter VDC (i.e., ICON(M+2) of this model is always 0 when called directly).
2. If the user wishes to block the converter, MDC(I) should be set to zero.
3. When called directly, this model uses auxiliary signal outputs stored in DC2SIG(1,I)
(i.e., auxiliary signal index 1), and DC2SIG(2,I) (i.e., auxiliary signal index 2).
VH1 VH2
VAR(ICON(M+2)) CON(J+19) CON(J+20)
CH
ICON(M+2)0
CON(J+16)
VACIN DCLVAC
VAR(L+21) VAR(L+20)
VDCI/1000 ICON(M+2)=0 CL VL1 VL2
CON(J+15) CON(J+17) CON(J+18)
1000*VCMODE(I)
ICON(M+1)=2 ICON(M+1)=2
SETVAL(I)<0 SETVAL(I)>0
0.0 CRAMP
CON(J+13)
VDCI/VAR(L+2) VDCR/VAR(L+2)
VSET
DCSET
DCSET(1 DELTI(I))
VAR(L+14)=DC2SIG(2,I)
Other Signals
+
+
VSET (kV)
VSCHED(I)
VAR(L+2)* 1.0
1
s
CON(J+10)
VSCHED(I)
ICON(M)2 ICON(M)=2
0.0 VRAMP
CON(J+12)
*VAR(L+2) is also used by the power controller so that the current order is not
increased when voltage is depressed. VAR(L+2) is started at the lower limit when
unblocking or unbypassing.
dc Setpoint Control
Model Description
MTDC1T Multiterminal (five converter) dc line model
MTDC2T Multiterminal (five converter) dc line model
MTDC3T Multiterminal (eight converter) dc line model
14.1 MTDC1T
Multiterminal (Five Converter) dc Line Model
STATEs # Description
K Measured ac voltage, converter 1
K+1 Measured dc voltage, converter 1
K+2 Measured dc current, converter 1
K+3 Measured ac voltage, converter 2
K+4 Measured dc voltage, converter 2
K+5 Measured dc current, converter 2
K+6 Measured ac voltage, converter 3
K+7 Measured dc voltage, converter 3
K+8 Measured dc current, converter 3
K+9 Measured ac voltage, converter 4
K+10 Measured dc voltage, converter 4
K+11 Measured dc current, converter 4
K+12 Measured ac voltage, converter 5
K+13 Measured dc voltage, converter 5
K+14 Measured dc current, converter 5
VARs # Description
L VAC bus converter 1
L+1 PAC bus converter 1
L+2 QAC bus converter 1
VARs # Description
L+17 Angle converter 3
L+18 VAC bus converter 4
L+19 PAC bus converter 4
L+20 QAC bus converter 4
L+21 VDC converter 4
L+22 IDC converter 4
L+23 Angle converter 4
L+24 VAC bus converter 5
L+25 PAC bus converter 5
L+26 QAC bus converter 5
L+27 VDC converter 5
L+28 IDC converter 5
L+29 Angle converter 5
L+30
L+31
L+32
Internal VARs required by model
L+33
L+34
L+35
ICONs # Description
Converter 1 flag:1, 2
0 Normal operation
M+1
1 Blocked
2 Unblocking
M+2 Converter 2 flag1, 2
M+3 Converter 3 flag1, 2
M+4 Converter 4 flag1, 2
M+5 Converter 5 flag1, 2
VARs # Description
14.2 MTDC2T
Multiterminal (Five Converter) dc Line Model
STATEs # Description
K Measured ac voltage, converter 1
K+1 Measured dc voltage, converter 1
K+2 Measured dc current, converter 1
K+3 Measured ac voltage, converter 2
K+4 Measured dc voltage, converter 2
K+5 Measured dc current, converter 2
K+6 Measured ac voltage, converter 3
K+7 Measured dc voltage, converter 3
K+8 Measured dc current, converter 3
K+9 Measured ac voltage, converter 4
K+10 Measured dc voltage, converter 4
K+11 Measured dc current, converter 4
K+12 Measured ac voltage, converter 5
K+13 Measured dc voltage, converter 5
K+14 Measured dc current, converter 5
K+15 Power controller voltage
K+16 VDCL voltage
VARs # Description
L VAC bus converter 1
L+1 PAC bus converter 1
L+2 QAC bus converter 1
L+3 VDC converter 1
VARs # Description
L+15 VDC converter 3
L+16 IDC converter 3
L+17 Angle converter 3
L+18 VAC bus converter 4
L+19 PAC bus converter 4
L+20 QAC bus converter 4
L+21 VDC converter 4
L+22 IDC converter 4
L+23 Angle converter 4
L+24 VAC bus converter 5
L+25 PAC bus converter 5
L+26 QAC bus converter 5
L+27 VDC converter 5
L+28 IDC converter 5
L+29 Angle converter 5
L+30 CRF1 current setpoint multiplier
L+31 CRF2 current setpoint multiplier
L+32 CRF3 current setpoint multiplier
L+33 CRF4 current setpoint multiplier
L+34 CRF5 current setpoint multiplier
L+35 VRF voltage setpoint multiplier
L+36
L+37
L+38
Internal memory
L+39
L+40
L+41
ICONs # Description
VARs # Description
VAR(LAUX+N-1)=DCMSIG(N,I)
+ VAR(L+29+1)
MDC(I)=2 (See Diagram B)
+
Current Control
SETVAL(N)
Converter
VDCOL(1) DCORDR(1)
VAR(LAUX+N-1)=DCMSIG(N,I)
C0-1
+
106
MDC(I)=1
+ VDCOL(2)
DCORDR(2)
SETVAL(N) VDCP(N) C0-2
VDCP(N) VDCOL(3)
DCORDR(3)
(See Diagram C) C0-3
All Current
Controlling VDCOL(4) DCORDR(4)
Converters C0-4
Voltage Control
SETVAL(N) VDCOL(5)
Converter
+ DCORDR(5)
C0-5
106 +
MARGIN
SETVAL(N) VDCP(N) VAR(L+29+5) (CON(J+78))
All Current (See Diagram B)
Controlling
VDCP(N) Converters
(See Diagram C)
VAR(L+29+1)/SDCPF
VAR(L+29+2)/SDCPF
VAR(L+29+4)/SDCPF
VAR(L+29+5)/SDCPF
Diagram A
Block Diagram Assuming Converter #5 is a Voltage Controlling Converter
1 1 1 1 1
S S S S S
Diagram B
Current Ramping
VDC of Voltage
Controlling Converter VDC of Voltage
VAR(L+35) Controlling Converter
V3 of Voltage
Controlling Converter
1 1 CON(J+76) Up
CON(J+75)
1 + sTVF 1 + sTVDCOL CON(J+77) Down
1000*VCMODE(I) V1 of Voltage
Controlling Converter
Calculated Upon
Initialization VDCOL Limits
VAR VAR VAR VAR VAR CON CON CON CON CON
(L+35+1) (L+35+2) (L+35+3) (L+35+4) (L+35+5) (J+9/J+14) (J+24/J+29) (J+39/J+44) (J+54/J+59) (J+69/J+74)
VDCP(1) VDCP(2) VDCP(3) VDCP(4) VDCP(5) VDCOL(1) VDCOL(2) VDCOL(3) VDCOL(4) VDCOL(5)
Diagram C
Converter Power Controller and
Voltage-Dependent Current Limiter
VAR(L+35) 1.0
1
S
RSVLT of Voltage
Controlling Converter
(VSCHED(I)
ICON(M)=2 or
ICON(M+6)=1
VRAMP of Voltage
Controlling Converter
Diagram D
dc Voltage Setpoint Control
VDC VDC
A = B*CON(J+78+N)
MARGIN MARGIN
(CON(J+78)) (CON(J+78))
IDC IDC
DCORDR DCORDR
Rectifier Inverter
Diagram E
Converter Characteristics
14.3 MTDC3T
Multiterminal (Eight Converter) dc Line Model
STATEs # Description
K Measured ac voltage, converter 1
K+1 Measured dc voltage, converter 1
K+2 Measured dc current, converter 1
K+3 Measured ac voltage, converter 2
K+4 Measured dc voltage, converter 2
K+5 Measured dc current, converter 2
K+6 Measured ac voltage, converter 3
K+7 Measured dc voltage, converter 3
K+8 Measured dc current, converter 3
K+9 Measured ac voltage, converter 4
K+10 Measured dc voltage, converter 4
K+11 Measured dc current, converter 4
K+12 Measured ac voltage, converter 5
K+13 Measured dc voltage, converter 5
K+14 Measured dc current, converter 5
K+15 Measured ac voltage, converter 6
K+16 Measured dc voltage, converter 6
K+17 Measured dc current, converter 6
K+18 Measured ac voltage, converter 7
K+19 Measured dc voltage, converter 7
K+20 Measured dc current, converter 7
K+21 Measured ac voltage, converter 8
K+22 Measured dc voltage, converter 8
K+23 Measured dc current, converter 8
VARs # Description
L VAC bus converter 1
L+1 PAC bus converter 1
L+2 QAC bus converter 1
L+3 VDC converter 1
L+4 IDC converter 1
L+5 Angle converter 1
L+6 VAC bus converter 2
L+7 PAC bus converter 2
L+8 QAC bus converter 2
L+9 VDC converter 2
L+10 IDC converter 2
L+11 Angle converter 2
L+12 VAC bus converter 3
VARs # Description
L+32 QAC bus converter 6
L+33 VDC converter 6
L+34 IDC converter 6
L+35 Angle converter 6
L+36 VAC bus converter 7
L+37 PAC bus converter 7
L+38 QAC bus converter 7
L+39 VDC converter 7
L+40 IDC converter 7
L+41 Angle converter 7
L+42 VAC bus converter 8
L+43 PAC bus converter 8
L+44 QAC bus converter 8
L+45 VDC converter 8
L+46 IDC converter 8
L+47 Angle converter 8
L+48
.
. Internal VARs required by model
.
L+56
ICONs # Description
Converter 1 flag:1, 2
0 Normal operation
M+1
1 Blocked
2 Unblocking
M+2 Converter 2 flag1, 2
M+3 Converter 3 flag1, 2
M+4 Converter 4 flag1, 2
M+5 Converter 5 flag1, 2
ICONs # Description
VARs # Description
This chapter contains a collection of data sheets for the VSC dc line models contained in the PSSE
dynamics model library.
15.1 VSCDCT
VSC DC Model with Two VSC Converters
STATEs # Description
P_ref_pu, Active power reference auxiliary input, pu on CONVERTER
K
MVA RATING (For VSC # 1).
Uac_int, AC Voltage controller integral output, pu on converter MVA rating
K+1
(For VSC # 1.
K+2 Uac_p_filt, AC voltage measured, pu (For VSC # 1).
P_ref_pu, Active power reference auxiliary input, pu on converter MVA
K+3
rating (For VSC # 2).
Uac_int, AC Voltage controller integral output, pu on converter MVA rating
K+4
(For VSC # 2).
K+5 Uac_p_filt, AC voltage measured, pu (For VSC # 2).
K+6 P_ret_pu, Power Order, pu on SBASE (For DC Line).
K+7 Plimit, Power Order Limit, pu on SBASE (For DC Line).
VARs # Description
P_aux, Active power reference auxiliary order, MW (For VSC # 1); uses
L
auxiliary signal index # 1
L+6 Q_ref, Reactive power order, pu on converter MVA rating (For VSC # 1).
L+7 P_ref, Interface Active power, pu on SBASE (For VSC # 1).
L+10 PELE, Active power, pu on SBASE (For VSC # 1).
L+11 QELE, Reactive power, pu on SBASE (For VSC # 1).
P_aux, Active power reference auxiliary order, MW (For VSC # 2); uses
L+12
auxiliary signal index # 2
L+18 Q_ref, Reactive power order, pu on converter MVA rating (For VSC # 2).
L+19 P_ref, Interface Active power, pu on SBASE (For VSC # 2).
L+22 PELE, Active power, pu on SBASE (For VSC # 2).
L+23 QELE, Reactive power, pu on SBASE (For VSC # 2).
L+24 P_ref_main, Active power main order, pu on SBASE (For DC Line).
L+32 Pzero_loss, DC system losses at zero current, MW (For DC Line).
L+33 Pdc_loss, DC losses, MW (For DC Line).
L+34
Isormod History, PSSE Variables for internal usage as well as: L+1
through L+5, L+8, L+9, L+13 through L+17, L+20, L+21, L+25 through
L+31.
L+45
Note: Smax (Converter MVA rating) should be non-zero in power flow input data when VSCDCT
model is used for stability simulations.
This chapter contains a collection of data sheets for the FACTS device (device modeled as FACTS
in power flow) models contained in the PSSE dynamics model library.
Model Description
CSTCNT Static Condenser (modeled as FACTS device in power flow).
SVSMO3U1 VSC based generic user written SVS model.
16.1 CSTCNT
FACTS Device Static Condenser (STATCON)
STATEs # Description
K Controlled voltage sensor
STATCOM main PI controller
K+1
integrator
K+2 STATCOM output Lag
STATCOM slow-reset PI controller
K+3
integrator
K+4 Short-term rating integrator
K+5 Lead-lag block
VARs # Description
STATCOM output, STATCOM terminal
L current (pu on STATCOM BASE MVA
(STBASE))
STATCOM reactive power output (pu
L+1
on STBASE)
L+2 STATCOM output in MVAr
L+3 Output of main PI controller
STATCOM lead-lag output before PI
L+4
controller
STATCOM voltage error signal into
L+5
lead-lag block
L+6 Reference voltage of STATCOM
Output of slow-secondary loop current
L+7
PI regulator
Measurement lead-lag transducer
L+8
output
L+9 Imax timer
L+10 Imax1*Ishrt
L+11 Timer for MSS
L+8 starting >I demand
L+13 Timer for MSS
L+14 starting <I demand
L+15 Timer for MSS1
L+16 Timer for MSS2
L+17 Timer for MSS3
L+18 Timer for MSS4
L+19 Timer for MSS5
L+20 Timer for MSS6
L+21 Timer for MSS7
L+22 Timer for MSS8
L+23 MSS timer monitors Tdelay+Tmssbrk
L+24 Deadband timer
L+25 I block timer
L+26 Time at which VBUS .GT. Vtrip
Where
BUSID is the FACTS device name (in single quotes)
Block Diagram
Block Diagram
Slow-Reset Control
Vrmax
Ki r flag1 = 1
K pr +
- s Vsched
+
S3 0 + +
Vrmin flag1 = 0
fla g1 = 1 Idbd
(close)
fla g1 = 0 Vrefmin Short-Term
(open) Vrefmax Ratin g Curve
-Idbd
Vsig vref
dbd > 0 : open Vemax Imax
dbd = 0 : close +
Vbus 1 + sTc1 Vr + err 1 + sTc2 Ki 1
Kp +
1 + sT b1 - 1 + sTb2 s 1 + sT o It (p.u.)
S0 S5 S1 S2
- Vemin -Imax
dbd
Logic
Deadband 0
flag2
Control
1
Xc 1 if Vr > = V1
Xc = Xc 2 if V 2 < Vr < V1
Xc 3 if Vr < = V2
STATCOM
over- and Non-linear
under-voltage Droop Control
tripping
functio n
16.2 SVSMO3U1
This model uses CONs starting with #_______ J,
and STATEs starting with #_______ K,
and VARs starting with #_______ L,
and ICON #_______ M.
States # Description
K Controlled voltage sensor
K+1 STATCOM main PI controller integrator
K+2 STATCOM output Lag
K+3 STATCOM slow-reset PI controller integrator
K+4 Short-term rating integrator
K+5 Lead-lag block
BUSID 'USRFCT' 'SVSMO3U1' 21, 1, 13, 44, 6, 27, ICON(M) to ICON(M+12), CON(J) to
CON(J+43) /
Where
Model Description
PVGU1 User written generator model to represent photo-voltaic (PV) systems
WT1G1 Direct connected (Type 1) generator
WT2G1 Induction generator with controlled external rotor resistor (Type 2)
WT3G1 Doubly-fed induction generator (Type 3)
WT3G2U Doubly-fed induction generator (Type 3), version 2
WT4G1 Wind generator model with power converter (Type 4)
W4G2U Wind generator model with power converter (Type 4), version 2
17.1 PVGU1
PV Converter
17.2 WT1G1
Direct Connected (Type 1) Generator
STATEs # Description
K Eq, transient flux q-component
K+1 Ed, transient flux d-component
K+2 Eq, subtransient flux q-component
K+3 Ed, subtransient flux d-component
K+4 Internal
VARs # Description
Admittance of initial condition MVAr
L
difference
L+1 Machine Q
L+2 Telec
17.3 WT2G1
Induction Generator with Controlled External Rotor Resistor (Type 2)
STATEs # Description
K Eq, transient flux q-component
K+1 Ed, transient flux d-component
K+2 Internal
VARs # Description
L Admittance of the hidden shunt
L+1 Machine Q
L+2 Telec
17.4 WT3G1
Doubly-Fed Induction Generator (Type 3)
STATEs # Description
K Converter lag for Ipcmd
K+1 Converter lag for Eqcmd
K+2 PLL first integrator
K+3 PLL second integrator
VARs # Description
Vx, Real component of Vterm in
L
generator ref. frame
VY, Imaginary component of Vterm in
L+1
generator ref. frame
Ixinj, Active component of the injected
L+2
current
Iyinj, Reactive component of the
L+3
injected current
ICON # Description
M Number of lumped wind turbines
17.5 WT3G2U
Doubly-Fed Induction Generator (Type 3)
STATEs # Description
K Converter lag for Ipcmd
K+1 Converter lag for Iqcmd
K+2 PLL first integrator
K+3 PLL second integrator
K+4 Voltage sensor for LVPL
VAR # Description
L deltaQ, overvoltage correction factor
ICON # Description
M Number of lumped wind turbines
WT4G1
Generic Wind Generator Model Data Sheets
17-10
PSSE 32.0.5
K+1 Converter lag for Eqcmd
K+2 Voltage sensor for LVACR
PSSE 32.0.5 Generic Wind Generator Model Data Sheets
PSSE Model Library WT4G1
VARs # Description
L through
For internal use
L+4
L+1 VAACC, previous Vterm angle
L+2 deltaQ, overvoltage correction factor
17.7 W4G2U
Wind Generator Model with Power Converter (Type 4)
STATEs # Description
K Converter lag for Ipcmd
K+1 Converter lag for Eqcmd
K+2 Voltage sensor for LVACR
VARs # Description
L through
For Internal Use
L+4
Model Description
PVEU1 User written electrical control model for photo-voltaic (PV) systems
WT2E1 Rotor resistance control model for Type 2 wind generator
WT3E1 Electrical control for Type 3 wind generator
WT4E1 Electrical control models for Type 4 wind generator
W4E2U Electrical control for Type 4 wind generator, version 2
18.1 PVEU1
Electrical Control Model for PV Converter
18.2 WT2E1
Rotor Resistance Control Model for the Type 2 Wind Generator
STATEs # Description
K Rotor speed filter
K+1 Power filter
K+2 PI integrator
WT3E1
Generic Wind Electrical Model Data Sheets
18-6
Electrical Control for Type 3 Wind Generator (for WT3G1 and WT3G2)
PSSE 32.0.5
J+11 IPMAX, Max active current limit
STATEs # Description
K Filter in voltage regulator
K+1 Integrator in voltage regulator
K+2 Filter in torque regulator
K+3 Integrator in torque regulator
K+4 Voltage sensor
K+5 Power filter
K+6 MVAR/Vref integrator
K+7 Verror/internal machine voltage integrator
K+8 Lag of the WindVar controller
K+9 Input filter of Pelec for PF fast controller
VARs # Description
L Remote bus ref voltage
VARs # Description
L+1 MVAR order from MVAR emulator
L+2 Q reference if PFAFLG=0 & VARFLG=0
L+3 PF angle reference if PFAFLG=1
L+4 Storage of MW for computation of compensated voltage
L+5 Storage of MVAR for computation of compensated voltage
L+6 Storage of MVA for computation of compensated voltage
ICONs # Description
M Remote bus # for voltage control; 0 for local voltage control
VARFLG:
M+1 0 Constant Q control
1 Use Wind Plant reactive power control
-1 Constant power factor control
VLTFLG:
0 Bypass terminal voltage control
M+21 1 Eqcmd limits are calculated as VTerm + XIQmin and
VTerm + XIQmax,
i.e., limits are functions of terminal voltage
2 Eqcmd limits are equal to XIQmin and XIQ max
M+3 From bus of the interconnection transformer
M+4 To bus of the interconnection transformer
M+5 Interconnection transformer ID
1 WT3E1 model can be used with WT3G1 as well as WT3G2 models. When used with WT3G1
model, it is recommended that ICON(M+2) be set to 1; and when used with WT3G2 model,
the ICON(M+2) be set to 2.
18.4 WT4E1
Electrical Control for Type 4 Wind Generator
STATEs # Description
K Filter in voltage regulator
K+1 Integrator in voltage regulator
K+2 Integrator in active power regulator
K+3 Active power regulator feedback
K+4 Voltage sensor
K+5 Power filter
K+6 MVAR/Vref integrator
K+7 Verror/Internal machine voltage integrator
K+8 Lag of the WindVar controller
K+9 Input filter of Pelec for PF fast controller
VARs # Description
L Remote bus reference voltage
L+1 Q reference if PFAFLG=0 & VARFLG=0
L+2 PFangle reference if PFAFLG=1
L+3 Power reference
ICONs # Description
M Remote bus # for voltage control; 0 for local control
PFAFLG:
M+1 1 if PF fast control enabled
0 if PF fast control disabled
VARFLG:
1 if Qord is provided by WindVar
M+2
0 if Qord is not provided by WindVar
if VARFLG=PFAFLG=0 then Qord is provided as a Qref=const
PQFLAG, P/Q priority flag:
M+3 0 Q priority
1 P priority
18.5 W4E2U
Electrical Control for Type 4 Wind Generator
STATEs # Description
K Filter in voltage regulator
K+1 Integrator in voltage regulator
K+2 Integrator in active power regulator
K+3 Active power regulator feedback
K+4 Voltage sensor
K+5 Power filter
K+6 MVAR/Vref integrator
K+7 Verror/Internal machine voltage integrator
K+8 Lag of the WindVar controller
K+9 Input filter of Pelec for PF fast controller
K+10 IQmax filter
VARs # Description
L Remote bus reference voltage
L+1 Q reference if PFAFLG=0 & VARFLG=0
L+2 PFangle reference if PFAFLG=1
L+3 Power reference
ICONs # Description
M Remote bus # for voltage control; 0 for local control
PFAFLG:
M+1 1 if PF fast control enabled
0 if PF fast control disabled
ICONs # Description
VARFLG:
1 if Qord is provided by WindVar
M+2
0 if Qord is not provided by WindVar
if VARFLG=PFAFLG=0 then Qord is provided as a Qref=const
PQFLAG, P/Q priority flag:
M+3 0 Q priority
1 P priority
Model Description
User written model to represent the linearized model of PV panels
PANELU1
output curve
WT12T1 Two mass turbine model for Type 1 and Type 2 wind generators
WT3T1 Mechanical system model for Type 3 wind generator
19.1 PANELU1
PV I-P Characteristics
CONs # Description
PDCMAX200, maximum power of
J panel at an irradiance of 200 W/m2, pu
on PDCMAX1000 base
PDCMAX400, maximum power of
J+1 panel at an irradiance of 400 W/m2,
pu on PDCMAX1000 base
PDCMAX600, maximum power of
J+2 panel at an irradiance of 600 W/m2, pu
on PDCMAX1000 base
PDCMAX800, maximum power of
J+3 panel at an irradiance of 800 W/m2, pu
on PDCMAX1000 base
PDCMAX1000, maximum power of
J+4 panel at an irradiance of 1000 W/m2,
pu on PDCMAX1000 base
VARs # Description
L DC power from PV array
19.2 WT12T1
Two-Mass Turbine Model for Type 1 and Type 2 Wind Generators
STATEs # Description
K Shaft twist angle, rad.
K+1 Turbine rotor speed deviation, pu
K+2 Generator speed deviation, pu
K+3 Generator rotor angle deviation, pu
VARs # Description
L Paero on the rotor blade side, pu
L+1 Initial rotor slip
L+2 Initial internal angle
19.3 WT3T1
Mechanical System Model for Type 3 Wind Generator (for WT3G1 and WT3G2)
STATEs # Description
K Shaft twist angle, rad.
K+1 Turbine rotor speed deviation, pu
K+2 Generator speed deviation, pu
K+3 Generator rotor angle deviation, pu
VARs # Description
L Paero on the rotor blade side, pu
L+1 Initial rotor slip
L+2 Initial internal angle
L+3 Initial pitch angle
L+4 Paero initial
Model Description
User written model to represent the linearized model of PV panels
IRRADU1
solar irradiance profile.
WT3P1 Pitch control model for Type 3 wind generator
20.1 IRRADU1
PV Irradiance Profile
CONs # Description
J TIME1, Time of first data point, sec
J+1 IRRADIANCE1, Irradiance at first data point, W/m2
J+2 TIME2, Time of second data point, sec
J+3 IRRADIANCE2, Irradiance at second data point, W/m2
J+4 TIME3, Time of third data point, sec
J+5 IRRADIANCE3, Irradiance at third data point, W/m2
J+6 TIME4, Time of forth data point, sec
J+7 IRRADIANCE4, Irradiance at forth data point, W/m2
J+8 TIME5, Time of fith data point, sec
J+9 IRRADIANCE5, Irradiance at fith data point, W/m2
J+10 TIME6, Time of sixth data point, sec
J+11 IRRADIANCE6, Irradiance at sixth data point, W/m2
J+12 TIME7, Time of seventh data point, sec
J+13 IRRADIANCE7, Irradiance at seventh data point, W/m2
J+14 TIME8, Time of eigth data point, sec
J+15 IRRADIANCE8, Irradiance at eigth at point, W/m2
J+16 TIME9, Time of ninth data point, sec
J+17 IRRADIANCE9, Irradiance at ninth data point, W/m2
J+18 TIME10, Time of tenth data point, sec
J+19 IRRADIANCE10, Irradiance at tenth data point, W/m2
NOTE: A maximum of 10 pairs of time versus irradiance may be specified. The unused pairs should
be entered as zero. T1 should be greater than 0 as the initial irradiance calculated from the load
flow output.
20.2 WT3P1
Pitch Control Model for Type 3 Wind Generator (for WT3G1 and WT3G2)
Note: When a WT operates with a partial output, the DSTATE(K+2) may show
INITIAL CONDITION SUSPECT. In this case no actions are needed.
STATEs # Description
K Output lag
K+1 Pitch control
K+2 Pitch compensation
Model Description
WT12A1 Pseudo-governor model for Type 1 and Type 2 wind generators
21.1 WT12A1
Pseudo-Governor Model for Type 1 and Type 2 Wind Generators
STATEs # Description
K Power filter
K+1 PI integrator
K+2 Output filter 1
K+3 Output filter 2
VARs # Description
L Reference
L+1 Power reference
This chapter contains a collection of data sheets for the switched shunt models contained in the
PSSE dynamics model library.
Model Description
CHSVCT SVC for switched shunt
CSSCST SVG for switched shunt
SWSHNT Switched shunt model
SVSMO1U1 User written model for continuously controled SVC
SVSMO2U1 User written model for discretely controled SVC
22.1 CHSVCT
SVC for Switched Shunt
J+6 T3
J+7 T4
J+8 K
J+9 BFMAX
J+10 BFMIN
J+11 TD1
J+12 BMAX
J+13 BMIN
J+14 Km
J+15 Tw
J+16 TD3
J+17 TM1
J+18 TM2 > 0
J+19 TM3
J+20 TM4
J+21 VSMAX
J+22 VSMIN
STATEs # Description
K First VSF lag-lead
K+1 Second VSF lag-lead
K+2 Thyristor
K+3 First thyristor time delay
K+4 Second thyristor time delay
K+5 SMF control
K+6 First SMF time delay
K+7 Second SMF time delay
K+8 First SMF lead-lag
K+9 Second SMF lead-lag
VARs # Description
L Other signals
L+1 VREF
L+2 Y (system base)
L+3 Voltage clamp timer
L+4 I Line (system base)
22.2 CSSCST
SVG for Switched Shunt
J+4 T4 (sec)
J+5 T5 (sec)
J+6 VMAX, Mvars
J+7 VMIN, Mvars
J+8 VOV (override voltage) (pu)
STATEs # Description
K First regulator
K+1 Second regulator
K+2 Thyristor
VARs # Description
L Other signals
L+1 VREF
L+2 Y (system base)
L+3 BREF
ICON # Description
M IB, remotely regulated bus
22.3 SWSHNT
Switched Shunt Model
VARs # Description
L Initial voltage
L+1 Timer
L+2 Maximum reactive
L+3 Maximum capacitive
Tentative
CONs # Description
Value
UVSBmax, max cap limit during undervoltage (assumed filter
J
size), pu on SBASE
J+1 UV1, undervoltage setting 1, p.u.
J+2 UV2, undervoltage setting 2, p.u.
J+3 UVT, undervoltage trip setting, p.u.
J+4 OV1, overvoltage setting 1, p.u.
J+5 OV2, overvoltage setting 2, p.u.
J+6 UVtm1, undervoltage trip time 1, sec.
J+7 UVtm2, undervoltage trip time 2, sec.
J+8 OVtm1, overvoltage trip time 1, sec.
J+9 OVtm2, overvoltage trip time 2, sec.
J+10 Xs1, slope/droop, p.u. on SBASE
J+11 Xs2, slope/droop, p.u. on SBASE
J+12 Xs3, slope/droop, p.u. on SBASE
J+13 Vup, upper voltage break-point for non-linear Slope/droop, p.u.
J+14 Vlow, lower voltage break-point for non-linear Slope/droop, p.u.
J+15 Tc1, voltage measurement lead time constant, sec.
J+16 Tb1, voltage measurment lag time constant, sec.
J+17 Tc2, lead time constant
J+18 Tb2, lag time constant
J+19 Kpv, proportional gain, p.u.
J+20 Kiv, integral gain, p.u./sec.
J+21 Vemax, voltage error max, p.u.
J+22 Vemin, voltage error min, p.u.
J+23 T2, thyristor firing sequence control delay, T2>0, sec.
Bshrt, short-term max. suceptance of SVC (short-term rating) ,
J+24
p.u. on SBASE
Bmax, max. suceptance of SVC (continuous rating), p.u. on
J+25
SBASE
J+26 Bmin, min. suceptance of SVC, p.u. on SBASE
Tentative
CONs # Description
Value
J+27 Tshrt, duration of short-term rating, sec.
J+28 Kps, proportional gain of slow suceptance control, p.u.
J+29 Kis, integral gain of slow suceptance control, p.u./sec.
J+30 Vrmax, max. output of slow suceptance control, p.u.
J+31 Vrmin, min. output of slow suceptance control, p.u.
Vdbd1, steady-state Voltage deadband; SVC is inactive
J+32
between Vref+Vdbd1 to Vref-Vdbd1, p.u.
J+33 Vdbd2, inner deadband, p.u.
J+34 Tdbd, Vdbd2 locked time, sec.
PLLdelay, delay in recovering if voltage remains below UV1 for
J+35
longer than UVtm1, sec.
xeps, small delta added to the susceptance bandwidth of the
J+36 slow-susceptance regulator in order to ensure its limits are not
exactly identical to the MSS switching point, p.u.
J+37 Blcs, larger threshold for switching MSCs, MVAr
J+38 Bscs, smaller threshold for switching MSCs, MVAr
J+39 Blis, larger threshold for switching MSRs, MVAr
J+40 Bsis, smaller threshold for switching MSRs, MVAr
J+41 Tmssbrk, time for MSS breaker to operate, sec.
J+42 Tdelay1, time delay for larger threshold, sec.
Tdelay2, Time delay for smaller threshold (should be much
J+43
larger than Tdelay1), sec.
Tout, time cap. bank should be off before switching back on,
J+44
sec.
J+45 Vrefmin, lower limit of Vref, p.u.
J+46 Vrefmax, upper limit of Vref, p.u.
SKATE # Description
K Controlled voltage sensor
K+1 SVC main PI controller integrator
K+2 SVC output lag
K+3 SSC PI controller imtegrator
K+4 SVC lead/lag
VAR # Description
L SVC output admittance, p.u. on SBASE
SVC PI controller output, p.u. on
L+1
SBASE
VAR # Description
L+2 SSC PI controller output, p.u.
L+3 Undervoltage timer, sec.
Rating dependent on voltage, p.u. on
L+4
SBASE
L+5
through Timers, delays set up by the model
L+18
L+19 Vmsrd, Vreg lead/lag output
L+20
through Timers set up by the model
L+22
L+23 SVC VREF, p.u.
L+24 SVC VSCHED, p.u.
L+25 optional POD input
SVC lead-lag output before PI
L+26
controller
L+27 SVC voltage error
L+28 SVC output in MVAR
ICON # Description
M SVC remote bus #_
M+1 MSS bus #
flag1 MSS switching: 0 - no MSS
M+2 switching, 1 - MSS switching on Q
[MVAr]
flag2 droop: 0 - linear droop; 1 - non-
M+3
linear droop
M+4
Internal ICONs (Flags used by the
through
model). (to be input as 0 in DYRE file)
M+13
Isvc
SVC over-
and under-
voltage X
tripping
function
22-11
Switched Shunt Model Data Sheets PSSE-32.1
SVSMO2U1
PSS E Model Library
22.5 SVSMO2U1
This model is at system bus #______ IBUS,
This model uses CONs starting with #_______ J,
and STATEs starting with #_______ K,
and VARs starting with #_______ L,
and ICON #_______ M.
Tentative
CONs # Description
Value
J T1, time delay of the SVC voltage sensor, sec.
J+1 D, SVC droop, p.u. Voltage/p.u. Current (SBASE)
J+2 Vdbmin, SVC voltage error deadband min, p.u
J+3 Vdbmax, SVC voltage error deadband max, p.u.
Vlow1, SVC voltage dependent gain table low voltage threshold
J+4
1, p.u.
Vlow2, SVC voltage dependent gain table low voltage threshold
J+5
2, p.u.
Vhigh1, SVC voltage dependent gain table high voltage
J+6
threshold 1, p.u.
Vhigh2, SVC voltage dependent gain table high voltage
J+7
threshold 2, p.u.
J+8 KP_VLow1, SVC prop. gain for VLow2<V<VLow1, p.u.
J+9 KP_VLow2, SVC prop. gain for V<VLow2, p.u.
J+10 KP_VHigh1, SVC prop. gain for VHigh2>V>VHigh1, p.u.
J+11 KP_VHigh2, SVC prop. gain for V>VHigh2, p.u.
J+12 KI_VLow1, SVC integr. gain for VLow2<V<VLow1, p.u./sec.
J+13 KI_VLow2, SVC integr. gain for V<VLow2, p.u./sec.
J+14 KI_VHigh1, SVC integr. gain for VHigh2>V>VHigh1, p.u./sec.
J+15 KI_VHigh2, SVC integr. gain for V>VHigh2, p.u./sec.
J+16 KP_N, SVC normal prop. Gain, p.u.
J+17 KI_N, SVC normal integr. Gain, p.u./sec.
J+18 TDON, SVC switching on delay, sec.
J+19 KPS, prop. gain of SSC PI-controller, p.u.
J+20 KIS, integral gain of SSC PI-controller, p.u./sec.
J+21 Vrmax, max limit of SSC PI controller, p.u.
J+22 Vrmin, min limit of SSC PI controller, p.u.
J+23 Vrefmax, max limit of SVC Vref, p.u.
J+24 Vrefmin, min limit of SVC Vref, p.u.
J+25 Brefmax, SSC range upper limit, p.u.
Tentative
CONs # Description
Value
J+26 Brefmin, SSC range lower limit, p.u.
J+27 Vcut, SVC cut-off voltage, p.u. Note: SVC is disabled if V<Vcut
BMSS1, Available MSS admittance on MSS Bus 1, p.u. on
J+28
SBASE
BMSS2, Available MSS admittance on MSS Bus 2, p.u. on
J+29
SBASE
BMSS3, Available MSS admittance on MSS Bus 3, p.u. on
J+30
SBASE
BMSS4, Available MSS admittance on MSS Bus 4, p.u. on
J+31
SBASE
BMSS5, Available MSS admittance on MSS Bus 5, p.u. on
J+32
SBASE
BMSS6, Available MSS admittance on MSS Bus 6, p.u. on
J+33
SBASE
BMSS7, Available MSS admittance on MSS Bus 7, p.u. on
J+34
SBASE
BMSS8, Available MSS admittance on MSS Bus 8, p.u. on
J+35
SBASE
J+36 SPARE
J+37 MSS_ON, MSS switching on time delay, sec.
J+38 MSS_ON1, MSS subsequent switching on time delay, sec.
J+39 MSS_OFF, MSS switching off time delay, sec.
MSS demand lower limit for soft switching, p.u.
J+40 Note: Smoothing works if the SVC demand does not exceed
CON(J+52)*TotalSVCcaps. If it does - no smoothing, all reactive
power resources are mobilized.
MSC_THRESHOLD, p.u.
J+41 Note: MSC cap is switched on if MSS demand exceeds this
threshold: convenient to disable MSCs
MSR_THRESHOLD, p.u.
J+42 Note: MSS reactor is switched on if MSC demand is below this
threshold: convenient to disable MSRs
MSS_Vcutoff, MSS cut-off voltage, p.u.Note: this feature is
J+43
disabled if V<MSS_Vcutoff
MSS_SWITCH_ALLOWED, a number of permissible MSS
J+44
switchings
MSS_COOL_ALLOWED, MSS cooling down time, sec.
J+45 Note: interval of time when the next switching on of the same
MSS is possible
Tentative
CONs # Description
Value
VUPLIM, overvoltage protection threshold, p.u., measured on
J+46
the SVC LV bus
SKATE # Description
K Controlled voltage sensor
K+1 Main PI controller integrator
K+2 SSC PI controller integrator
Tentative
VARs # Description
Value
L Total SVC capacitor admittance, p.u. on SBASE
L+1 Total SVC reactor admittance, p.u. on SBASE
L+2 Current SVC admittance, p.u. on SBASE
L+3 SVC Vref, p.u.
L+4 Admittance demand from PI controller, p.u. on SBASE
L+5 SVC Look-up table output, p.u. on SBASE
L+6
through Delay memory
20
L+21 SVC Bref, p.u.
L+22 SVC Vsched, scheduled voltage, p.u.
L+23 SSC PI output, p.u.
L+24 Input for MSS switching, p.u. on SBASE
L+25 MSS total capacitors, MVAr
L+26 MSS total reactors, MVAr
L+27 Voltage error, p.u.
L+28 MSS to SVC "smoothing" signal
L+29
through Internal VARs
44
L+45 Auxiliary (stabilizer) signal
L+46
through Internal VARs
L+117
ICON # Description
M Bus # the first half of SVC is connected to
Bus # the second half of SVC is connected to. Must
M+1
be 0 if one bus only.
ICON # Description
M+2 Remote bus # for voltage control
The first block with capacitors of the switched shunt
M+3
in load flow (to be input as 0 in DYRE file)
The last step on of the switched shunt in load flow
M+4
(to be input as 0 in DYRE file)
M+5
through MSS bus #, 0 otherwise
M+12
internal flag (Flag to switch MSS). (to be input as 0 in
M+13
DYRE file)
M+14
through Internal ICONs (to be input as 0 in DYRE file)
M+37
Table 23-2 lists those models whose model calls are generated in subroutine CONET by activity
DYRE.
Table 23-3 lists those models whose model calls are generated automatically in subroutine CONEC
and CONET by activity DYRE.
Table 23-4 lists those models for which either an explicit model call may be manually inserted into
the subroutine CONEC or CONET as appropriate, or the user can let PSSE generate implicit
model calls by using activities CHAN or CHSB.
Table 23-5 lists those models for which the model calls must be entered manually into the subrou-
tine CONEC or CONET as appropriate.
23.1 DCPOW
Power Control for dc System
DELDCP(I)
This model uses CONs starting with #__________ J, SETVAL(I) DCREF(I)
DCPOW
and STATEs starting with #__________ K, VDCR(I)
and VARs starting with #__________ L, VDCI(I)
and ICONs starting with #__________ M.
STATEs # Description
K VDCP, sensed voltage for power controller (pu)
K+1 RESET, dc reset (pu)
VARs # Description
L MYSET, auxiliary input (pu)
L+1 DCREFR, dc reference controller output (pu)
L+2 Internal VAR
MYSET(L)
+
+
SETVAL(I)/DCRATE
+
DELDCP(I)
(2)
+
+ P0 MDC(I) +
DCREF(I)
SETVAL(I)/PRATE P0 VDCP (1)
+ DCREF(I)*DELT(I) +
VDCP
MYSET(L) +
RESET
VPMAX RESETG*
S
K+1
KA
0.0
1 + sTVDCP DCR(I)
K
1.0
VPMIN
SETVAL(I)>0 SETVAL(I)<0
VDCR(I) VDCI(I)
23.2 VFTU1
GE Variable Frequency Transformer
0 'USRMDL' 0 'VFTU1' 8 1 4 42 14 19
V1
Plimo GE VFT:
+ 1 Tr n Base
Min
sTVD SBase
Governor Control
gov _ lim
-
V2 State( K+8)
VPX V P1
TUP
TVD
TDOWN
VFT Governor
F p_M ax
Output
Pcmd-f
Var(L +11)
Kpi
VFT P ower
s
Pvft +
1 K+3
Var(L+1)
sTd Fpstab -F p_M ax
or - +
Var(L+2) ST AT E(K+13)
Kpp
Fsrlim +
DFth: Va r(L+6) Fratelim Fp_Max
V FT Drive
+ +
1 1 - S ystem
- TFSR S
DFth : Va r(L +7) Va r(L +12)
- -
-Frate lim K+4 -Fp_M ax spd_cmd
-Fsr lim
m
Va r(L+13)
STATE (K 1)
Fp _ Sta blim
+ +
1 + +
sTd F pst ab K pstab
- -
GE VFT: K+5 -Fp_Stablim
1
Var(L+11)
Pcmd _f Trq_Acel _Lim
V th 1
V ar(L+8)
TRQ _Vdtl_min -
+ 1 +
x x TRQ _min_lim
sTVdtl
Max Var(L+18)
-
K+7 -1
Vth 2
Var(L+9) -1
TRQ _Vdtl_max
GE VFT:
Torque Limiter
TRQ_max_lim
Var(L+17) angle( )
Var(L)
Notes:
The real power flowing across the VFT is stored in VAR(L+1) and VAR(L+2) for the from and to side
flows respectively, with the convention of positive flow from the bus into the VFT. Similarly the reac-
tive power is stored in VAR(L+4) and VAR(L+5). Note that the default channels for branch flow for
the VFT should NOT be used as they do not generally take into account the movement in VFT. That
is, if plotting the VTF flow is desired, the VFT model VARS should be used.
At initialization, the initial active power flow is stored in Pcmd. To simulate a change in the active
power flow setpoint, change Pcmd, VAR(L+10), to the new setpoint. Note that the relative direction
of the power flow must be taken into account.
When the VFT rotates by an angle greater than the admittance re-factorizing angle, CON(J+40),
the power flow admittance matrix will be re-factorized. This re-factorization speeds up the network
solution and prevents a potential divergent solution when the VFT alters the power flow significantly
from the initial conditions. As a starting point, Siemens PTI recommends a value of 20 degrees for
this re-factorization angle, but this angle may need to be adjusted based on the characteristics of
the power system modeled.
23.3 RUNBK
Eel River and Madawaska dc Line Runback Model
CALL RUNBK(I,M,J,K,L,)
This is dc line (internal dc line number) #_______ I,
This model uses CONs starting with #_______ J,
and STATEs starting with #_______ K,
and VARs starting with #_______ L,
This model uses ICONs starting with #_______ M.
STATE # Description
K Level of SETVAL
VARs # Description
L Starting time for ramp
L+1 Final time for ramp
Note: This model adjusts SETVAL, so it does not require any additional statements in CONEC.
This model is called from the CEEL/TEEL dc line model. To call it directly from CONEC requires that
it be manually introduced into your PSSE setup as:
23.4 ULCFB1
Turbine Load Controller Model
STATEs # Description
K Measured Power
K+1 Integrator
VARs # Description
L Pmwset
L+1 Deadband input
L+2 Deadband output
L+3 Pref 0
This model can be used with the following turbine governor models:
23.5 DCTC1
Online dc Tap Changer Model
VARs # Description
L Time delay (rectifier)
L+1 Tap changer timer (rectifier)
L+2 Subsequent timer (rectifier)
L+3 Time delay (inverter)
L+4 Tap changer timer (inverter)
L+5 Subsequent timer (inverter)
23.6 INTFLW
Interface MW and Mvar Flow Model
Note: Add this model to a simulation database using a dynamic raw data record of the form:
0 USRMDL 0 'INTFLW' 0 2 3 0 0 0 0 0 0 /
23.7 LOEXR1
Loss of Excitation Distance Relay
CONs # Description
J T1, zone 1 operating time (cycles)
J+1 R1, zone 1 reach (diameter in pu)
J+2 A1, zone 1 centerline angle (degrees)
J+3 D1, zone 1 center distance (pu)
J+4 T2, zone 2 operating time (cycles)
J+5 R2, zone 2 reach (diameter in pu)
J+6 A2, zone 2 centerline angle (degrees)
J+7 D2, zone 2 center distance (pu)
J+8 T3, zone 3 operating time (cycles)
J+9 R3, zone 3 reach (diameter in pu)
J+10 A3, zone 3 centerline angle (degrees)
J+11 D3, zone 3 center distance (pu)
J+12 VPV, voltage pickup value (pu)
J+13 STB, self trip breaker time (cycles)
VARs # Description
L Apparent R
L+1 Apparent X
L+2
L+3 VARS required for internal program
L+4 logic
L+5
2. The center distances are normally negative since R and X are assumed looking out
from terminals.
4. The voltage pickup value should be set to a high value (10.0 pu) to disable it.
Angle
23.8 OLPS1
Online Phase Shifter Model
VARs # Description
L Time delay
L+1 Phase shifter timer
L+2 Subsequent timer
L+3 MW flow
23.9 OLTC1
Online Tap Changer Model
VARs # Description
L Time delay
L+1 Tap changer timer
L+2 Subsequent timer
23.10 OLPS3
Online Phase Shift Regulator Model for Three-Winding Transformers
VARs # Description
L Time delay
L+1 Phase shift timer
L+2 Subsequent timer
L+3 MW flow
23.11 OLTC3
Online Tap Changer Model for Three-Winding Transformers
VARs # Description
L Time delay
L+1 Tap changer timer
L+2 Subsequent timer
23.12 SAT2
Transformer Saturation
J+5 I3
J+6 4
J+7 I4
L Acceleration factor
N Transformer MVA base
VAR # Description
K Memory
4
2 3
1
1+f
= ----------
23.13 SWCAP
Switched Capacitor Bank Model
VAR # Description
L Memory
23.14 SWSHN1
Switched Shunt Model
VARs # Description
L Initial voltage
L+1 Timer
L+2 Maximum reactive
L+3 Maximum capacitive
Notes:
1. The model allows three different choices for CON(J) and CON(J+3). If the user inputs
0 for the first quantity, the high-voltage pickup and low-voltage pickup will be the values
specified in power flow (VIN1 or VIN2). The second input choice is to specify a voltage
deviation of less than or equal to 0.5 (DELVUP or DELVDO). The model expects a neg-
ative voltage deviation value (DELVDO) for low-voltage switching. Lastly, the input
values can be per-unit voltages (VHI or VLO) above and below which pickup times
activate.
2. ICON (M+2) specifies the limit on the number of switches allowed. If the maximum
number of switches exceed this value, further model action is disabled.
23.15 CASEA1
Intermountain Power Project HVDC Model
STATEs # Description
K DCR, direct current at rectifier (amps)
K+1 DCI, direct current at inverter (amps)
K+2 VDCMR, measured dc voltage at rectifier
K+3 VDCMI, measured dc voltage at inverter
K+4 ALPHR, rectifier firing angle (degrees)
K+5 ALPHI, inverter firing angle (degrees)
K+6 RESETR, rectifier current controller state
K+7 RESETI, inverter current controller state
K+8 VDCOLR, rectifier VDCL sensed voltage
K+9 VDCOLI, inverter VDCL sensed voltage
K+10 VDCP, power control sensed voltage
K+11 MAKEUP, current margin makeup current
K+12 DTHVRR, rectifier Thevenin resistance deviation
K+13 DTHVRX, rectifier Thevenin reactance deviation
K+14 DTHVIR, inverter Thevenin resistance deviation
K+15 DTHVIX, inverter Thevenin reactance deviation
K+16 Frequency controller state
K+17 Frequency controller state
K+18 Frequency controller state
K+19 Voltage controller state
K+20 Voltage controller state
K+21 Voltage controller state
VARs # Description
L DCREF, dc reference
L+1 GAMINR, minimum rectifier margin angle
L+2 GAMINI, minimum inverter margin angle
L+3 ALFMNR, minimum rectifier firing angle
L+4 ALFMNI, minimum inverter firing angle
L+5 ALPHAR, rectifier firing angle
L+6 ALPHAI, inverter firing angle
L+7 PACR, rectifier power
L+8 QACR, rectifier reactive power
L+9 PACI, inverter active power
L+10 QACI, inverter reactive power
L+11 GAMAR, rectifier margin angle
L+12 GAMAI, inverter margin angle
L+13 BUMP, initialization current setpoint adjustment
L+14 DESDCR, desired rectifier direct current (VDCL output)
L+15 DESDCI, desired inverter direct current (VDCL output)
L+16 DELHZ, error signal into frequency controller
DELREF, frequency controller output, modification to power or
L+17
current setpoint
L+18 DELV, error signal into voltage controller
DELGAM, voltage controller output, modification to margin angle
L+19
setpoint
L+20 DESV, desired dc voltage
L+21 Initial rectifier EP
L+22 Initial inverter EPP
FORCUP, modification to inverter current controller error signal to
L+23
reduce the margin angle when dc voltage is low
L+24 STARTM, time at which forcing starts
L+25 STOPTM, time at which forcing stops
L+26 THEVRR, rectifier Thevenin voltage real part
L+27 THEVRX, rectifier Thevenin voltage imaginary part
L+28 THEVIR, inverter Thevenin voltage real part
L+29 THEVIX, inverter Thevenin imaginary part
L+30 MYGAM, external modification to inverter margin angle
L+31 MYALF, external modification to rectifier firing angle
L+32 MYSET, external modification to current setpoint
VARs # Description
L+33 MYDCR, external modification to rectifier current after VDCL
L+34 MYDCL, external modification to inverter current after VDCL
L+35 PWDCI, external modification to power setpoint
L+36 DCSETI, dc setpoint
L+37 EDCR, rectifier dc voltage
L+38 EDCI, inverter dc voltage
L+39 EMINR, rectifier minimum commutation voltage
L+40 EMINI, inverter minimum commutation voltage
L+41 RNEGR, rectifier negative sequence resistance
L+42 XNEGR, rectifier negative sequence reactance
L+43 RNEGI, inverter negative sequence resistance
L+44 XNEGI, inverter negative sequence reactance
L+45 AVACR, ac faulted phase voltage at rectifier
L+46 AVACI, ac faulted phase voltage at inverter
L+47 VDPP, hysteresis voltage
23.16 CDCRL
Two-Terminal HVDC With Current Control and Line Dynamics
STATEs # Description
K VDCL, voltage at the rectifier (pu)
K+1 VDCL, voltage at the inverter (pu)
Voltage control inverter firing angle
K+2
modification (degrees)
K+3 DCV measurement for voltage control (pu)
K+4 Rectifier current controller state
K+5 Inverter current controller state
K+6 Rectifier current controller state
K+7 Inverter current controller state
K+8 Rectifier direct current (amps)
K+9 Inverter direct current (amps)
K+10 Rectifier Thevenin resistance update
K+11 Rectifier Thevenin reactance update
K+12 Inverter Thevenin resistance update
K+13 Inverter Thevenin reactance update
K+14 Rectifier current controller state
K+15 Inverter current controller state
VARs # Description
L dc order from power control (pu)
L+1 DELDCP, modification in power order setpoint
L+2 DELVDC, modification in dc voltage setpoint
L+3 Rectifier minimum margin angle
L+4 Inverter minimum margin angle
L+5 Rectifier minimum firing angle
L+6 Inverter minimum firing angle
L+7 Rectifier maximum firing angle
L+8 Inverter maximum firing angle
L+9 Rectifier firing angle
L+10 Inverter firing angle
L+11 Rectifier active power (MW)
L+12 Rectifier reactive power (Mvar)
VARs # Description
L+13 Inverter active power (MW)
L+14 Inverter reactive power (Mvar)
L+15 Rectifier margin angle
L+16 Inverter margin angle
L+17 Rectifier dc voltage (pu)
L+18 Inverter dc voltage (pu)
L+19 Rectifier VDCL current order (pu)
L+20 Inverter VDCL current order (pu)
L+21 Inverter margin angle from voltage control (pu)
L+22 Direct current at rectifier (pu)
L+23 Direct current at inverter (pu)
DELREF, external change in direct current reference
L+24
(pu)
L+25 MYGAM, external change in inverter margin angle
MYALF, external change in rectifier minimum firing
L+26
angle
MYDCR, external change in rectifier direct current order
L+27
after VDCL
MYDCI, external change in inverter direct current order
L+28
after VDCL
L+29 Saved value of EP
L+30 Saved value of EPP
L+31 Rectifier minimum commutation voltage (pu)
L+32 Inverter minimum commutation voltage (pu)
L+33 Rectifier ac voltage (pu)
L+34 Inverter ac voltage (pu)
L+35 Rectifier Thevenin resistance
L+36 Rectifier Thevenin reactance
L+37 Inverter Thevenin resistance
L+38 Inverter Thevenin reactance
d
DC(K) GAIN(J) (1 + sTDC1 (J)) MAX(J)
dt
(1 + sTDC2 (J)) ALFMX(L) +
1
GI(J)
+ S + DMXANG(L)
d ALPHA(L)
DELREF(L) DCREF(I)*DELT(I) MIN(J)
dt
GP(J) +
+ + ALFMN(L)
+ DESDC(L) GAIN(J) (1 +sTDES1 (J))
DCREF(I) VDCL
(1 + sTDES2 (J))
MYDC(L)
1
1 + sTVDCL
V3(J)
V1(J)
VDC
Current Control
DELVDC(I)
+ 1 + 1 VGAIN
VDCI(I) DMXANG(K)
1 +sTVDCI (J) VDCRAT(J)*1000 S
+
RCOMP(I) VSCHED(I)
DCI(K)
Voltage Control
23.17 CDCVUP
Two-Terminal HVDC With Current Control
STATEs # Description
K Rectifier VDCL voltage
K+1 Inverter VDCL voltage
VARs # Description
L dc order from power control (pu)
L+1 DELDCP, modification in power order setpoint
L+2 DELVDC, modification in dc voltage setpoint
L+3 Rectifier minimum margin angle
L+4 Inverter minimum margin angle
L+5 Rectifier minimum firing angle
L+6 Inverter minimum firing angle
L+7 Rectifier maximum firing angle
L+8 Inverter maximum firing angle
L+9 Rectifier firing angle
L+10 Inverter firing angle
L+11 Rectifier active power (MW)
L+12 Rectifier reactive power (Mvar)
L+13 Inverter active power (MW)
L+14 Inverter reactive power (Mvar)
VARs # Description
L+15 Rectifier margin angle
L+16 Inverter margin angle
L+17 Rectifier dc voltage (pu)
L+18 Inverter dc voltage (pu)
L+19 Rectifier VDCL current order (pu)
L+20 Inverter VDCL current order (pu)
L+21 Direct current (pu)
L+22 Initial minimum margin angle offset
DELREF, external change in direct current
L+23
reference (pu)
MYGAM, external change in inverter margin
L+24
angle
MYALF, external change in rectifier minimum
L+25
firing angle
MYDCR, external change in rectifier direct
L+26
current order after VDCL
MYDCI, external change in inverter direct
L+27
current order after VDCL
L+28 Saved value of EP
L+29 Saved value of EPP
L+30 Rectifier minimum commutation voltage (pu)
L+31 Inverter minimum commutation voltage (pu)
L+32 Rectifier ac voltage (pu)
L+33 Inverter ac voltage (pu)
DELREF(L) DCREF(I)*DELT(I)
+ +
+
DCREF(I) VDCL DESDC
MYDC(L)
1
1 + sTVDCL
+ GI
DESDCR(L) DANG
V3(J) S
V1(J)
VDC DESDCI(L)
Control
Rectifier Angles
Control Not on Limits Rectifier Control
GPI
(DESDCR DESDCI)
GPR + GPI
GPR
(DESDCR DESDCI)
GPR + GPI
DESDCR
DC
DESDCI
23.18 CEELRI
dc Line Model
STATEs # Description
K VDCOL, dc or ac voltage (kV or pu), VDCOL
K+1 Current order (amps)
K+2 Power controller dc voltage (V), VDCP
VARs # Description
L Other signals, MW
L+1 RESTR, time unblocks or unbypasses (sec)
L+2 VRF, voltage setpoint multiplier
L+3 CRF, current setpoint multiplier
L+4 VCOMP, compensated dc voltage (V)
L+5 PACR, rectifier ac real power (pu)
L+6 QACR, rectifier ac reactive power (pu)
L+7 PACI, inverter ac real power (pu)
L+8 QACI, inverter ac reactive power (pu)
L+9 VDCI, inverter dc voltage (V)
L+10 VDCR, rectifier dc voltage (V)
L+11 DC, dc current (amps)
VARs # Description
L+12 ALFA, alpha (degrees)
L+13 GAMA, gamma (degrees)
L+14 Other VDC signals (kV)
L+15 TIMER, rectifier blocking and unblocking, timer
L+16 TIMEI, inverter blocking and unblocking, timer
L+17 TIBYP, inverter bypass and unbypass timer
ICONs # Description
Voltage ramp flag:
0 Normal
M 1 Blocked
2 Ramping
-1 Bypassed
Current ramp flag:
0 normal
M+1 1 blocked
2 ramping
-1 bypassed
0 current limit uses inverter VDC
M+2
> 0 current limit uses VAR (ICON(M+2))
CRAMP
Other Signals 0.0 CON(J+13)
VAR(L) (MW)
When When
ICON(M+1)=0 ICON(M+1)=2
1000.
VSCHED(I)
(amps) 1.0
+
+ 1
SETVAL(I) Current Control
s
(amps) (MDC(I)=2)
CRF
RLOW VAR(L+3)
1
1 + sTIDR STATE VDCOL
CON(J+3) (K+1) C0
+
106 CON(J+14)
SETVAL(I) Power Control
VDCP (MDC(I)=1)
(MW)
+ (V) VVDCOL
VDCP STATE(K)
Other Signals STATE(K+2)
VAR(L) (MW) CON(J+2) Up
1 1
CON(J+16)*VSCHED(I) 1 + sTVP 1 + sTVDCOL
CON(J+31) CON(J+4) Down
1000
1000*VCMODE(I)
CON(J+11)*VSCHED(I)
If (MDC(I) = 1), RLOW =
1000 * SETVAL (I)
CON(J+11)
If (MDC(I) = 2), RLOW =
SETVAL (I)
dc Setpoint Control
VAR(L+14)
Other Signals
(kV)
+
+
VSCHED(I) VSET (kV)
(kV)
VAR(L+2) 1.0
1
s
CON(J+10)
VSCHED(I)
0.0 VRAMP
CON(J+12)
23.19 CHESVC
SVC for Switched Shunt
J+3 TD2
J+4 T1
J+5 T2 > 0
J+6 T3
J+7 T4
J+8 K
J+9 BFMAX
J+10 BFMIN
J+11 TD1
J+12 BMAX
J+13 BMIN
J+14 KM
J+15 TW
J+16 TD3
J+17 TM1
J+18 TM2 > 0
J+19 TM3
J+20 TM4
J+21 VSMAX
J+22 VSMIN
STATEs # Description
K First VSF lag-lead
K+1 Second VSF lag-lead
K+2 Thyristor
K+3 First thyristor time delay
K+4 Second thyristor time delay
K+5 SMF control
K+6 First SMF time delay
K+7 Second SMF time delay
K+8 First SMF lead-lag
K+9 Second SMF lead-lag
VARs # Description
L Other signals
L+1 VREF
L+2 Y (system base)
L+3 Voltage clamp timer
L+4 I Line (system base)
Voltage Clamp
VCL
VCL=1 1
e-sTD2
0
V1 V2 Vpu
VCL=0
|VIB|
+
I pu
XC
(SVCBASE)
Slope
+ 1 B SVCBASE Switched
VREF K e-sTD1 Shunt
(pu) S SBASE
(Bpu/Vpu)
+ BMIN
VS Other (BFMIN) (VCL)
Signals
VSMIN
23.20 CHIGAT
dc Line Model
STATEs # Description
K VDCOL, dc or ac voltage (kV or pu), VVDCOL
K+1 Measured inverter dc current (amps)
K+2 Power controller dc voltage (V), VDCP
VARs # Description
L Other signals, MW
L+1 RESTR, time unblocks or unbypasses (sec)
L+2 VRF, voltage setpoint multiplier
L+3 CRF, current setpoint multiplier
L+4 VCOMP, compensated dc voltage (V)
L+5 PACR, rectifier ac real power (pu)
L+6 QACR, rectifier ac reactive power (pu)
L+7 PACI, inverter ac real power (pu)
L+8 QACI, inverter ac reactive power (pu)
L+9 VDCI, inverter dc voltage (V)
L+10 VDCR, rectifier dc voltage (V)
L+11 DC, dc current (amps)
L+12 ALFA, alpha (degrees)
VARs # Description
L+13 GAMA, gamma (degrees)
L+14 Other VDC signals (kV)
L+15 TIMER, rectifier blocking and unblocking timer
L+16 TIMEI, inverter blocking and unblocking timer
L+17 TIBYP, inverter bypass and unbypass timer
CRAMP
0.0 CON(J+13)
Other Signals
VAR(L) (MW)
ICON(M+1)2 ICON(M+1)=2
1000
VSCHED 1.0
(amps) 1
+ s RAMPING
(1 - DELTA(I))
+
SETVAL (I) Current Control VAR(L+3)
(amps) MDC(I)=2 RLOW
VDCOL DCSET
C0
+ 106
SETVAL (I) MDC(I)=1
VDCP CON(J+14)
Power Control VVDCOL
+ V3=CON(J+19)
STATE(K)
Other Signals VDCP
VAR(L) STATE(K+2) CON(J+2) Up
1
1 1 + STVDCOL
CON(J+31) CON(J+4) Down
1 + STUP
V1=CON(J+15)
1000*VCMODE(I)
dc Setpoint Control
VAR(L+14)
Other Signals
+
+
VSCHED(I) VSET (kV)
VAR(L+2)* 1.0
1
s
CON(J+10)
VSCHED(I)
0.0 VRAMP
CON(J+12)
VSET
(1.0 + COS(MIN))
COS() = + 1.0
VACI
V CON(J+7)
I
DCSET
DCSET(1 DELTA(I))
23.21 CMDWAS
dc Line Model
STATEs # Description
K VDCOL, dc or ac voltage (kV or pu), VVDCOL
K+1 Measured inverter dc current (amps)
K+2 Power controller dc voltage (V), VDCP
VARs # Description
L Other signals, KA
L+1 RESTR, time unblocks or unbypasses (sec)
L+2 VRF, voltage setpoint multiplier
L+3 CRF, current setpoint multiplier
L+4 VCOMP, compensated dc voltage (V)
L+5 PACR, rectifier ac real power (pu)
L+6 QACR, rectifier ac reactive power (pu)
L+7 PACI, inverter ac real power (pu)
L+8 QACI, inverter ac reactive power (pu)
L+9 VDCI, inverter dc voltage (V)
L+10 VDCR, rectifier dc voltage (V)
L+11 DC, dc current (amps)
L+12 ALFA, alpha (degrees)
VARs # Description
L+13 GAMA, gamma (degrees)
L+14 Other VDC signals (kV)
L+15 TIMER, rectifier blocking and unblocking timer
L+16 TIMEI, inverter blocking and unblocking timer
L+17 TIBYP, inverter bypass and unbypass timer
RAMP
RAMP RATE = CRAMP IF VDCR > VRAMPI = CON(J+30) RATE
VDCR CRAMP CON(J+13)
RAMP RATE = 2. * CRAMP IF VDCR < VRAMPI
ICON(M+1)=0 ICON(M+1)=2
1.0
1
s RAMPING
+
VDCOL DCSET
106 C0
SETVAL (I) MDC(I)=1 +
(MW) VDCP Power CON(J+14)
Control
VVDCOL
VDCP STATE(K) (1.DELTA(I))
STATE(K+2) V3=CON(J+19) 1000
CON(J+2) Up
1 1
CON(J+31) 1 + STUP 1 + S+TVDCOL
CON(J+4) Down
Other Signals
V1=CON(J+15) VAR(L)
1000*VCMODE(I)
CON(J+11) * VSCHED(I)
If (MDC(I) = 1), RLOW =
1000 * SETVAL (I)
CON(J+11)
If (MDC(I) = 2), RLOW =
SETVAL (I)
dc Setpoint Control
VAR(L+14)
Other Signals
+
+ VSET (kV)
VSCHED(I)
VAR(L+2)* 1.0
1
s
CON(J+10)
VSCHED(I)
0.0 VRAMP
CON(J+12)
*This VAR is also used by the power controller so that the current
order is not increased when voltage is depressed.
VSET
GAMMA MIN CON(J+1)
DCSET
DCSET(1DELTA(I))
23.22 CMDWS2
Madawaska dc Line Model
STATEs # Description
K Power controller dc voltage (V),VDCP
K+1 Measured inverter dc current (amps)
VARs # Description
L Other signals, KA
L+1 RESTR, time unblocks or unbypasses (sec)
L+2 VRF, voltage setpoint multiplier
L+3 DCLVDC, dc voltage dependent current limit
L+4 VCOMP, compensated dc voltage (V)
L+5 PACR, rectifier ac real power (pu)
L+6 QACR, rectifier ac reactive power (pu)
L+7 PACI, inverter ac real power (pu)
L+8 QACI, inverter ac reactive power (pu)
L+9 VDCI, inverter dc voltage (V)
L+10 VDCR, rectifier dc voltage (V)(V)
L+11 DC, dc current (amps)
L+12 ALFA, alpha (degrees)
L+13 GAMA, gamma (degrees)
L+14 Other VDC signals (kV)
L+15 TIMER, rectifier blocking and unblocking timer
VARs # Description
L+16 TIMEI, inverter blocking and unblocking timer
L+17 TIBYP, inverter bypass and unbypass timer
L+18 TDELAY, reference time for current limit delay
TSAMPL, reference time for current limit
L+19
sampling
DCLVAC, ac voltage dependent current limit
L+20
(amps)
L+21 VACIN, voltage that determines current limit
L+22 DCSET
ICONs # Description
Inverter status:
0 Normal
M
1 Blocked or bypassed
2 Ramping
Rectifier status:
0 Normal
M+1
1 Blocked
2 User ramp
0 current limit uses inverter VDC
M+2
> 0 current limit uses VAR (ICON(M+2))
1 VDCL on upper hysteresis path
M+3
-1 VDCL on lower hysteresis path
Note: ICONs M and M+1 are set by the program and should not be modified by the user. If the user
wishes to block the converter, MDC(I) should be set to zero. The user can force a bypass by putting
appropriate values in CON(J+27) and CON(J+28).
1
s DCLVDC
VAR(L+3)
CRAMP ICON(M+1)=2 DCSMIN
CON(J+13) CON(J+11)
VAR(ICON(M+2))
ICON(M+2)0 VH1 VH2
CON(J+19) CON(J+20)
CH
CON(J+16)
VACIN DCLVAC
VAR(L+21) VAR(L+20)
VDCI/1000 CL VL1 VL2
ICON(M+2) = 0 CON(J+15) CON(J+17) CON(J+18)
SETVAL(I)
DCLVDC DCLVAC
VAR(L+3) VAR(L+20)
1
1 + sTIODC DCSET
C0
106 CON(J+3) CON(J+14)
Power
SETVAL(I) VDCP Control
(MW) MDC(I)=1 1000
VDCP
CON(J+31)
1
1 + sTVP Other Signals
VAR(L)
1000*VCMODE(I)
SETVAL(I)<0 SETVAL(I)>0
VDCI/VAR(L+2) VDCR/VAR(L+2)
VAR(L+14)
Other Signals
+
+
VSCHED(I) VSET (kV)
VAR(L+2)* 1.0
1
s
CON(J+10)
VSCHED(I)
ICON(M)2 ICON(M)=2
0.0 VRAMP
CON(J+12)
*This VAR is also used by the power controller so that the current order is
not increased when voltage is depressed. VAR(L+2) is started at the
lower limit when unblocking or unbypassing.
VSET
GAMMA MIN CON(J+1)
DCSET
DCSET(1DELTA(I))
23.23 CMFORD
dc Line Model
STATEs # Description
K VDCOL, dc or ac voltage (kV or pu), VVDCOL
K+1 Measured inverter dc current (amps)
K+2 Power controller dc voltage (V), VDCP
VARs # Description
L Other signals, MW
L+1 RESTR, time unblocks or unbypasses (sec)
L+2 VRF, voltage setpoint multiplier
L+3 CRF, current setpoint multiplier
L+4 VCOMP, compensated dc voltage (V)
L+5 PACR, rectifier ac real power (pu)
L+6 QACR, rectifier ac reactive power (pu)
L+7 PACI, inverter ac real power (pu)
L+8 QACI, inverter ac reactive power (pu)
L+9 VDCI, inverter dc voltage (V)
L+10 VDCR, rectifier dc voltage (V)
VARs # Description
L+11 DC, dc current (amps)
L+12 ALFA, alpha (degrees)
L+13 GAMA, gamma (degrees)
L+14 Other VDC signals (kV)
L+15 TIMER, rectifier blocking and unblocking timer
L+16 TIMEI, inverter blocking and unblocking timer
L+17 TIBYP, inverter bypass and unbypass timer
ICONs # Description
Voltage ramp flag:
0 Normal
M 1 Blocked
2 Ramping
-1 Bypass
Current ramp flag:
0 Normal
M+1 1 Blocked
2 Ramping
-1 Bypassed
0 current limit uses inverter VDC
M+2
> 0 current limit uses VAR (ICON(M+2))
1000.
VSCHED
1.0
1
+ s RAMPING
(1DELTA(I))
+
RLOW VAR(L+3)
SETVAL(I) Current Control
MDC(I)=2
VDCOL
DCSET
C0
+ 106 CON(J+14)
MDC(I)=1
SETVAL(I) VDCP Power VVDCOL
+ Control STATE(K)
V3=CON(J+19)
VDCP
Other Signals STATE(K+2) CON(J+2) Up
VAR(L) 1
1000 1 + STVDCOL
CON(J+31) CON(J+4) Down
1 + STUP
V1 = CON(J+15)
1000*VCMODE(I) +
VAR(L+14)
Other Signal
+
ICON(M+2)=0 ICON(M+2)0
VSCHED(I)
VDCI VAR(ICON(M+2))
CON(J+11) * VSCHED(I)
If (MDC(I) = 1), RLOW =
1000*SETVAL (I)
CON(J+11)
If (MDC(I) = 2), RLOW =
SETVAL (I)
dc Setpoint Control
VAR(L+14)
Other Signals
+
+
VSCHED(I) VSET (kV)
VAR(L+2) 1.0
1
s
CON(J+10)
VSCHED(I)
0.0 VRAMP
CON(J+12)
VSET
GAMMA MIN = CON(J+1)
DCSET
DCSET(1DELTA(I))
23.24 CRANI
Series Reactor FACTS Model
STATEs # Description
K Transducer filter
K+1 Washout
K+2 Lead/lag
VARs # Description
L Input signal1
L+1 Initial output
L+2 Desired reactance
1 Statement must be added in CONEC and CONET to place
signal into VAR(L).
Xmax
1 sTW 1 + sT2 +
VAR(L) K VAR(L+2)
1 + sT1 1 + sTW 1 + sT3 X
+
Xmin
VAR(L+1)
23.25 CSSCS1
SVG for Switched Shunt
J+2 T2 (sec)
J+3 T3 (>0) (sec)
J+4 T4 (sec)
J+5 T5 (sec)
J+6 VMAX Mvars
J+7 VMIN Mvars
J+8 VOV (override voltage) (pu)
STATEs # Description
K First regulator
K+1 Second regulator
K+2 Thyristor
VARs # Description
L Other signals
L+1 VREF
L+2 Y (system base)
L+3 BREF
ICONs # Description
M IBUS, bus where SVG is connected
M+1 IB, remotely regulated bus
Capacitors
VREF BREF VMAX (Mvar)
+
VERR K (1 + sT1) (1 + sT2) 1
|VIB| 1 + sT5
+ (1 + sT3) (1 + sT4)
Other VMIN Reactors
Signals (Mvar)
23.26 FRQDCA/FRQTPA
Under/Over Frequency Generator Bus Disconnection Relay
Under/Over Frequency Generator Trip Relay
FRQDCA
This model is located at system bus #_______ IBUS,
machine #_______ IM,
This model uses CONs starting with #_______ J,
and VARs starting with #_______ K,
and ICONs starting with #_______ M.
FRQTPA
CONs # Value Description
J FL, Lower frequency threshold (Hz)
J+1 FU, Upper frequency threshold (Hz)
J+2 TP, Relay pickup time (sec)
J+3 TB, Breaker time (sec)
VAR # Description
K Timer memory
ICONs # Description
M Bus number where frequency is monitored
Bus number of generator bus where relay is
M+1
located
M+2 Generator ID
M+3 Delay flag
M+4 Timeout flag
M+5 Timer status
Note: ICONs (M+3) through (M+5) are control flags that are not to be changed by the user.
23.27 VTGDCA/VTGTPA
Under/Over Voltage Generator Bus Disconnection Relay
Under/Over Voltage Generator Trip Relay
VGTDCA
This model is located at system bus #_______ IBUS,
machine #_______ IM,
This model uses CONs starting with #_______ J,
and VARs starting with #_______ K,
and ICONs starting with #_______ M.
VTGTPA
CONs # Value Description
J VL, Lower voltage threshold (pu)
J+1 VU, Upper voltage threshold (pu)
J+2 TP, Relay pickup time (sec)
J+3 TB, Breaker time (sec)
VAR # Description
K Timer memory
ICONs # Description
M Bus number where voltage is monitored
Bus number of generator bus where relay is
M+1
located
M+2 Generator ID
M+3 Delay flag
M+4 Timeout flag
M+5 Timer status
Note: ICONs (M+3) through (M+5) are control flags that are not to be changed by the user.
23.28 FLOW1
Branch Flow Model
VARs # Description
N MW
M Mvar
L MVA
Note: Flows include the line shunt component at the from bus end.
Model call must be manually inserted into subroutine CONET after the IFLAG test and data must
be entered, or branch flow must be selected in activity CHAN or CHSB.
23.29 FLOW3
Three-Winding Transformer Flow Model
VARs # Description
N MW
M Mvar
L MVA
Note: Flows include the magnetizing admittance component at the from bus end if it is the bus to
which winding one is connected.
Model call must be manually inserted into subroutine CONET after the IFLAG test and data must
be entered, or branch flow must be selected in activity CHAN or CHSB.
23.30 GENTMC
Generator Terminal Current Model
VARs # Description
L Current magnitude on MBASE
L+1 Current angle (radians)
Model call must be manually inserted into subroutine CONET after the IFLAG test and data must
be entered, or machine terminal current must be selected in activity CHAN or CHSB.
23.31 GENTMZ
Generator Apparent Impedance Model
VARs # Description
L Apparent resistance on MBASE
L+1 Apparent reactance on MBASE
The apparent impedance is expressed from the terminals looking out into the system.
Model call must be manually inserted into subroutine CONET after the IFLAG test and data must
be entered, or machine apparent impedance must be selected in activity CHAN or CHSB.
VARs # Description
L Mechanical power, PM
L+1 Electrical power, PE
L+2 Accelerating power, PM-PE
L+3 Load power, PL
L+4 PE-PL
An explicit model call may be manually inserted into subroutine CONEC and data may be manually
entered. The model call will be placed implicitly by activity CHSB,SU, or by employing the Sub-
system power totals selection of the Select Channels by Subsystem dialog.
23.33 RELAY2
Relay Checking Model
VARs # Description
N Apparent resistance
M Apparent reactance
Model call must be manually inserted into subroutine CONET after the IFLAG test and data must
be entered, or RELAY2 must be selected in activity CHAN or CHSB.
23.34 RELAY3
Three-Winding Transformer Relay Checking Model
VARs # Description
N Apparent resistance
M Apparent reactance
Model call must be manually inserted into subroutine CONET after the IFLAG test and data must
be entered, or RELAY3 must be selected in activity CHAN or CHSB.
23.35 VOLMAG
Voltage Monitoring Model
VARs1 # Description
J Voltage magnitude
K Phase angle
1 J or K may be zero to bypass storing of that quantity.
Model call must be manually inserted into subroutine CONET after the IFLAG test and data must
be entered, or bus voltage (or voltage and angle) must be selected in activity CHAN or CHSB.
23.36 BSDSCN
Bus Isolation Model
Model call must be manually inserted into subroutine CONET and data must be entered.
23.37 FLOW
Branch Flow Model
VARs # Description
N MW
M Mvar
L MVA
Model call must be manually inserted into subroutine CONET after the IFLAG test and data must
be entered.
23.38 FLOW2
Branch Flow Model
VARs # Description
N MW
M Mvar
L MVA
Model call must be manually inserted into subroutine CONET after the IFLAG test and data must
be entered.
Model call must be manually entered into subroutine CONEC and called in mode 3.
23.40 LINESW
Branch Switching Model
Model call must be manually entered into subroutine CONET and data must be entered.
23.41 LINRCL
Branch Reclosing Model
Model call must be manually entered into subroutine CONET and data must be entered.
23.42 LINTRP
Branch Tripping Model
Model call must be manually entered into subroutine CONET and data must be entered.
23.43 SAT1
Saturable Reactor or Transformer Saturation
STATEs # Description
K VON, turn on volts (pu)
K+1 Local storage of reactor current
Procedure for Initializing: Set up initial condition power flow using a normal reactor with rating
equal to CON(J+2). Decommit this, but do not resolve, before factorizing the Y matrix for use in the
simulation. The first call of SAT1 and STRT will then initialize VON to the value required to match
the saturated operating point VAR consumption to the VARs consumed by the conventional reactor
used in power flow.
Model must be manually entered into subroutine CONET and data must be entered.
R
1.0
1
Voltage (pu)
VON
1.0
CRO
Reactor Current (pu)
(Reactor Base)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-21
American Superconductor DSMES Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
Basler DECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37
Basler Static Voltage Regulator Feeding dc or ac Rotating Exciter . . . . . . . . . . . . . . . . . . . . .6-67
Branch Flow Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-79
Branch Flow Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-88
Branch Flow Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-89
Branch Reclosing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-92
Branch Switching Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-91
Branch Tripping Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-93
Brown Boveri Static Exciter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9
Bus Fed or Solid Fed Static Exciter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-130
Bus Isolation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-87
Bus or Solid Fed SCR Bridge Excitation System Model Type NEBB (NVE) . . . . . . . . . . . . . . .6-73
Bus or Solid Fed SCR Bridge Excitation System Model Type NI (NVE) . . . . . . . . . . . . . . . . . .6-75
Bus Voltage Angle Sensitive Auxiliary Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-12
Chateauguay Auxiliary Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2
Combined Cycle on Single Shaft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-84
Comerford Auxiliary Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5
Complex Load Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-18
Composite Load Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-21
Constant Internal Voltage Generator Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-39
Cross Compound Turbine-Governor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
Czech Hydro and Steam Governor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-75
Czech Proportion/Integral Exciter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11
dc Line Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-13
dc Line Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-45
dc Line Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-53
dc Line Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-58
dc Line Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-68
Direct Connected (Type 1) Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-3
Double Circle or Lens Out-of-Step Tripping or Blocking Relay . . . . . . . . . . . . . . . . . . . . . . . . .11-2
Doubly-Fed Induction Generator (Type 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-6
Doubly-Fed Induction Generator (Type 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-8
Eel River and Madawaska dc Line Runback Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-11
Eel River dc Line and Auxiliaries Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-27
Eel River dc Line Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-28
Eel River Runback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-14
Electrical Control for Type 3 Wind Generator (for WT3G1 and WT3G2) . . . . . . . . . . . . . . . . .18-6