ME445M:EmbeddedandRealTimeSystems

LectureSet#01

EE445M: EMBEDDED AND REAL TIME SYSTEMS LectureSet#01

February15,2017

CourseofferedbytheDepartmentofElectricalEngineeringat
UniversityofTexasatAustin

Disclaimer:ThecontentsofthisdocumentarescribenotesforTheUniversityofTexasatAustin
EE445MSpring2017,EmbeddedandrealTimeSystems.

RTOS
Real Time Operating System

Note Taker: Hilgad Montelo (hilgad.montelo@utexas.edu)

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 ME445M:EmbeddedandRealTimeSystems
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RTOSReview

RTOS
RealTimeOperatingSystemisasoftwarethatmanagescomputersystemresourceslikememory,I/O,
dataandprocessors,satisfyingalltimeconstraints.

HAL
HardwareAbstractionLayer.Asoftwarethatsimplifiesportingapplicationcodefromonemicrocontroller
toanother.

ResponseTimeorlatency
Itisthedelayfromrequesttothebeginningoftheserviceofthatrequest.

Bandwidth
Itisthenumberofinformationthatcanbetransferredorprocessed(bytes/sec).

EmbeddedSystem
Itconsistofasmartdevicewithaprocessorthathasaspecialanddedicatedpurpose.

ForEmbeddedSystems,RealTimemeansthattheembeddedsystemmustrespondtocriticalevents
withastrictlydefinedtime(deadline).

Thereare5(five)typesofsoftwarefunctionsthattheprocessorcanperforminanembeddedsystem:

1. Mathematicalordataprocessingoperations.
2. Handlingandmanagingtime.
3. RealTiminput/outputformeasurementandcontrol
4. DSP(Ex.:Audio,video,radaretc)
5. CommunicationandNetwork.

EmbeddedSystemsareclassifiedas:

Transformative:Collectdatafrominputs,makesdecisionsandaffectsitsenvironmentbydriving
actuators(Ex.:Robots).
Reactive:Collectsdatafrominputsincontinuousfashionandproducesoutputsincontinuosfashion
(Ex.:DSP).

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CommonEmbeddedSystemConstraints:

SmallSize,
Lowweight,
Lowpower,
HarshEnvironments,
SafetyCriticalSystems
SensitiveCost.

Computer
ItcombinesaCPU,RandomAccessmemory(RAM),ReadOnlyMemory(ROM),andI/Oports.

Software
Itisanorderedsequenceofveryspecificinstructionsthatarestoredinmemory,definingexactlywhatand
whencertaintasksaretobeperformed.

HarvardArchitecture
Ithasaseparateddataandinstructionbuses.

Interrupt
Itisahardwaretriggeredsoftwarefunction,whichisextremelyimportantforrealtimeembedded
systems.

LatencyofaninterruptService
Itisthetimebetweenhardwaretriggeredandsoftwareresponse.

ARMCortexMMemoryAccess(bitbanding)
Bitbandingallowtoread/writememoryaccess.

Ex.01:Whataddressdoyouusetoaccessbit3ofthebyte0x2000.1010?

Address=0x2200.0000+0x20xn+4xb

b=3

n=0x1010

So,

Address=0x2200.0000+0x20x0x1010+4x3=2202.020C

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Ex.02:Whataddressdoyouusetoaccessbit7ofthebyte0x4000.0030?

Address=0x4200.0000+0x20xn+4xb

b=7

n=0x0030

So,

Address=0x4200.0000+0x20x0x0030+4x7=4200.061C

ARMCortexMRegisters
R0R12 GeneralPurposeRegisters.
R13 StackPointer(SP)
Note:thereare2(two)stackpointers:
ManStackPointer(MSP):UsedfortheOperatingSystem
ProcessStackpointer(PSP):UsedfortheUserSoftware.
R14 LinkRegister(LR).Itstoresthe returnlocationforthefunctions.
R15 ProgramCounter(PC).Itpointstothenextinstructiontobefetchedinmemory.

TheARMArchitectureProcedureCallStandard(AAPCS)partoftheARMApplicationBinaryInterface(ABI):

UsesR0,R1,R2,R3,andR12topassinputparametersintoaCfunctionoranassemblysubroutine.
TheplacetoreturnparameterisR0.
PreserveregistersR4R11,whichimpliessaveR4R11,usethem,andrestoreR4r11beforereturning.
Keepthestackalignedto64bits,bypushingandpoppinganevennumberofregisters(multipleof8
bytes).

SpecialRegisters:

PSR(ProgramStatusRegister),
ControlRegister
PRIMASK*,
FAULTMASK*,
BASEPRI* *ExceptionmaskRegisters

ARMProgramStatusRegister(PSR)
Itcontainstheflagstorepresenttheprogramstatus.
N Z C V Q IC I/IT T RESERVED ICI/IT ISRNumber
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

N,Z,C,V,andQrepresentsstatusofALU(ArithmeticalandLogicalUnit)operations.

N Setiftheresultofalogicalorarithmetical operationwasnegative

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Z Iftheresultwaszero
C Ifacarryhappened
V Ifanoverflowhappened
Q Ifasaturationhasoccurred
T Armisexecutingthumbinstructions
ICI/T Usedbyinterruptions andIFTHENinstructions
bit0ofPRIMASK ItistheinterruptmaskbitorIbit.Ifis1,mostinterruptandexceptionsarenot
allowed;ifis0,interruptionsareallowed.

STACK
ALastInFirstOut(LIFO)temporarystorage.

ProperuseofStackrequiresthefollowingrules:

1. Functionsshouldhaveanequalnumberofpushesandpops.
2. Stackaccessshouldnotbeperformedoutsidetheallocatedarea.
3. Stackreadandwriteshouldnotbeperformedwithinthefreearea.
4. StackpushdecrementsSPthenstoredata
5. StackpopshouldfirstreadsdatathenincrementSP.

Abusfaultwillbegeneratedwhenthesoftwaretriestoread/writefromanaddressthatdoesnotexists.
Ifavalidaddressbeloworabovethestack,thenfurtherstackoperationwillcorruptthedata.

Whenmultipleregistersarepushedandpopped,thedataexistsinmemorywiththelowestnumbered
registerusingthelowestmemoryaddress(stackstop).Ex.:

IfR1,R4,R5,R6containsthevalues1,4,5,6respectively,thenthevalueofthelowestnumberedregister
R1isplacedintheloweststackaddress.

IffourentriesarepoppedlikePOP{R0,R2,R7,R9},thevaluetheloweststackaddressisloadedinthe
lowestnumberedregister.

ARMOperatingModes
ArmCortexMprocessorhas2privilegedmodes:privilegedandunprivileged.

Bit0onRegisterControlisthethreadPrivilegedMode(TPL).

IfTPLis1processorisinprivilegedmode.IfTPLis0runsinunprivilegedmode.

Bit1ontheRegisterControlistheActiveStackPointerSelection(ASPSEL).

IfASPSELis1thenprocessorusesPSP.

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IfASPSELis0thenprocessorusesMSP.

ARMDefines
Foreground(mainprogram)asthreadMode.
Background(ISR)ashandlerMode.

Switchingbetweenthreadandhandlermodeisautomatic.

Theprocessorbeginsinthreadmode,i.e.ISR_NUMBER=0.

Wheneveritisservinganinterrupt,itswitchestohandlermode;i.e.ISR_NUMBER=Interruptbeing
processed.

AllISRrunsusingtheMSPstackpointer.

Note:Thecontextissavedwhicheverstackpointerisactive,butduringtheexecutionofISR,theMSPis
used.

RESET
Afterareset.

1. Processoristhreadmode
2. Runinprivilegedmode
3. UsesMSPstackpointer
4. Loadthe32bitvaluelocatedinposition0ofROMintotheSP
5. Loadthe32bitvaluelocatedinposition4ofROMintothePC
6. Thumbbit(TbitinControlregister)isalways1inCortexM.
7. LRissetto0xFFFFFFFF.

I/O
Pin Specificwireonthemicrocontrollerunit(MCU) thatcanbeusedforspecificinput/output
operations.
Port Acollectionofpinsgroupedbycommonfunctionalities
Interface CollectionofI/Oports,externalelectronics,physicaldevices,andsoftwares.

I/OInterfaces
I/Ointerfacescanbeclassifiedin4(four)categories:

1. Parallel/Digital:Binarydataavailablesimultaneouslyonagroupoflines.
2. Serial:Binarydataisavailable1bitofthetime.
3. Analog:Dataareencodedaselectrical,voltageorpower.
4. Time:dataareencodedasaperiod,frequency,pulsewidthorphaseshift.

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