The Microprocessor and its Architecture

Microprocessor (MP) is an integrated circuit that contains the entire central pr

ocessing unit (CPU) of a computer on a single chip. In 1978, Intel introduced a
16-bit microprocessor, the 8086.

Fig: 8086 External Bus

Bus Operation
Bus is group of conducting lines which carry binary information.
Internal Bus: connects two minor components within a major component (or IC), su
ch as the connection between the control unit and internal registers of the MPU.
External Bus: connects two major components, such as MPU and an interface (Memor
y or input/output). Although some systems include more than one external bus, 80
86 and 8088 processors contain only one external bus called system-bus.
Typical system-bus includes: Address-bus (carries physical address of memory or
input/output locations), Data-bus (carries data to be read or written into MPU r
egisters) and Control-bus(carries information to control the read or write opera
tion).
Address Bus
Address bus is used by the P to select a memory location, from where data can be
read or written.
The number of address lines varies from one processor to the other processor and
are unidirectional.
The number of memory locations that the P can address is determined by number of
address lines. A P with N address lines can address upto 2N locations. i.e. if a P
contains 16 address lines, it can address 216 memory locations.
Data Bus
The data bus is a bidirectional bus which carries data between the P and other un
its of microprocessor based system(ie. Memory or I/O devices)
The number of data lines varies from processor to processor.
Many devices in a system will have their outputs connected to the data bus, but
only one device at a time will have its outputs enabled
Control bus
The P issues proper timing and bus control signals to memory and I/O device. It i
s unidirectional.
8086 Architecture
The functional block diagram of 8086 is divided into
Bus Interface Unit (BIU)
Execution Unit (EU)
While EU decodes and executes instructions, BIU fetches instructions from memory
and stores them in the QUEUE.
BIU and EU operate in parallel independent of each other.
This type of overlapped operation of the functional units of a MP is called Pipe
lining.

Bus Interface Unit: The blocks present in this BIU are,

Adder
Segment Registers
Instruction Pointer(IP)
The Queue
Adder ( ? ): It is the address conversion mechanism used to generate 20bit Physi
cal address.
16-bit code segment(CS) register contents are loaded into a 20-bit Adder ( ? ) i
n BIU and shifted to left by 4-bits, inserting zeros in four LSBs.
 Thus, CS contents are changed from 16 to 20 bits in BIU.
The 16-bit offset in IP is added to the shifted CS to generate 20-bit physical a
ddress.
Therefore, Physical address = CSx16+IP (or) CSx10H+IP
Example: Let CS=5000H and IP=1234H
20bit physical address = 5000Hx16 + 1234H
= 50000H+1234H
= 51234H
Segment Registers: The BIU contains four 16-bit segment registers. They a
re:
1. Code Segment (CS) Register
2. Data Segment (DS) Register
2. Stack Segment (SS) Register
3. Extra Segment (ES) Register
Each segment has a maximum capacity of 64k bytes.
Code segment holds the base address of memory where instructions of a program ar
e stored.
Data segment holds the base address of memory, where program data, variables and
constants are stored.
Stack segment holds the base address of stack, where data related to stack opera
tions are stored.
Extra segment stores the base address of memory, where data corresponding to str
ing operations are stored.
Each segment is assigned a base address that identifies its lowest addressed byt
e storage location.
Instruction Pointer (IP): Holds the offset address that should be added to the s
hifted CS to generate 20-bit physical address.
Instruction object code queue
8086 processor maintains 6-byte object code queue.
Fetched instructions are arranged in a queue.
Operates in FIFO (first in first out ).
Output of this unit is sent to execution unit.