`

Analog Layout Design for

Integrated Circuits in
CMOS

Page 1
 TABLE OF CONTENTS

TABLE OF CONTENTS.......................................................................................................................................3

TABLE OF FIGURES...........................................................................................................................................5

Chapter 1: Introduction to Analog Design.........................................................................................................6

Introduction............................................................................................................................................................6

Objectives...............................................................................................................................................................7

Target audience......................................................................................................................................................7

How to use this manual.........................................................................................................................................7

Chapter 2: Definitions..........................................................................................................................................8

Basic Electrical Definitions...................................................................................................................................8

Current:................................................................................................................................................................8
Voltage:................................................................................................................................................................8
Impedance:...........................................................................................................................................................9
Resistance:...........................................................................................................................................................9
Capacitance:.......................................................................................................................................................10
Inductance:.........................................................................................................................................................10

Other Definitions..................................................................................................................................................11
Digital:...............................................................................................................................................................11
Analog:...............................................................................................................................................................11
Parasitic:.............................................................................................................................................................11
Noise:.................................................................................................................................................................11
Fully Covered Contact (Via):.............................................................................................................................12
Fully Contacted Strap:.......................................................................................................................................12
Diffusion Matching:...........................................................................................................................................13
Unitized Devices:...............................................................................................................................................13
Isolated Substrates:............................................................................................................................................13
Legs and Mults:.................................................................................................................................................13

Chapter 3: Analog Layout Guidelines..............................................................................................................15

Purpose:................................................................................................................................................................15

General Analog Layout Guidelines:...................................................................................................................15

Ideal Devices.........................................................................................................................................................15

Ideal Interconnect................................................................................................................................................17

Stability and Noise...............................................................................................................................................19

Page 2
Resistors................................................................................................................................................................20

Capacitors.............................................................................................................................................................21

Guardrings...........................................................................................................................................................22

Shielding...............................................................................................................................................................23

Chapter 4: Device Matching..............................................................................................................................24

Purpose:................................................................................................................................................................24

Device Matching and Balancing:........................................................................................................................24

Mirroring..............................................................................................................................................................24

Common Centroid:..............................................................................................................................................25

Dummification:....................................................................................................................................................31

Legs and Mults:....................................................................................................................................................34

Legs....................................................................................................................................................................34
Mults..................................................................................................................................................................35

Chapter 5: Signal Matching...............................................................................................................................36

Purpose:................................................................................................................................................................36

Signal Matching and Balancing:........................................................................................................................36

Signal matching by exact geometric copying....................................................................................................36
Signal matching by adding shielding.................................................................................................................38
Signal matching by increased spacing...............................................................................................................38
Mirroring:..........................................................................................................................................................39

Page 3
 TABLE OF FIGURES
Figure 2.1: Current 8
Figure 2.2: Voltage 9
Figure 2.3: Resistor schematic symbol. 10
Figure 2.4: Capacitor schematic symbol. 10
Figure 2.5: Inductor schematic symbol. 11
Figure 2.6: A representation of an analog waveform. 11
Figure 2.7: Fully Covered Contact (Via). 12
Figure 2.8: Fully Contacted Strap. 12
Figure 2.9: Diffusion Matching. 13
Figure 3.1: Minimum Design Rule after Fully Contacted Strap. 15
Figure 3.2: No Diffusion Notches. 16
Figure 3.2: No Dogbones 16
Figure 3.3: 2x Poly Endcap Extensions. 16
Figure 3.4: Two Contact/Via Minimum Rule per connection. 17
Figure 3.5: No Routing Over the Top of Devices. 17
Figure 3.6: Example of Wire Width Oversizing. 18
Figure 3.7: Use as many contacts/vias as will fit. 18
Figure 3.8: Example of unique n-well connection. 19
Figure 3.9: No Dogbone Resistors. 20
Figure 3.10: No Serpentine Resistors. 20
Figure 3.11: Example of a Unitized CMOS Capacitor. 21
Figure 3.12: Example GuardRings (corners). 22
Figure 3.13: Example Cross-Sections of Various Shields. 23
Figure 4.1: Mirroring versus Stepping. 25
Figure 4.2: A Typical Differential Circuit Schematic. 26
Figure 4.3: Common Centroid Device Placement. 27
Figure 4.4: Interdigitation Device Placement. 28
Figure 4.5: Interdigitation Device Placement Variation. 29
Figure 4.6: Interdigitation Device Placement Variation. 29
Figure 4.7: Interdigitation Device Placement Variation. 30
Figure 4.8: Combining Common Centroid and Interdigitation. 31
Figure 4.9: Interdigitation Device Placement without Dummy Device. 32
Figure 4.10: Interdigitation with Additional Dummy Devices. 32
Figure 4.11: Example of Unitized Resistors with Dummy Devices. 33
Figure 5.1: Example of geometric copying. 37
Figure 5.2: Signal Matching by adding shields. 38
Figure 5.3: Signal matching by increased spacing. 39
Figure 5.4: Unmatched Metal1 when mirrored. 40
Figure 5.5: Example of a mirrored matched pair. 41

Page 4
 Chapter 1: Introduction to Analog Design
Introduction

The purpose of this document is to present analog layout design concepts to Engineers and Mask Designers. It
will introduce fundamental and essential methodologies. It will describe basic concepts and techniques that can
be used to successfully complete the physical design of CMOS analog circuits.

Historically, CMOS processes have been specifically designed for the manufacture of high-speed digital
circuits such as microprocessors and memory chips. Many of the parameters associated with these processes
are tuned specifically for these digital applications. The fact that a digital switch is inherently immune to
certain types of noise prompted the Process Engineers to settle for materials and devices that are considered less
than ideal for the analog applications. Therefore the analog circuit Engineer and Mask Designer must have a
basic understanding of these principles in order to minimize the impact of certain undesirable parasitic effects
on their circuits.

Analog layout is different from digital in the following ways:

The sensitivity of individual signals to noise is greatly increased in analog circuits.

Appropriate placement of devices can be critical to meeting electrical specifications.

Protection and isolation from other more noisy circuits can be important.

Device balancing and matching is required in certain kinds of circuits.

Signal balancing and matching is necessary for certain kinds of circuits.

Because of the complexity and attention to detail required for analog circuits, you will need to plan an
extra amount of time to complete an analog layout compared to a digital layout with equivalent part
counts.

Analog layout can require up to 8 times more area than a digital layout with equivalent parts.

In short, an analog layout is very meticulous and requires a great attention to detail.

Page 5
Objectives

After completing this guide you will be able to:

Minimize noise by reducing the effects of parasitic.

Demonstrate a working knowledge of general layout guidelines as they apply to analog integrated
circuits.

Build all types of analog devices including transistors, resistors, capacitors, diodes, etc...

Describe analog design techniques for:

guard rings
signal shielding
device matching
signal balancing
dummification (ghosting)
ESD structures

Target audience

This manual is designed for Engineers and Mask Designers with at least one year of experience.

This manual will give Mask Designers the basic tools to complete analog layout.

This manual will be useful for the Engineer who desires to understand analog layout techniques and who desires
to create schematics that are tuned to analog design methodologies. Circuit Designers that are actively
designing analog circuits can use this information when conducting Design Reviews and Plot Reviews.

How to use this manual

There is a review exercise and a layout exercise at the end of this manual. These exercises should be done
individually after attending the class or studying this manual. They should be done in an environment, and
using drawing tools, that the user is familiar with. Therefore, specific tool data and specific process data were
intentionally omitted from this manual.

Page 6
 Chapter 2: Definitions

One of the primary considerations for successful analog layout is controlling parasitics.

In microelectronics, parasitics are the intrinsic physical characteristics of the different layers and materials
that are used to manufacture an Integrated Circuit (IC).
Resistance and capacitance are the primary electrical components of these materials that we are required to
understand in order to predict circuit performance. To perform successful circuit layout, these parasitics must
be understood and controlled. This is important for digital circuits, but it is extremely critical for the success of
analog circuits.

This chapter will establish definitions for the terminology used in this manual.

Basic Electrical Definitions

Current:
Current is simply the measure of how many electrons flow through a conductor in a given period of time.
Literally, one ampere (I) of current is 6.242 x 1018 electrons flowing through a wire in one second of time (t).

And a coulomb (Q) is defined as the charge associated with 6.242 x 1018 electrons. Therefore:

I(amps) = Q(coulombs) / t(seconds)

Figure 2.1: Current

Also, the amount of current in an electronic circuit can also be calculated by the formula: voltage (E) (in volts)
divided by resistance (R) (in ohms). For example: in order for one amp of current to flow, it takes one volt of
electrical pressure to overcome one ohm of resistance.

I(amps) = E(volts) / R(ohms)

Voltage:
Voltage (E) is the electrical pressure that is needed to cause current to flow. As you know, unlike charges
attract and like charges repel. In a circuit the force of this attraction (or repulsion) is what causes the electrons
to move. Voltage is the potential energy that exists between two points as a result of this attraction or repulsion.
The electrical pressure can exist in a circuit without current actually flowing, but current cannot flow without
the electrical pressure.
Page 7
Voltage is also defined in electronic circuits with respect to current and resistance. One volt of electrical
pressure is required to push one amp of current through one ohm of resistance.

E(volts) = I(amps) x R(ohms)

Figure 2.2: Voltage

Furthermore, the physical measure of work in and electrical circuit is the joule.
If the work required to move a charge of 1 coulomb (Q) from one point to another is 1 joule (W), we say there
exists a potential difference of 1 volt between these two points.1

E(volts) = W(joules) / Q(coulombs)

Impedance:
Impedance (Z) is the measure of how much a circuit will impede or hinder the flow of current.
It is the total combination of resistance, capacitance and inductance in an Alternating Current (AC) circuit, and
thus it can have a corresponding phase angle* associated with it.
A pure resistance has a 0 degree phase angle (Z = R = (R + j0) ).
A capacitance has a minus 90 degree phase angle (Z = XC = (0 - jXC) ).
An inductance has a plus 90 degree phase angle (Z = XL = (0 + jXL) ).

The total impedance of any circuit is:

Z (of any circuit) = R + XC + XL

Where:
XL = 2fL
XC = 1 / (2fC)
f = frequency
L = inductance (henry)
C = capacitance (farad)

* Note: the phase angle is the phase relationship between the voltage and current waveforms in an AC
circuit.

Resistance:

1
Boylestad, Robert L., Introductory Circuit Analysis, 2nd Edition, 1972, p. 21
Page 8
Resistance (R) is the ability of a circuit to resist or impede the flow of electrons. This opposition is due to the
collision of electrons into other electrons as well as other atoms. These collisions result in the electrical energy
being converted to heat energy. Resistance is similar to friction in a mechanical system. The unit of measure is
the ohm ().
A pure resistance has no phase angle associated with it and would react the same in a Direct Current (DC)
circuit as it would in an Alternating Current (AC) circuit. Resistance is one specific form of Impedance (see
above).

A resistor is a device designed to impede the flow of electrons and usually is defined in terms of its value
(ohms) and how much heat it can dissipate (watts).

Figure 2.3: Resistor schematic symbol.

In MICROELECTRONICS a resistor can be made of almost any conductive layer.

Normally conductors have resistance specified as ohms per square.
Typically an engineer will specify a resistor in a schematic as a certain material (resistor type) a specific length
and width.

Capacitance:
Capacitance (C) is the measure of a circuits ability to store a charge.
Think of it as a devices storage capacity.
A capacitor has the physical properties such that it resists instantaneous changes in voltage, because a storage
device takes measurable amounts of time to fill or empty.
A capacitor that can store one coulomb (Q) of charge with one volt of electrical pressure (E) across it is said to
be one farad.

C (farads) = Q (coulombs) / E (volts)

A capacitor is made when two conductors of a certain size (area) are in proximity to each other separated by a
dielectric (insulator).

Figure 2.4: Capacitor schematic symbol.

In MICROELECTRONICS a capacitor is usually specified as a transistor of certain size, the gate being one
terminal and the drain and source are the other terminal.
The reason a transistor is used as a capacitor is because the gate insulator (dielectric) layer is the thinnest and
most tightly controlled dielectric produced on a microchip.
Caps can also be made from any adjacent metal layers of a specified area. Some processes have MIM caps
which are usually the top two metal layers with a special process that fine tunes the dielectric thickness between
the two metal layers in the area of the capacitor.

Page 9
Inductance:
The ability of a coil to oppose any instantaneous change in current is a measure of the inductance of that
coil.
The unit of measure of inductance (L) is the Henry.
As current passes through any conductor, a magnetic field is produced around the conductor. The effect of the
magnetic field is such that it opposes the cause that produced it. These magnetic fields take time to build and
collapse, thus resulting in the components ability to resist instantaneous changes in current. In a coil, the loops
of wire interact with each other as well as the core material they are wound around in a specific mathematical
relationship, in order to produce a specific amount of inductance.

An inductor is a device where a wire is coiled around a core material, which is designed to have specific
inductive properties.

Figure 2.5: Inductor schematic symbol.

IN MICROELECTRONICS: Inductors are rarely produced on a microcircuit. And the parasitic effects of
inductance are considered negligible with a very few exceptions.
Typically, inductance is only taken into consideration when evaluating circuits like bond pads and ESD
structures.

Other Definitions

Digital:
A way to represent information in a circuit in a format that is made up of discrete bits of data. Typically a
binary system is used where data is in the form of a 1 (a circuit is turned on) or a 0 (a circuit is turned off).

Analog:
A way to represent information in a circuit where the data is a continuously variable signal over time.

Figure 2.6: A representation of an analog waveform.

Parasitic:

Page 10
In microelectronics, parasitics are the intrinsic physical characteristics of the different layers and materials
that are used to manufacture an Integrated Circuit (IC).
Resistance and capacitance are the primary electrical components of these materials that we are required to
understand in order to predict circuit performance. To perform successful circuit layout, these parasitics must
be understood and controlled.

Noise:
Noise has specific technical definitions depending on the application. For the purpose of this document we
will attempt to simplify this a little.
Think of noise as anything that will add or subtract from the original or intended signal. Sources of noise that
should concern layout are direct results of parasitics, cross-talk, substrate currents and process variations.
Many of these can be controlled and minimized with proper layout techniques described in this book.

Fully Covered Contact (Via):

Many process definitions have two sets of Design Rules (DR) for contact and via metal coverage. There is a
set of rules for minimum DR metal overlap of a contact or via. The minimum DR overlaps are usually
associated with the use of multiple contacts or vias per connection. There is often also a second set of rules for
metal coverage of contacts and vias that ensures a good electrical connection through a single contact or via.
These fully covered rules have metal coverage that is larger than the minimum Design Rule.

Figure 2.7: Fully Covered Contact (Via).

Fully Contacted Strap:

A fully contacted strap is a connection from a transistors drain or source to metal1 through contacts that will
have as many minimum spaced fully covered contacts as will fit on the drain or source. For the purpose of
analog layout, the fully contacted strap will be in the exact center of the source or drain as well (plus or minus
one grid mark).

Figure 2.8: Fully Contacted Strap.

Page 11
Page 12
Diffusion Matching:
Diffusion matching is making the diffusion on a fully contacted strap match exactly the size of the transistors
drain or source diffusion. This will cause the drain or source diffusion to be an exact rectangle with no notches
in the corners.

Figure 2.9: Diffusion Matching.

Unitized Devices:
A unitized approach should be taken when creating larger value devices (usually resistors and capacitors).
This requires picking a smaller device value that corresponds to a reasonably sized device in layout.
Also, in many cases the values picked can be used on multiple assemblies if a somewhat standardized value
is selected. The target value would then be some multiple number of these smaller unitized devices all
connected together in series or parallel as required.
It is generally understood that unitized resistors and capacitors are much more accurate and can be more
accurately matched when necessary.

Isolated Substrates:
Some processes and some projects require isolated substrate regions where the actual substrate name is different
than the tool and full-chip default substrate name.
This can be accomplished by placing a full unbroken n-well guardring around the isolated area. The devices
inside the guardring can have bulk connections named something besides the full-chip default substrate name.
Engineers and Mask Designers must understand that these signals can be isolated for LVS purposes only, but
they are still physically shorted together through substrate. The signals then must be connected together
schematically at the top level assembly.

Legs and Mults:

LEGS: There is much confusion over the subject of legs and mults as they relate to Analog Layout.
Historically, when a single device (in a schematic) is divided into smaller devices that are all connected in
parallel (in layout), the total width of all of the smaller devices are summed together, and then they should equal
the original device width. Each one of these smaller devices is called a LEG.

However, there is a slight complication with processes.

Again, going back to the fact that these processes are designed for high speed digital, when you have any
legged device there is a penalty associated with the legging. This penalty is called the Legging Add-On
Value (LAV).
It is also referred to as the Birds Beak Factor. This means that for every additional leg you must increase
the actual device width by a certain amount.
Page 13
The formula for LAV is as follows:

Wt = Ws + ( n-1) LAV

where: Wt is the total width of all of the legged devices added up in layout.
Ws is the original size of the device as specified in the schematic.
n is the total number of legs.
LAV is the Legging Add-On Value (different for every process).

For example: Assume that a schematic device is sized at 20/.8. If, in layout, this was broken into four legs,
then each single device would be 5/.8 without the LAV factor added in. Assume a LAV of 0.12.

Wt = 20 + (4-1) 0.12
Wt = 20 + (3) 0.12
Wt = 20 + 0.36 = 20.36

The total of the four devices must be 20.36/.8 in order to match the original schematic size of 20/.8. Now you
must distribute the LAV across all four devices. Each device would then be 5.09/.8.

Now we have another problem. The size 5.09 does not fall on our grid. Assume that we have a grid of 0.04
for this example. The closest size would be 5.08. Therefore, we can make three devices 5.08 and one device
5.12. These four devices would then add up to the required 20.36. This size difference between the first three
devices and the larger fourth device is acceptable for digital types of layout. However, this is highly
undesirable for analog layout.
This leads us directly to the subject of MULTS. It is because of this problem that MULT was created.

MULTS: For analog layout purposes it is generally unacceptable to have matching devices that are different
sizes and/or have jogs in the diffusion. The Legging Add-On Value (LAV) described above is not a
requirement necessary for analog design considerations. Therefore, another method of describing devices in a
schematic, in terms of the exact size and number of legs, was devised specifically to meet analog layout and
schematic simulation requirements. This new method is called the MULT factor.

A mult is simply a multiple of a single schematic device.

To continue with the example given above: For an analog sensitive circuit the engineer can specify in the
schematic that the device should be exactly size 5/.8 with a mult = 4 factor. This simply means that there are to
be four parallel devices in layout that are exactly 5/.8.
The Legging Add-On Value is NOT applied in this case.
The resulting layout is more precise and much cleaner since all four devices are exactly the same sizes AND if
they are sharing diffusions there will be no jogs in the diffusions and everything will be drawn to minimum
design rule spacing between the gates.
The end result is a device that has an effective width of (5 x 4) = 20. If there is any degradation of
performance it is then accounted for in the engineers schematic simulations.

Page 14
 Chapter 3: Analog Layout Guidelines

Purpose:

The purpose of this section is to describe the methodologies used in analog layout. There are unique inter-
relationships between the way that schematics are drawn and annotated, and the methods with which those
items are created in the physical layout.

General Analog Layout Guidelines:

The following are some of the general analog guidelines. This document will not spend time justifying the
validity of these guidelines. Guidelines are not Design Rules, and thus are subject to exception. However, you
should seriously consider the implications of wavering from them. This section will also explain the need for
certain types of schematic annotations.

The intention of these guidelines is to be able to understand and control the effects of a circuits parasitics. In
some cases you are able to reduce actual parasitic values. In other cases, you may simply reduce the effect of
the parasitic by matching or balancing. In some cases, you may actually increase the absolute value of a
parasitic in order to decrease the effect of that parasitic on a particular circuit parameter.

Before any device matching and interconnect can take place, you must first ensure that the devices themselves
are created in an ideal manner. The ideal devices methodologies given below will help you to create devices
that are the most likely to have the least parasitic effects, and more importantly they will be more consistent
when fabricated which is extremely important for the purposes of matching.

Ideal Devices
Draw all CMOS transistor device diffusion to minimum Design Rules (DR), but only after ensuring a
fully contacted strap drain and source connection.

Figure 3.1: Minimum Design Rule after Fully Contacted Strap.

Avoid notches in transistor diffusions. Try to make all diffusions rectangular in shape. Use diffusion
matching on all straps. Center the diffusion contacts.

Page 15
 Figure 3.2: No Diffusion Notches.

Avoid the use of dogbone devices. Therefore, the minimum width analog transistors should be exactly
what is required for two diffusion contacts on the drain and source. (There is a two contact minimum
rule for analog circuits. See below.)

Figure 3.2: No Dogbones

Attempt to draw devices in close proximity and symmetrically when they are closely linked in the
schematic. (More about this in the device matching and balancing sections below.)

All CMOS transistors must have poly endcap extensions that are at least twice (2X) the minimum DR.

Figure 3.3: 2x Poly Endcap Extensions.

All devices must have the same orientation (vertical or horizontal).

Page 16
 Two devices are a better match if current is flowing through them in the same direction (drains on one
side and sources on the other side). Therefore, mirroring devices is NOT an acceptable solution to
match devices. (More about this in the device matching and balancing sections below.)

Ideal Interconnect
There is a two contact or via minimum rule for all connections (except NACs).

Figure 3.4: Two Contact/Via Minimum Rule per connection.

Make all critical interconnect the minimum length possible.

Do not use poly for interconnect routing.

Establish a metal direction standard for every project, and adhere to that on all assemblies. Assuming
vertically oriented devices, then use the following metal directions: Metals 1, 3, and 5 vertical. Metals
2, 4, and 6 horizontal. Assuming horizontal devices, then use the following metal directions: Metals 1,
3, and 5 horizontal. Metals 2, 4, and 6 vertical. .

Dont cross any interconnect over the top of devices. This applies to ALL devices including resistors,
capacitors, diodes, and etc... There are several notable exceptions to this rule. For example, large
drivers and PAD circuits require direct contact over devices. Also, it is generally accepted that ESD
structures are to be exempt from this rule.

Figure 3.5: No Routing Over the Top of Devices.

Minimize signal crossings. Especially take care to isolate analog signals from digital signals.

Page 17
 Perfectly match and balance all differential signals. (More about this in the signal matching and
balancing section below.)

Sacrifice area for noise free interconnect.

Avoid the use of minimum width wires. A 2x minimum DR wire is considered a 1x minimum wire for
analog purposes. When area permits, make a wire the same width as the contact or via landing pads
,that you are connecting to.

The processing of corners is not an exact science in microchip technology.

Any pair of identical geometries will match more precisely when there are fewer corners. Try to make
rectangles whenever possible. Of course, over-sizing wires also adds parasitic capacitance, so check with
your Circuit Designer to determine if capacitance or matching is more critical. Also, over-sizing wires
reduces the resistance of the interconnect which is usually considered a significant benefit for analog
circuits.

Figure 3.6: Example of Wire Width Oversizing.

Generously contact (or via) all connections between layers. There is a two contact (or via) minimum
rule (see above) for any connection. Furthermore, fill as many contacts (or vias) as will fit at every
intersection.

Figure 3.7: Use as many contacts/vias as will fit.

Provide signal shielding when required (more about shielding below).

Page 18
Stability and Noise
Maximize all substrate and n-well connections. You should have at least ten times the substrate
connections (in area) as required for the average digital circuits. Some projects require up to 20% of the
total area to be substrate and n-well connection. Many designers feel that 20% is overkill, but
significant substrate and n-well taps are necessary.
Establish a guideline for each project. Furthermore, a substrate or n-well connection in the form of a
guardring is considered acceptable even when the schematic doesnt specifically call for a guardring.
This guardring subtap (or n-well tap) methodology has several advantages in terms of matching and
balancing as well. If fact, many ESD structures require this type of structure.
Also, there are many possible exceptions to this guideline. For example, a particular type of analog
circuit may be extremely sensitive to noise caused by substrate connections. Again, make sure you
establish a guideline for each project before you waste time and space. Every Engineer has a different
opinion on this subject. Different types of analog circuits have different requirements for bulk connections.

Be aware that n-well connections may be tied to signals other than power and ground. Double check all
devices to insure the proper substrate or n-well connections.

Figure 3.8: Example of unique n-well connection.

Some processes and some projects require a clearly defined region where the substrate name is different
than the project tool defaults. This isolated substrate region must be surrounded by a full n-well
guardring (more about isolated substrates above). Double check all devices to insure the proper
substrate or n-well connections.

Use guardrings to help isolate noisy circuits from sensitive circuits that are in close proximity. There are
hundreds of variations of guardrings. Make sure you are using a consistent guardring methodology on
your project (more about guardrings below).

Page 19
Resistors
Avoid dogbones.
And generally speaking, avoid minimum width resistors. The wider the resistor, the more accurate the
resistance value, especially when trying to match resistors.
A minimum resistor width should be whatever size is required for a 2 contact wide connection.

Figure 3.9: No Dogbone Resistors.

Resistors must be well contacted to ensure that the contact (via) resistance is negligible compared to the
value of the resistor.

Avoid bending resistors (serpentine resistors) except in non-critical applications. In fact, most projects
only allow serpentine resistors for ESD applications. Use a unitized resistor approach for more accurate
results.

Figure 3.10: No Serpentine Resistors.

Page 20
Capacitors
There is a maximum Design Rule size allowed for CMOS capacitors, depending upon the process.
However, it is generally understood that large CMOS capacitors do not have the best capacitance per
unit of area.
Also, very large CMOS capacitors typically have less desirable frequency characteristics.
Therefore, it is necessary that each project determine the optimal capacitor sizes based on the process
and circuit performance required. Once this is determined, then the design should incorporate a unitized
approach to building large capacitors that incorporates the smaller optimized devices connected in
parallel (as required).

Figure 3.11: Example of a Unitized CMOS Capacitor.

For all types of capacitors, check the Design Rules of each process for the maximum allowed device
sizes. You may also determine that the largest Design Rule sizes are not necessarily the optimum size
for capacitance and frequency response.

Page 21
Guard rings
Specify the guard rings in terms of (a) the number of contacts wide of each ring, (b) the diffusion type.
The innermost ring would be p type diffusion (ptap), and then the outer ring will be n type in an n-
well (ntap). And please specify exactly what signal to hook the n type ring to. The p ring will go to
the substrate connection, as determined by your project methodology rules.

Figure 3.12: Example GuardRings (corners).

All guardring diffusion widths, and especially the spaces between the diffusions and n-well, should all
be exactly minimum DR.

Deep n-well guardrings are also available on some processes. It is generally accepted that deep n-well
guardrings have the best isolation characteristics.

Make your guardring methodology consistent within your project. Please discuss guardring
methodology with your Lead Engineer and Lead Mask Designer.

Page 22
Shielding
There are several types of shields. A shield is usually a minimum width wire on both sides of a sensitive
signal (same metal layer). The shield is usually tied to ground, or some other quiet low impedance
source. Shields can also be placed over and under a sensitive signal. If you have shield wires on all four
sides, that is called a tunnel or a coax shield (see cross-section A below). (Note: coax in layout
terminology does not imply a transmission line with a characteristic impedance.)

Figure 3.13: Example Cross-Sections of Various Shields.

Shield differential signals together within the shield wires. Rarely will you shield differential signals
from each other. See cross-section C above.

Chapter 4: Device Matching

Purpose:

The purpose of this section is to describe the methodologies used to match devices in analog layout. There are
unique inter-relationships between the way that schematics are drawn and annotated, and the methods with
which those items are created in the physical layout. This section will focus on common centroid,
interdigitation, and other device matching techniques.

Device Matching and Balancing:

Device matching is very different than signal matching. For this reason the two concepts are treated separately
in this manual.

Mirroring
There are several commonly accepted methods of matching devices. Mirroring is NOT usually an acceptable
solution. It may appear on the surface that mirroring is an easy way to match devices, but this is NOT the case.

In order for devices to match, the current must flow through them in the same direction.
When mirroring, the current flows through matched devices in the opposite direction, therefore, causing
them to have slightly different electrical characteristics.

In addition to that, if there is any process variation on any of the metal or via layers, the variation would be such
that mirroring would double the effect. When the stepping technique is used, the variation will more likely be
same on devices in close proximity.

Page 23
For example: On Figure 4.1 below, if the metal2 were skewed slightly to the right, then the mirrored device
on the left would have more metal2 over the poly, and the device on the right would have more metal2 more
over the field. On the stepped example, the skewed metal2 would be both over the poly, thus creating a better
matching condition.

Figure 4.1: Mirroring versus Stepping.

Likewise, on the surface it would appear that mirroring is an easy method to signal match. However, in most
cases the parasitics associated with mirrored wiring are usually not matched because of their proximity to
devices.
Also, it is impossible to use mirrored wiring on the top of devices that are not mirrored. There will be more
about matching wiring in a later section.

There may be cases where mirroring is acceptable. In some cases using the mirroring technique to match
wiring might be more important than the actual device matching. Therefore, it is critical for an Engineer to
decide what is most important.
Normally, device matching is as critical, or even more critical than the benefits of signal matching . Therefore,
mirroring is rarely acceptable in the most sensitive analog circuits. Also, there are known techniques where
both the devices and the signals can match without mirroring.

Common Centroid:
A commonly accepted method of device matching is called common centroid.
This is where devices are placed in an identical manner, exactly spaced in four quadrants around a common
center point.
This method is widely used on differential circuits. It implies that there are exactly two devices that need
critical matching. These devices need to be divided into at least two parts each, in order to fill all four
quadrants.

Common centroid makes the most sense when you have smaller devices (a low number of mults). It is most
commonly used on differential pairs of transistors.

Page 24
 Figure 4.2: A Typical Differential Circuit Schematic.

A single device on a schematic can be divided in layout into several pieces.

These pieces are called legs in the digital realm, and they are called mults in the analog realm.
There is a very big difference in the way that the Cadence tools and the Hercules runsets interpret the legs and
mult factors.
Make sure you have a clear understanding of legs and mults when you create and read schematics.

Page 25
There are an infinite combination of ways to implement this. The most basic form is as show below:

Figure 4.3: Common Centroid Device Placement.

where: A is transistor one divided into two legs.

B is transistor two divided into two legs.

In this case care must be taken to assure that the drains of all devices are on the same side, and the sources of all
devices are on the same side.

Also, the number of legs and mults for a particular device are annotated in the schematic. The Engineer must
assure that the number of mults specified in the schematic can be divided up properly in the four quadrants.
A rule of thumb is that the number of mults be divisible by four, and the result be an even number integer.

Page 26
For example: you can use the following mult numbers:
2
4
2x4=8
4x4=16
6x4=24
8x4=32
10x4=40 etc..

Note to Engineers:
DO NOT use a mult factor in a schematic as a method of sizing devices. You MUST think about the exact
configuration and placement of these devices when you are creating a schematic.

Interdigitate:
Another method to match devices is to interdigitate them. This is simply a way of combining them such that
they are evenly distributed across an area.
This has the unique characteristic that exactly half of the devices have current flowing through them in one
direction, and the other half have current flowing through them in the opposite direction. This will help offset
any variation in the process that is directional.

Interdigitation is most commonly used on current mirrors and other larger (large mult number)
differential pairs of devices. It is also the best know method of matching MORE than two devices.

Also, the assumption when interdigitating is that the drains and sources are shared. But this is not always the
case.

Again, there are an infinite combination of ways to implement this. The most basic form is as show below:

Figure 4.4: Interdigitation Device Placement.

where: A is transistor one divided into four legs.

B is transistor two divided into four legs.

As you can see, the above implementation has A transistors on both ends. One method of eliminating this
mis-match is to use the following configuration:

Page 27
 Figure 4.5: Interdigitation Device Placement Variation.

In this configuration there is one A on an end and one B on an end. However, you may notice that in this
case the A end is on the left and the B end is on the right. If you have larger devices and more mults
available, then you can do the following:

Figure 4.6: Interdigitation Device Placement Variation.

OR

Page 28
 Figure 4.7: Interdigitation Device Placement Variation.

We now have two rows of interdigitated devices. But now the number of ends between A and B match,
each with one end on the left and right.

Note to Engineers:
As you can see, there is not one exact methodology for implementing these devices in layout. Therefore, it is
imperative that the Engineer carefully note their intention on the schematics. As with any methodology it is
imperative that the Engineer calculate the mult numbers of the devices carefully such that they make sense in
the specified configuration.

Obviously you need an even mult number and usually one that is divisible by four, the same as common
centroid (above).

Common Centroid and Interdigitation:

Page 29
It is possible to combine these two methods. There are infinite combinations with which this can be done. I
will only show one example for your consideration.

Figure 4.8: Combining Common Centroid and Interdigitation.

The above example has four groups of eight interdigitated devices. The four groups have been common
centroided. Obviously, if an Engineer wants to specifiy this configuration they must have the correct mult
number for each device (A=16 and B=16 in this example).
Note to Engineers:
DO NOT use a mult factor in a schematic as a method of sizing devices. You MUST think about the exact
configuration and placement of these devices when you are creating a schematic.

Dummification:
Dummification in terms of device matching is very different from dummification in terms of Metal Density
requirements. Please dont confuse the two.

As a small example, and to build upon our previous examples, an Engineer may desire to eliminate the edge
effects of having active devices on the ends of Interdigitated and Common Centroided components. Consider
the following example:

Page 30
 Figure 4.9: Interdigitation Device Placement without Dummy Device.

Even though they match in the sense that A and B have the same number of ends, there are still some cases
where you may want to eliminate the end effect altogether.

One possible solution is as follows:

Figure 4.10: Interdigitation with Additional Dummy Devices.

where: D is a dummy device configured such that it can never become active.

Page 31
This configuration will eliminate the end effect for all active devices.

Another advantage: As you planarize devices (each layer one at a time), the devices on the ends tend to grind
off more material than devices in the center of such an array. Having dummy devices on the ends, allows the
dummies to take most of the excess grinding.

This theory is further amplified with resistors and capacitors. Often, you will want to purposely add dummy
devices completely around the most high precision resistors, capacitors, and transisitors. For example, if you
need a resistor as accurate as possible, you can comfigure it as follows:

Figure 4.11: Example of Unitized Resistors with Dummy Devices.

Where: R is a unitized resistor, and D is a unitized dummy resistor.

Page 32
Note that these dummy devices are LVS-able and MUST be in the schematic. Note that in the case of the
transistors, they are also electrically tied to one of the nodes of each of the active devices. You will most
certainly need to include these devices in your simulations.

Legs and Mults:

Note: See also Chapter 2 Definitions for more about legs and mults.

Legs and Mults are some of the most confusing issues related to schematic annotations. Let me try to make it
simple.

Legs
Legs is the number of devices in layout that a single schematic device can be broken into.

Assumptions:
A leg requires a legging add-on value (or birds beak factor) which is an additional amount of device width
added for each additional leg in the layout. See your DR book. This add-on value is added to the layout, not
changing the original schematic value. The LVS tool automatically calculates the value based upon each
additional leg it finds in the layout, and will compare clean (if done right in layout).

Legs are not to be used in critical analog circuits because of the legging add-on value, which is normally
considered undesirable for sensitive analog circuits. Therefore, it is the assumption of the Mask Designer, when
they see a leg notation, that this device is non-critical layout and then actual leg value can be changed based
on the Mask Designers best judgment, unless otherwise specifically noted in the schematic.

Additionally, when there is a leg value in a schematic, the Mask Designers assume that are to share diffusions,
unless otherwise noted.

Mults
A mult does NOT require an additional legging add-on value. A mult is very different from a leg. A mult takes
a single device as drawn in the schematic and reproduces that exact device a number of times.

Leg breaks a device into a number of smaller pieces that add up to the original size (plus add-on value).
A mult takes a device and replicates it exactly, the result being mult times the original size.

Assumptions:
When a mult factor is used, the Mask Designer assumes that this is critical layout.

A Mask Designer cannot, without first consulting the Engineer, change the mult value.

The LVS tool is capable of automatically comparing clean when using a mult factor.

Also, unless otherwise specified, a mult is assumed to NOT share diffusions.

Last, but not least, when a Mask Designer sees a leg AND a mult factor on a single device in a schematic,
the assumption is that there is a mistake on the schematic. Please use leg OR mult, not both.

Page 33
NOTE: There is a feature in the Cadence Schematic Editor that automatically calculates the leg value for
Ztransistors. In most cases, in analog circuits, the automatic leg value must be overwritten manually.

Chapter 5: Signal Matching

Purpose:

The purpose of this section is to describe the methodologies used to match interconnect in analog layout. There
are unique inter-relationships between the way that schematics are drawn and annotated, and the methods with
which those items are created in the physical layout. This section will focus on techniques that can be used to
match signal wiring and interconnect.

Signal Matching and Balancing:

Signal matching and balancing is very different than device matching. For this reason the two concepts are
treated separately in this manual.

Literally EVERYTHING that is physically located near a particular wire and/or device has some parasitic effect
upon that component. The previous chapter discussed the criticality of correctly placing devices such that they
can have the best matching in terms of parasitics and manufacturing processes. Once you take the utmost care
in placing your devices, then it stands to reason that you must also take care to connect the devices properly.

There is no exact formula for signal matching. Many of the techniques listed below come with some associated
penalty. Therefore, you should determine before you start what exact specification is required in terms of
parasitic matching. It is possible to over-design a circuit. Everything associated with matching and balancing
has some cost of either added parasitic and/or increased area.

To make two (or more) signals match there are additional parasitics added to the circuit. In other words, to
match the parasitics associated with a particular pair of nodes, there is an increase in the absolute value of the
parasitic. It might appear on the surface that in order to reduce the effects of parasitics on a circuit that you
actually reduce the parasitics. But in fact the opposite is true.

Signal matching by exact geometric copying.

Two signals match better when the signals contain the exact same sizes and shapes of geometries. The only
differences in the circuit will be parasitics associated with their position and placement.

In order to match parasitics associated with a sensitive pair of nodes, you usually add a matching parasitic to the
node that has the least absolute value of parasitic. I will attempt to explain this with the following examples.

Page 34
 Figure 5.1: Example of geometric copying.

The BAD example on the left has a signal gate_a Poly gate connection that is shorter than the Poly gate
connection of signal gate_b. Also, the Metal1 connection to gate_a is longer than the Metal1 connection to
gate_b. Furthermore, there is a piece of Metal1 on signal gate_a that is crossing over the Poly (see circle) of
signal gate_b. There is no Metal1 on gate_b that is crossing over a piece of Poly on gate_a.

The BETTER example on the right has Poly gate connections exactly the same length. It also has Metal1
connections that are exactly the same length. It also has matching crossovers of Metal1 over Poly on both
signals (see circles).

As you can see, geometries were added to the circuit in order to make the parasitics match better. Usually you
must add to the absolute value of the parasitics in order to reduce the effect of the parasitic by matching. Also,
you can see that by adding geometries it can also increase the area required for the circuit.
Signal matching by adding shielding.
We can take this approach one step further. Consider the drain and source connections in Figure 5.2. Note that
in the BAD example there is a common signal that is directly next to the outb signal. The outa signal has no
equivalent parasitic. By placing an extra common signal on both sides of the matched pair, you can better
match the parasitic associated with both signals. In practical terms, adding shielding around matched pairs of
signals can increase their matched characteristics.

But again, on the negative side, you can see the increased area. You can also see a dramatic increase in the
absolute value of the parasitic associated with shielding. Usually you can use techniques like this within
localized circuitry, but then you can drop the shielding when routing outside of the congested areas.

Page 35
 Figure 5.2: Signal Matching by adding shields.

Extreme care must be taken when using shields around sensitive analog signals. A noisy shield signal can
actually inject noise into a circuit, when it was originally intended to actually keep noise away from the signal.
Therefore, it is imperative that you find a very quiet low impedance source to connect your shields.

The example above uses the common signal as the shield. This particular arrangement is usually only
considered valid for matching purposes in small localized situations. If the shield will extend beyond this
circuit, you should consider connecting the shields to a quiet VCC or VSS source.

Signal matching by increased spacing.

Even with these techniques in place, you can see that there are still slight mismatches. For example, the Metal1
on signal gate_a (in Figure 5.2) is closer to the actual devices A and B. Where signal gate_b has no such
matching devices next to it. You could also add shields to the gate signals. Or you could slide the gate signals
away from the devices such that the parasitic is negligible. It is generally considered that parasitics are
negligible when there is over 3 microns of space. For interconnect that travels long distances, the spacing must
be greater. For example, if a matched pair of wires must travel 1000 microns next to another signal, then the
spacing must be much greater that 3 microns for the parasitic to be negligible.

Notice also in Figure 5.3 where the re-ordering of the common signal helps in this case. The common signal has
no signal that it must match, therefore, it is acceptable for that signal to be close to the devices as long as the
distance to the devices is equal.

Page 36
 Figure 5.3: Signal matching by increased spacing.

There are trade-offs between adding space or adding shields. Adding space has one considerable advantage
over shielding in that the total parasitic capacitance is greatly decreased. Shielding has a slight advantage over
increased spacing in that you can usually add shields that require less area than simple spacing.

Mirroring:
There are several commonly accepted methods of matching routing. Mirroring is NOT usually an acceptable
solution. It may appear on the surface that mirroring is an easy way to match signals, but this is NOT the case.
In order for devices to match, the current must flow through them in the same direction. When mirroring, the
current flows through matched devices in the opposite direction, therefore, causing them to have slightly
different electrical characteristics.

Page 37
 Figure 5.4: Unmatched Metal1 when mirrored.

Under normal manufacturing conditions it is possible for different layers to shift slightly. Figure 5.4 shows an
exaggerated example of a Metal1 shift to the right. When mirrored circuits are used, this shift can cause
significant parasitic differences between device A and device B. Notice the source of device A has more Metal1
over the gate. Also notice that the drain of device B has more Metal1 over the gate.(2ND FIG.)

The implementation of stepped devices (as opposed to mirrored) will reduce the effect of this process shifting of
layers. It is more likely that any layer shift will occur consistently in a localized area.
Therefore, if all devices are oriented identically, the process variation will more likely affect all of the devices
in a similar manner, thus increasing the matching characteristics.
The exact opposite occurs when mirroring. When mirroring, the affect of any process variation is likely to be
doubled.

Page 38
 Figure 5.5: Example of a mirrored matched pair.

Please consider some other possible disadvantages to mirrored circuits. In Figure 5.5, consider that the input
and output signals are on opposite sides of the layout. To keep these signals matched outside of this localized
circuit will require tremendous care. Usually the circuits are much larger than the two device example show
above. Also, in many mirrored applications, the matched devices can be separated by other devices in a larger
group of circuitry, thus separating them by a greater distance, which can cause other process variations that will
reduce the matching of the devices. We discussed earlier about current flowing in opposite directions (see
Figure 4.1) through matched devices as being unacceptable.

Mirroring IS NOT an acceptable solution for matching except in the least critical of applications.

Page 39