288418312adsp Bf533 Ez Kit Lite Manual Rev. 3.1

ADSP-BF533 EZ-KIT Lite®
Evaluation System Manual
Revision 3.1, September 2007

Part Number
82-000730-01
Analog Devices, Inc.

One Technology Way
Norwood, Mass. 02062-9106 a
Copyright Information
©2007 Analog Devices, Inc., ALL RIGHTS RESERVED. This document
may not be reproduced in any form without prior, express written consent
from Analog Devices, Inc.
Printed in the USA.
Limited Warranty
The EZ-KIT Lite evaluation system is warranted against defects in materi-
als and workmanship for a period of one year from the date of purchase
from Analog Devices or from an authorized dealer.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli-
cation or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice

The Analog Devices icon bar and logo, VisualDSP++, VisualDSP++ logo,
Blackfin, Blackfin logo, CROSSCORE logo, EZ-KIT Lite, and
EZ-Extender are registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
Regulatory Compliance
The ADSP-BF533 EZ-KIT Lite is designed to be used solely in a labora-
tory environment. The board is not intended for use as a consumer end
product or as a portion of a consumer end product. The board is an open
system design which does not include a shielded enclosure and therefore
may cause interference to other electrical devices in close proximity. This
board should not be used in or near any medical equipment or RF devices.
The ADSP-BF533 EZ-KIT Lite has been certified to comply with the
essential requirements of the European EMC directive 89/336/EEC
amended by 93/68/EEC and therefore carries the “CE” mark.
The ADSP-BF533 EZ-KIT Lite has been appended to Analog Devices,
Inc. Technical Construction File (TCF) referenced ‘DSPTOOLS1’ dated
December 21, 1997 and was awarded CE Certification by an appointed
European Competent Body as listed below.
Technical Certificate No: Z600ANA1.011
Issued by: Technology International (Europe) Limited
60 Shrivenham Hundred Business Park
Shrivenham, Swindon, SN6 8TY, UK
The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge)

sensitive devices. Electrostatic charges readily accumulate on the human body
and equipment and can discharge without detection. Permanent damage may
occur on devices subjected to high-energy discharges. Proper ESD precau-
tions are recommended to avoid performance degradation or loss of func-
tionality. Store unused EZ-KIT Lite boards in the protective shipping
package.
CONTENTS
PREFACE
Purpose of This Manual ................................................................. xii
Intended Audience ......................................................................... xii
Manual Contents .......................................................................... xiii
What’s New in This Manual ........................................................... xiv
Technical or Customer Support ...................................................... xiv
Supported Processors ....................................................................... xv
Product Information ....................................................................... xv
MyAnalog.com .......................................................................... xv
Processor Product Information .................................................. xvi
Related Documents .................................................................. xvi
Online Technical Documentation ............................................ xvii
Accessing Documentation From VisualDSP++ .................... xviii
Accessing Documentation From Windows .......................... xviii
Accessing Documentation From Web ................................... xix
Printed Manuals ....................................................................... xix
Hardware Tools Manuals ...................................................... xix
Processor Manuals ................................................................. xx
Data Sheets ........................................................................... xx
ADSP-BF533 EZ-KIT Lite Evaluation System Manual v

CONTENTS
Notation Conventions .................................................................... xx
USING ADSP-BF533 EZ-KIT LITE

Package Contents ......................................................................... 1-2
Default Configuration .................................................................. 1-3
Installation and Session Startup ..................................................... 1-5
Evaluation License Restrictions ..................................................... 1-7
Memory Map ............................................................................... 1-7
SDRAM Interface ......................................................................... 1-9
Flash Memory ............................................................................ 1-10
Flash Memory Map ............................................................... 1-10
Flash General-Purpose IO ..................................................... 1-12
Configuring Flash Memory ................................................... 1-14
LEDs and Push Buttons .............................................................. 1-15
Audio Interface ........................................................................... 1-15
Video Interface ........................................................................... 1-16
Example Programs ...................................................................... 1-17
Background Telemetry Channel .................................................. 1-17
ADSP-BF533 EZ-KIT LITE HARDWARE REFERENCE

System Architecture ...................................................................... 2-2
External Bus Interface Unit ..................................................... 2-3
SPORT Audio Interface .......................................................... 2-3
SPI Interface ........................................................................... 2-4
Programmable Flags ................................................................ 2-4
vi ADSP-BF533 EZ-KIT Lite Evaluation System Manual

CONTENTS
PPI Interface ........................................................................... 2-5

Video Output Mode ........................................................... 2-7
Video Input Mode .............................................................. 2-7
UART Port .............................................................................. 2-8
Expansion Interface ................................................................. 2-8
JTAG Emulation Port .............................................................. 2-9
Jumper and Switch Settings ......................................................... 2-10
UART Loop Jumper (JP4) ..................................................... 2-10
Boot Mode Switch (SW11) .................................................... 2-11
Test DIP Switches (SW1 and SW2) ........................................ 2-11
Video Configuration Switch (SW3) ....................................... 2-11
Push Button Enable Switch (SW9) ......................................... 2-12
SPIS1/SPISS Select Switch (SW10) ........................................ 2-13
SPORT0 Switch (SW12) ....................................................... 2-13
LEDs and Push Buttons .............................................................. 2-13
Programmable Flag Push Buttons (SW4–7) ............................ 2-13
Reset Push Button (SW8) ...................................................... 2-15
Power LED (LED1) ............................................................... 2-15
Reset LED (LED2) ................................................................ 2-15
User LEDs (LED4–9) ............................................................ 2-15
USB Monitor LED (ZLED3) ................................................. 2-16
Connectors ................................................................................. 2-17
Expansion Interface (J1–3) .................................................... 2-17
Audio (J4 and J5) .................................................................. 2-18
ADSP-BF533 EZ-KIT Lite Evaluation System Manual vii

CONTENTS
Video (J8) ............................................................................. 2-18

Power (J9) ............................................................................ 2-18
FlashLINK (P1) .................................................................... 2-19
RS-232 (P2) ......................................................................... 2-20
SPORT1 (P3) ....................................................................... 2-20
JTAG (ZP4) .......................................................................... 2-21
SPI (P6) ................................................................................ 2-21
ADSP-BF533 EZ-KIT LITE BILL OF MATERIALS

ADSP-BF533 EZ-KIT LITE SCHEMATIC
Title Page ..................................................................................... B-1
ADSP-BF533 Processor ................................................................ B-2
Memory ....................................................................................... B-3
Audio Codec ................................................................................ B-4
Audio Out .................................................................................... B-5
Audio In ....................................................................................... B-6
Video Out .................................................................................... B-7
Video In ....................................................................................... B-8
IO/Reset/UART ........................................................................... B-9
Connectors ................................................................................. B-10
Power ......................................................................................... B-11
Bypass Caps ................................................................................ B-12
INDEX
viii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

PREFACE
Thank you for purchasing the ADSP-BF533 EZ-KIT Lite®, Analog

Devices, Inc. evaluation system for Blackfin® processors.
Blackfin processors support a media instruction set computing (MISC)
architecture. This architecture is the natural merging of RISC, media
functions, and digital signal processing (DSP) characteristics. Blackfin
processors deliver signal-processing performance in a microprocessor-like
environment.
The evaluation board is designed to be used in conjunction with the Visu-
alDSP++® development environment to test the capabilities of
ADSP-BF533 Blackfin processors. The VisualDSP++ development envi-
ronment gives you the ability to perform advanced application code
development and debug, such as:
• Create, compile, assemble, and link application programs written
in C++, C, and ADSP-BF533 assembly
• Load, run, step, halt, and set breakpoints in application programs
• Read and write data and program memory
• Read and write core and peripheral registers
• Plot memory
Access to the ADSP-BF533 processor from a personal computer (PC) is
achieved through a USB port or an optional JTAG emulator. The USB
interface gives unrestricted access to the ADSP-BF533 processor and the
evaluation board peripherals. Analog Devices JTAG emulators offer faster
ADSP-BF533 EZ-KIT Lite Evaluation System Manual ix

communication between the host PC and target hardware. Analog Devices
carries a wide range of in-circuit emulation products. To learn more about
Analog Devices emulators and processor development tools, go to
http://www.analog.com/dsp/tools/.
The ADSP-BF533 EZ-KIT Lite provides example programs to demon-

strate the capabilities of the evaluation board.
L The ADSP-BF533 EZ-KIT Lite installation is part of the Visu-

alDSP++ installation. The EZ-KIT Lite is a licensed product that
offers an unrestricted evaluation license for the first 90 days. For
details about evaluation license restrictions after the 90 days, refer
to “Evaluation License Restrictions” on page 1-7 and the Visu-
alDSP++ Installation Quick Reference Card.
The board features:
• Analog Devices ADSP-BF533 Blackfin processor
D Performance up to 600 MHz
D 160-pin mini-BGA package
D 27 MHz CLKIN oscillator
• Synchronous dynamic random access memory (SDRAM)
D MT48LC32M16 - 64 MB (32M x 16 bits)
• Flash memories
D 2 MB (512K x 16 x 2chips)
• Analog audio interface
D AD1836 – Analog Devices 96 kHz audio codec
D 4 input RCA phono jacks (2 channels)
D 6 output RCA phono jacks (3 channels)
x ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface
• Analog video interface

D ADV7183 video decoder w/ 3 input RCA phono jacks
D ADV7171 video encoder w/ 3 output RCA phono jacks
• Universal asynchronous receiver/transmitter (UART)
D ADM3202 RS-232 line driver/receiver
D DB9 male connector
• LEDs
D 10 LEDs: 1 power (green), 1 board reset (red), 1 USB (red),
6 general-purpose (amber), and 1 USB monitor (amber)
• Push buttons
D 5 push buttons with debounce logic: 1 reset,
4 programmable flags
• Expansion interface
D PPI, SPI, EBIU, Timers2-0, UART, programmable flags,
SPORT0, SPORT1
• Other features
D JTAG ICE 14-pin header
The EZ-KIT Lite board has two flash memories with a total of 2 MB of
memory. The flash memories can be used to store user-specific boot code,
allowing the board to run as a stand-alone unit. For more information, see
“Flash Memory” on page 1-10. The board also has 64 MB of SDRAM,
which can be used by the user at runtime.
SPORTs interface with the AD1836 audio codec to aid development of
audio signal processing applications. SPORT0 also attaches to an off-board
connector for communication with other serial devices. For information
about SPORT0, see “SPORT Audio Interface” on page 2-3.
ADSP-BF533 EZ-KIT Lite Evaluation System Manual xi

Purpose of This Manual
The parallel peripheral interface (PPI) of the processor connects to both a

video encoder and video decoder, facilitating development of video signal
processing applications.
The UART of the processor connects to an RS-232 line driver and a DB9
male connector, providing an interface to a PC or other serial device.
Additionally, the EZ-KIT Lite board provides access to most of the pro-
cessor’s peripheral ports. Access is provided in the form of a
three-connector expansion interface. For information about the expansion
interface, see “Expansion Interface” on page 2-8.
Purpose of This Manual

The ADSP-BF533 EZ-KIT Lite Evaluation System Manual provides
instructions for installing the product hardware (board). The text
describes the operation and configuration of the board components and
provides guidelines for running your own code on the ADSP-BF533
EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a
reference for future designs.
The product software installation is detailed in the VisualDSP++ Installa-
tion Quick Reference Card.
Intended Audience
The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set. Programmers who are unfamiliar with Analog Devices
processors can use this manual but should supplement it with other texts
(such as the ADSP-BF533 Processor Hardware Reference and the Blackfin
Processor Instruction Set Reference) that describe your target architecture.
xii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface
Programmers who are unfamiliar with VisualDSP++ should refer to the

VisualDSP++ online Help and user’s or getting started guides. For the
locations of these documents, see “Related Documents”.
Manual Contents
The manual consists of:
• Chapter 1, “Using ADSP-BF533 EZ-KIT Lite” on page 1-1
Describes the EZ-KIT Lite functionality from a programmer’s per-
spective and provides an easy-to-access memory map.
• Chapter 2, “ADSP-BF533 EZ-KIT Lite Hardware Reference” on
page 2-1
Provides information on the EZ-KIT Lite hardware components.
• Appendix A, “ADSP-BF533 EZ-KIT Lite Bill Of Materials” on
page A-1
Provides a list of components used to manufacture the EZ-KIT
Lite board.
• Appendix B, “ADSP-BF533 EZ-KIT Lite Schematic” on page B-1
Provides the resources to allow EZ-KIT Lite board-level debugging
or to use as a reference design.
L Appendix B now is part of the online Help. The PDF version of

the ADSP-BF533 EZ-KIT Lite Evaluation System Manual is located
in the Docs\EZ-KIT Lite Manuals folder on the installation CD.
Alternatively, the schematics can be found on the Analog Devices
Web site: www.analog.com/processors.
ADSP-BF533 EZ-KIT Lite Evaluation System Manual xiii

What’s New in This Manual
What’s New in This Manual

The ADSP-BF533 EZ-KIT Lite Evaluation System Manual has been
updated for the current revision of VisualDSP++.
Appendix B, “ADSP-BF533 EZ-KIT Lite Schematic” on page B-1 have
been updated to reflect the latest revision of the board.
Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following
ways:
• Visit the Embedded Processing and DSP products Web site at
http://www.analog.com/processors/technicalSupport
• E-mail tools questions to

processor.tools.support@analog.com
• E-mail processor questions to

processor.support@analog.com (World wide support)
processor.europe@analog.com (Europe support)
processor.china@analog.com (China support)
• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized
distributor
• Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
xiv ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface
Supported Processors
This evaluation system supports Analog Devices ADSP-BF533 Blackfin
processors.
Product Information
You can obtain product information from the Analog Devices Web site,
from the product CD-ROM, or from printed publications (manuals).
Analog Devices is online at www.analog.com. Our Web site provides infor-
mation about a broad range of products—analog integrated circuits,
amplifiers, converters, and digital signal processors.
MyAnalog.com
MyAnalog.com is a free feature of the Analog Devices Web site that allows
customization of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.
Registration:
Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as means for you to select
the information you want to receive.
If you are already a registered user, just log on. Your user name is your
e-mail address.
ADSP-BF533 EZ-KIT Lite Evaluation System Manual xv

Product Information
Processor Product Information

For information on embedded processors and DSPs, visit our Web site at
www.analog.com/processors, which provides access to technical publica-
tions, data sheets, application notes, product overviews, and product
announcements.
You may also obtain additional information about Analog Devices and its
products in any of the following ways.
• E-mail questions or requests for information to
processor.support@analog.com (World wide support)
processor.europe@analog.com (Europe support)
processor.china@analog.com (China support)
• Fax questions or requests for information to

1-781-461-3010 (North America)
+49-89-76903-157 (Europe)
Related Documents
For information on product related development software, see the follow-
ing publications.
Table 1. Related Processor Publications

Title Description
ADSP-BF533 Embedded Processor Datasheet General functional description, pinout, and

timing.
ADSP-BF533 Blackfin Processor Hardware Ref- Description of internal processor architecture

erence and all register functions.
Blackfin Processor Instruction Set Reference Description of all allowed processor assembly
instructions.
xvi ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface
Table 2. Related VisualDSP++ Publications

Title Description
VisualDSP++ User’s Guide Description of VisualDSP++ features and usage.
VisualDSP++ Assembler and Preprocessor Description of the assembler function and com-
Manuals mands.
VisualDSP++ C/C++ Complier and Library Description of the complier function and com-
Manual for Blackfin Processors mands for Blackfin processors.
VisualDSP++ Linker and Utilities Manual Description of the linker function and com-
mands.
VisualDSP++ Loader and Utilities Manual Description of the loader/splitter function and
commands.
L IfJTAG
you plan to use the EZ-KIT Lite board in conjunction with a
emulator, also refer to the documentation that accompanies
the emulator.
All documentation is available online. Most documentation is available in
printed form.
Visit the Technical Library Web site to access all processor and tools man-
uals and data sheets:
http://www.analog.com/processors/technicalSupport/technicalLi-
brary/.
Online Technical Documentation

Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary .pdf files of most manuals are provided in the
Docs folder on the VisualDSP++ installation CD.
ADSP-BF533 EZ-KIT Lite Evaluation System Manual xvii

Product Information
Each documentation file type is described as follows.
File Description
.chm Help system files and manuals in Help format
.htm or Dinkum Abridged C++ library and FlexLM network license manager software doc-
.html umentation. Viewing and printing the .html files requires a browser, such as
Internet Explorer 6.0 (or higher).
.pdf VisualDSP++ and processor manuals in Portable Documentation Format (PDF).

Viewing and printing the .pdf files requires a PDF reader, such as Adobe Acrobat
Reader (4.0 or higher).
If documentation is not installed on your system as part of the software

installation, you can add it from the VisualDSP++ CD at any time by run-
ning the Tools installation. Access the online documentation from the
VisualDSP++ environment, Windows® Explorer, or the Analog Devices
Web site.
Accessing Documentation From VisualDSP++

To view VisualDSP++ Help, click on the Help menu item or go to the
Windows task bar and navigate to the VisualDSP++ documentation via
the Start menu.
To view ADSP-BF533 EZ-KIT Lite Help, which is part of the Visu-
alDSP++ Help system, use the Contents or Search tab of the Help
window.
Accessing Documentation From Windows

In addition to any shortcuts you may have constructed, there are many
ways to open VisualDSP++ online Help or the supplementary documenta-
tion from Windows.
xviii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface
Help system files (.chm) are located in the Help folder, and .pdf files are
located in the Docs folder of your VisualDSP++ installation CD-ROM.
The Docs folder also contains the Dinkum Abridged C++ library and the
FlexLM network license manager software documentation.
Your software installation kit includes online Help as part of the Windows
interface. These help files provide information about VisualDSP++ and
the ADSP-BF533 EZ-KIT Lite evaluation system.
Accessing Documentation From Web

Download manuals at the following Web site:
http://www.analog.com/processors/technicalSupport/technicalLi-
brary/.
Select a processor family and book title. Download archive (.zip) files, one
for each manual. Use any archive management software, such as WinZip,
to decompress downloaded files.
Printed Manuals
For general questions regarding literature ordering, call the Literature
Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
Hardware Tools Manuals

To purchase EZ-KIT Lite and in-circuit emulator (ICE) manuals, call
1-603-883-2430. The manuals may be ordered by title or by product
number located on the back cover of each manual.
ADSP-BF533 EZ-KIT Lite Evaluation System Manual xix

Notation Conventions
Processor Manuals
Hardware reference and instruction set reference manuals may be ordered
through the Literature Center at 1-800-ANALOGD (1-800-262-5643),
or downloaded from the Analog Devices Web site. Manuals may be
ordered by title or by product number located on the back cover of each
manual.
Data Sheets
All data sheets (preliminary and production) may be downloaded from the
Analog Devices Web site. Only production (final) data sheets (Rev. 0, A,
B, C, and so on) can be obtained from the Literature Center at
1-800-ANALOGD (1-800-262-5643); they also can be downloaded from
the Web site.
To have a data sheet faxed to you, call the Analog Devices Faxback System
at 1-800-446-6212. Follow the prompts and a list of data sheet code
numbers will be faxed to you. If the data sheet you want is not listed,
check for it on the Web site.
Text conventions used in this manual are identified and described as
follows.
Example Description
Close command Titles in reference sections indicate the location of an item within the
(File menu) VisualDSP++ environment’s menu system (for example, the Close
command appears on the File menu).
{this | that} Alternative required items in syntax descriptions appear within curly
brackets and separated by vertical bars; read the example as this or
that. One or the other is required.
xx ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Preface
Example Description
[this | that] Optional items in syntax descriptions appear within brackets and sepa-
rated by vertical bars; read the example as an optional this or that.
[this,…] Optional item lists in syntax descriptions appear within brackets
delimited by commas and terminated with an ellipse; read the example
as an optional comma-separated list of this.
.SECTION Commands, directives, keywords, and feature names are in text with
letter gothic font.
filename Non-keyword placeholders appear in text with italic style format.
Note: For correct operation, ...
L A Note provides supplementary information on a related topic. In the

online version of this book, the word Note appears instead of this
symbol.
Caution: Incorrect device operation may result if ...
a
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.
Warning: Injury to device users may result if ...
[
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Warning
appears instead of this symbol.
ADSP-BF533 EZ-KIT Lite Evaluation System Manual xxi

xxii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

1 USING ADSP-BF533 EZ-KIT
LITE
This chapter provides specific information to assist you with development

of programs for the ADSP-BF533 EZ-KIT Lite evaluation system.
The information appears in the following sections.
• “Package Contents” on page 1-2
Lists the items contained in your ADSP-BF533 EZ-KIT Lite
package.
• “Default Configuration” on page 1-3
Shows the default configuration of the ADSP-BF533 EZ-KIT Lite.
• “Installation and Session Startup” on page 1-5
Instructs how to start a new or open an existing ADSP-BF533
EZ-KIT Lite session using VisualDSP++.
• “Evaluation License Restrictions” on page 1-7
Describes the restrictions of the VisualDSP++ demo license
shipped with the EZ-KIT Lite.
• “Memory Map” on page 1-7
Defines the ADSP-BF533 EZ-KIT Lite board’s memory map.
• “SDRAM Interface” on page 1-9·
Defines the register values to configure the on-board SDRAM.
• “Flash Memory” on page 1-10
Describes the on-board flash memory.
• “LEDs and Push Buttons” on page 1-15
Describes the board’s general-purpose IO pins and buttons.
ADSP-BF533 EZ-KIT Lite Evaluation System Manual 1-1

Package Contents
• “Audio Interface” on page 1-15

Describes the board’s audio interface.
• “Video Interface” on page 1-16
Describes the board’s video interface.
• “Example Programs” on page 1-17
Provides information about the example programs included in the
ADSP-BF533 EZ-KIT Lite evaluation system.
• “Background Telemetry Channel” on page 1-17
Highlights the advantages of the background telemetry channel
feature of VisualDSP++.
For information on the graphical user interface, including the boot load-
ing, target options, and other facilities of the EZ-KIT Lite system, refer to
the online Help.
For more detailed information about programming the ADSP-BF533
Blackfin processor, see the documents referred to as “Related
Documents”.
Package Contents
Your ADSP-BF533 EZ-KIT Lite evaluation system package contains the
following items.
• ADSP-BF533 EZ-KIT Lite board
• VisualDSP++ Installation Quick Reference Card
• CD containing:
D VisualDSP++ software
D ADSP-BF533 EZ-KIT Lite debug software
1-2 ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Using ADSP-BF533 EZ-KIT Lite
D USB driver files

D Example programs
D ADSP-BF533 EZ-KIT Lite Evaluation System Manual (this
document)
• Universal 7.5V DC power supply
• USB 2.0 type cable
• Registration card (please fill out and return)
If any item is missing, contact the vendor where you purchased your
EZ-KIT Lite or contact Analog Devices, Inc.
Default Configuration
The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge)
sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without detection. Permanent
damage may occur on devices subjected to high-energy discharges. Proper
ESD precautions are recommended to avoid performance degradation or
loss of functionality. Store unused EZ-KIT Lite boards in the protective
shipping package.
The ADSP-BF533 EZ-KIT Lite board is designed to run outside your per-
sonal computer as a stand-alone unit. You do not have to open your
computer case.
When removing the EZ-KIT Lite board from the package, handle the
board carefully to avoid the discharge of static electricity, which may dam-
age some components. Figure 1-1 shows the default jumper settings, DIP
switch, connector locations, and LEDs used in installation. Confirm that
your board is set up in the default configuration before using the board.

Default Configuration
Figure 1-1. EZ-KIT Lite Hardware Setup

To connect the EZ-KIT Lite board:
1. Plug the provided power supply into J9 on the EZ-KIT Lite board.
Visually verify that the green power LED (LED1) is on. Also verify
that the red reset LED (LED2) goes on for a moment and then goes
off.
2. Connect one end of the USB cable to an available full speed USB
port on your PC and the other end to ZJ1 on the ADSP-BF533
EZ-KIT Lite board.

Installation and Session Startup
L For correct operation, install the software and hardware in the

order presented in the VisualDSP++ Installation Quick Reference
Card.
1. Verify that the yellow USB monitor LED (ZLED3, located near the
USB connector) is lit. This signifies that the board is communicat-
ing properly with the host PC and is ready to run VisualDSP++.
2. If you are running VisualDSP++ for the first time, navigate to the
VisualDSP++ environment via the Start –> Programs menu. The
main window appears. Note that VisualDSP++ does not connect to
any session. Skip the rest of this step to step 3.
If you have run VisualDSP++ previously, the last opened session

appears on the screen. You can override the default behavior and
force VisualDSP++ to start a new session by pressing and holding
down the Ctrl key while starting VisualDSP++. Do not release the
Ctrl key until the Session Wizard appears on the screen. Go to
step 4.
3. To connect to a new EZ-KIT Lite session, start Session Wizard by
selecting one of the following.
• From the Session menu, New Session.
• From the Session menu, Session List. Then click New Ses-
sion from the Session List dialog box.
• From the Session menu, Connect to Target.
4. The Select Processor page of the wizard appears on the screen.
Ensure Blackfin is selected in Processor family. In Choose a target
processor, select ADSP-BF533. Click Next.
5. The Select Connection Type page of the wizard appears on the
screen. Select EZ-KIT Lite and click Next.

Installation and Session Startup
6. The Select Platform page of the wizard appears on the screen.

Ensure that the selected platform is ADSP-BF533 EZ-KIT Lite via
Debug Agent. Specify your own Session name for your session or
accept the default name.
The session name can be a string of any length; although, the box
displays approximately 32 characters. The session name can
include space characters. If you do not specify a session name,
VisualDSP++ creates a session name by combining the name of the
selected platform with the selected processor. The only way to
change a session name later is to delete the session and to open a
new session.
Click Next.
7. The Finish page of the wizard appears on the screen. The page dis-
plays your selections.Check the selections. If you are not satisfied,
click Back to make changes; otherwise, click Finish. VisualDSP++
creates the new session and connects to the EZ-KIT Lite. Once
connected, the main window’s title is changed to include the ses-
sion name set in step 6.
L Toor select
disconnect from a session, click the disconnect button
Session–>Disconnect from Target.
To delete a session, select Session –> Session List. Select the ses-
sion name from the list and click Delete. Click OK.

Evaluation License Restrictions

The ADSP-BF533 EZ-KIT Lite installation is part of the VisualDSP++
installation. The EZ-KIT Lite is a licensed product that offers an unre-
stricted evaluation license for the first 90 days. Once the initial
unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-BF533 EZ-KIT
Lite via the USB debug agent interface only. Connections to simu-
lators and emulation products are no longer allowed.
• The linker restricts a users program to 20 KB of internal memory
for code space with no restrictions for data space.
L The EZ-KIT Lite hardware must be connected and powered up to

use VisualDSP++ with a valid evaluation or permanent license.
Refer to the VisualDSP++ Installation Quick Reference Card for details.
Memory Map
The ADSP-BF533 processor has internal SRAM that can be used for
instruction or data storage. The configuration of internal SRAM is
detailed in the ADSP-BF533 Processor Hardware Reference.
The ADSP-BF533 EZ-KIT Lite board includes two types of external
memory, SDRAM and flash memory.
The size of the SDRAM is 64 Mbytes (32M x 16-bits). The processor’s
memory select pin ~SMS0 is configured for the SDRAM.
The flash memory is implemented with two dual-bank flash memory
devices. These devices include primary and secondary flash memory as
well as internal SRAM and registers. Primary flash memory totals
2 Mbytes mapped into two separate asynchronous memory banks,

Memory Map
1 Mbyte each. Secondary flash memory, along with SRAM and registers,
occupies the third bank of asynchronous memory space. The processor’s
~AMS0, ~AMS1, and ~AMS2 memory select pins are used for that purpose.
Table 1-1. EZ-KIT Lite Evaluation Board Memory Map

Start Address End Address Content
External 0x0000 0000 0x07FF FFFF SDRAM bank 0 (SDRAM). See “SDRAM Interface”
Memory on page 1-9.
0x2000 0000 0x200F FFFF ASYNC memory bank 0 (primary flash A). See
“Flash Memory” on page 1-10.
0x2010 0000 0x201F FFFF ASYNC memory bank 1 (primary flash B). See
“Flash Memory” on page 1-10.
0x2020 0000 0x202F FFFF ASYNC memory bank 2 (flash A and B secondary
memory, SRAM and internal registers). See “Flash
Memory” on page 1-10.
All other locations Not used
Internal 0xFF80 0000 0xFF80 3FFF Data bank A SRAM 16 KB
Memory
0xFF80 4000 0xFF80 7FFF Data bank A SRAM/CACHE 16 KB
0xFF90 0000 0xFF90 3FFF Data bank B SRAM 16 KB
0xFF90 4000 0xFF90 7FFF Data bank B SRAM/CACHE 16 KB
0xFFA0 0000 0xFFA0 FFFF Instruction SRAM 64 KB
0xFFA1 0000 0xFFA1 3FFF Instruction SRAM /CACHE 16 KB
0xFFB0 0000 0xFFBO 0FFF Scratch pad SRAM 4 KB
0xFFC0 0000 0xFFDF FFFF System MMRs 2 MB

0xFFE0 0000 0xFFFF FFFF Core MMRs 2 MB
All other locations Reserved

SDRAM Interface
The three SDRAM control registers must be initialized in order to use the
MT48LC32M16 – 64 MB (32M x 16 bits) SDRAM memory.
If you are in an EZ-KIT Lite or emulator session and a reset operation is
performed, the SDRAM registers are set automatically to the values listed
in Table 1-2. To disable this feature, clear the Use XML reset values
check box on the Target Options dialog box, which is accessible through
the Settings pull-down menu. The values are derived for maximum flexi-
bility and work for a system clock frequency between 54 MHz and
133 MHz. For more information about the Target Options dialog box,
see the online Help.
Automatic configuration of SDRAM is not optimized for any SCLK fre-
quency. Table 1-2 shows the optimized configuration for the SDRAM
registers using a 118.8 MHz, 126 MHz, and 133 MHz SCLK. The fre-
quency of 118.8 MHz is the maximum SCLK frequency when using a
594 MHz core frequency, the maximum frequency for the EZ-KIT Lite
when using the internal voltage regulator. Only the EBIU_SDRRC register
needs to be modified in the user code to achieve maximum performance.
Table 1-2. SDRAM Optimum Settings

Register SCLK = 133 MHz SCLK = 126 MHz SCLK = 118.8 MHz
(Processor MAX) (CCLK = 756 MHz) (CCLK = 594 MHz)
EBIU_SDGCTL 0x0091 998D 0x0091 998D 0x0091 998D
EBIU_SDBCTL
ADSP-BF533 EZ-KIT Lite 0x0000 0013 0x0000 0013 0x0000 0013

revision 1.5 and below
ADSP-BF533 EZ-KIT Lite 0x0000 0025 0x0000 0025 0x0000 0025

revision 1.6 and above
EBIU_SDRRC 0x0000 0406 0x0000 03CF 0x0000 0397

Flash Memory
An example program is included in the EZ-KIT Lite installation directory

to demonstrate how to set up the SDRAM interface.
Flash Memory
The following sections describe how to use the memory and general-pur-
pose IO pins, as well as how to configure the flash memory devices.
The ADSP-BF533 EZ-KIT Lite board employs two PSD4256G6V flash
general-purpose IO devices from STMicroelectronics. These devices not
only have flash memory but also extra IO pins, which are memory
mapped.
Example code is provided in the EZ-KIT Lite installation directory to
demonstrate how to program the flash memory as well as to demonstrate
the functionality of the general-purpose IO pins.
Flash Memory Map

Each device includes the following memory segments:
• 1M byte of primary flash memory
• 64K bytes of secondary flash memory
• 32 Kbytes of internal SRAM
• 256 Bytes of configuration registers (IO control)
Access to each segment can be 8-bit or 16-bit. The processor’s ~AMS0,
~AMS1, and ~AMS2 memory select pin are used for that purpose. Asynchro-
nous memory bank 0 is always enabled after a hard reset, while banks 1
and 2 need to be enabled by software. Table 1-3 provides an example on
asynchronous memory configuration registers.

Table 1-3. Asynchronous Memory Control Registers Settings Example

Register Value Function
EBIU_AMBCTL0 0x7BB07BB0 Timing control for banks 1 and 0
EBIU_AMBCTL1 bits 15-0 0x7BB0 Timing control for bank 2 (bank 3 is not used)
EBIU_AMGCTL bits 3-0 0xF Enable all banks
Each flash chip is initially configured with the memory sectors mapped
into the processor’s address space shown in Table 1-4.
Table 1-4. Flash Memory Map

Start Address End Address Content
0x2000 0000 0x200F FFFF Flash A primary (1MB)
0x2010 0000 0x201F FFFF Flash B primary (1MB)
0x2020 0000 0x2020 FFFF Flash A secondary (64KB)
0x2024 0000 0x2024 7FFF Flash A SRAM (32KB)
0x2027 0000 0x2027 00FF Flash A registers (256 Bytes)
0x2028 0000 0x2028 FFFF Flash B secondary (64KB)
0x202C 0000 0x202C 7FFF Flash B SRAM (32KB)
0x202E 0000 0x202E 00FF Flash B registers (256 Bytes)
All other locations Reserved

Flash Memory
Flash General-Purpose IO
This section describes general-purpose IO signals that are controlled by
means of setting appropriate registers of the flash A or flash B. These reg-
isters are mapped into the processor’s address space, as shown in
Table 1-4.
Flash device IO pins are arranged as 8-bit ports labeled A through G. There
is a set of 8-bit registers associated with each port. These registers are
Direction, Data In, and Data Out. Note that the Direction and Data Out
registers are cleared to all zeros at power-up or hardware reset.
The Direction register controls IO pins direction. When a bit is 0, a cor-
responding pin functions as an input. When the bit is 1, a corresponding
pin is an output. This is a 8-bit read-write register.
The Data In register allows reading the status of port’s pins. This is a 8-bit
read-only register.
The Data Out register allows clearing an output pin to 0 or setting it to 1.
This is a 8-bit read-write register.
The ADSP-BF533 EZ-KIT Lite board employs only flash A and flash B
ports A and B. Table 1-5 and Table 1-6 provide configuration register
addresses for flash A and flash B, respectively (only ports A and B are
listed). The following bits connect to the expansion board connector.
• Flash A: port A bits 7 and 6, as well as port B bits 7 and 6
• Flash B: port A bits 7–0
Table 1-5. Flash A Configuration Registers for Ports A and B

Register Name Port A Address Port B Address
Data In (read-only) 0x2027 0000 0x2027 0001
Data Out (read-write) 0x2027 0004 0x2027 0005
Direction (read-write) 0x2027 0006 0x2027 0007

Table 1-6. Flash B Configuration Registers for Ports A and B

Register Name Port A Address Port B Address
Data In (read-only) 0x202E 0000 0x202E 0001
Data Out (read-write) 0x202E 0004 0x202E 0005
Direction (read-write) 0x202E 0006 0x202E 0007
Table 1-7 and Table 1-8 depict the IO assignments.
Table 1-7. Flash A Port A Controls

Bit Number User IO Bit Value
7 Not defined Any
6 Not defined Any
5 PPI clock select bit 1 00 = local OSC (27 MHz)
4 PPI clock select bit 0 01= video decoder pixel clock

1X = expansion board PPI clock
3 Video decoder reset 0= reset ON; 1= reset OFF
2 Video encoder reset 0= reset ON; 1= reset OFF
1 Reserved Any
0 Codec reset 0= reset ON; 1= reset OFF
Table 1-8. Flash A Port B Controls

7 Not used Any
6 Not used Any
5 LED9 0= LED OFF; 1= LED ON

Flash Memory
Table 1-8. Flash A Port B Controls (Cont’d)

Configuring Flash Memory

The flash memory is completely configurable. Use PSDsoft Express™ to
modify the default settings of each flash memory. After the project has
been modified, the flash memory must be re-programmed using
FlashLINK™. The default project file is provided in
…\Blackfin\Examples\ADSP-BF533 EZ-KIT Lite\PSD4256G_ConfigFiles
directory. Analog Devices does not provide any support for setting up the
PSD4256G6V with PSDsoft Express or programming it using
FlashLINK. Email STMicroelectronics at apps.psd@st.com for technical
assistance.
The PSD4256G6Vcan be re-programmed using the FlashLINK JTAG
programming cable available from STMicoreclectronics (www.st.com/psd)
for approximately $59. FlashLINK plugs into any PC parallel port. The
PSDsoft Express development software is required to modify the
DSM2150 configuration and to operate the FlashLINK cable. PSDsoft
Express can be downloaded at no charge from www.st.com/psd.

LEDs and Push Buttons

The EZ-KIT Lite provides four push buttons and six LEDs for gen-
eral-purpose IO.
The six LEDs, labeled LED4 through LED9, are accessed via some of the
general-purpose IO pins of the flash memory interface. For information
on how to program the pins, see “Flash General-Purpose IO” on
page 1-12.
The four general-purpose push button are labeled SW4 through SW7. A sta-
tus of each individual button can be read through programmable flag (PF)
inputs, PF8 through PF11. A PF reads 1 when a corresponding switch is
being pressed-on. When the switch is released, the PF reads 0. A connec-
tion between the push button and PF input is established through the SW9
DIP switch. See “Push Button Enable Switch (SW9)” on page 2-12 for
details.
An example program is included in the EZ-KIT Lite installation directory
to demonstrate the functionality of the LEDs and push buttons.
Audio Interface
The AD1836 audio codec provides three channels of stereo audio output
and two channels of multichannel 96 kHz input. The SPORT0 interface of
the processor links with the stereo audio data input and output pins of the
AD1836 codec. The processor is capable of transferring data to the audio
codec in time-division multiplexed (TDM) or two-wire interface (TWI)
mode.
The TWI mode allows the codec to operate at a 96 kHz sample rate but
limits the output channels to two. The TDM mode can operate at a maxi-
mum of 48 kHz sample rate but allows simultaneous use of all input and
output channels. When using TWI mode, the TSCLK0 and RSCLK0 pins, as
well as the TFS0 and RFS0 pins of the processor, must be tied together

Video Interface
external to the processor. This is accomplished with the SW9 DIP switch
(see “Push Button Enable Switch (SW9)” on page 2-12 for more
information).
The AD1836 audio codec’s internal configuration registers are configured
using the SPI port of the processor. The processor’s PF4 programmable
flag pin is used as the select for this device. For information on how to
configure the multichannel codec, go to
www.analog.com/UploadedFiles/Datasheets/344740003AD1836_prc.pdf.
The general-purpose IO pin PA0 of flash A is a source for the AD1836

codec reset. See “Flash General-Purpose IO” on page 1-12 for more infor-
mation about the pin.
Example programs are included in the EZ-KIT Lite installation directory
to demonstrate AD1836 codec capabilities.
Video Interface
The board supports video input and output applications. The ADV7171
video encoder provides up to three output channels of analog video, while
the ADV7183 video decoder provides up to three input channels of analog
video. Both the encoder and the decoder connect to the parallel peripheral
interface (PPI) of the processor. For additional information on the video
interface hardware, refer to “PPI Interface” on page 2-5.
For the video interface to be operational, the following basic steps must be
performed.
1. Configure the SW3 DIP switch as required by the application. Refer
to “Video Configuration Switch (SW3)” on page 2-11 for details.
2. Remove reset to the video device. Refer to “Flash General-Purpose
IO” on page 1-12 for details.

3. If using the decoder:

D Enable device by driving programmable flag output PF2
to 0.
D Select PPI clock (see Table 1-7 on page 1-13).
4. Program internal registers of the video device in use. Both video
encoder and decoder use a two-wire serial interface to access inter-
nal registers. A programmable flag PF0 functions as a serial clock
(SCL), and PF1 functions as a serial data (SDAT).
5. Program the processor’s PPI interface (configuration registers,
DMA, etc.).
Example programs are included in the EZ-KIT Lite installation directory
to demonstrate the capabilities of the video interface.
Example Programs
Example programs are provided with the ADSP-BF533 EZ-KIT Lite to
demonstrate various capabilities of the evaluation board. These programs
are installed with the EZ-KIT Lite software and can be found in the
…\Blackfin\Examples\ADSP-BF533 EZ-KIT Lite subdirectory of the Visu-
alDSP++ installation directory. Please refer to the readme file provided
with each example for more information.
Background Telemetry Channel

The ADSP-BF533 USB debug agent supports the background telemetry
channel (BTC), which facilitates data exchange between VisualDSP++ and
the processor without interrupting processor execution.

Background Telemetry Channel
The BTC allows you to view a variable as it is updated or changed, all

while the processor continues to execute. For increased performance of the
BTC, including faster reading and writing, please check our latest line of
processor emulators at http://www.analog.com/proces-
sors/resources/crosscore/emulators/index.html. For more
information about the background telemetry channel, see the Visu-
alDSP++ User’s Guide or online Help.

2 ADSP-BF533 EZ-KIT LITE
HARDWARE REFERENCE
This chapter describes the hardware design of the ADSP-BF533 EZ-KIT

Lite board. The following topics are covered.
• “System Architecture” on page 2-2
Describes the configuration of the ADSP-BF533 EZ-KIT Lite
board and explains how the board components interface with the
processor.
• “Jumper and Switch Settings” on page 2-10
Shows the location and describes the function of the configuration
jumpers and switches.
• “LEDs and Push Buttons” on page 2-13
Shows the location and describes the function of the LEDs and
push buttons.
• “Connectors” on page 2-17
Shows the location and gives the part number for all of the connec-
tors on the board. Also, the manufacturer and part number
information is given for the mating parts.

System Architecture
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board.
64 MB 2 MB
SDRAM Flash LEDs (6)
(32M x 16-bit) (1M x 8-bit x 2-chips)
EBIU
JTAG Port
JTAG Header
ADSP-BF533 Expansion
Connectors
32.768 KHz (3)
Oscillator
RTC
DSP
27 MHz
Oscillator
UART SPORT1 SPI SPORT0 PPI/PFs PBs (4)
SPORT0
A5V 3.3V
Connector
ADV7183 ADV7171
+7.5V
Power ADM3202 AD1836

Video Video
Regulation RS-232 Codec
Decoder Encoder
TX/RX
Stereo
Stereo In Video In Video Out
RS-232 Out
Phono Phono Phono
Male Phono
Jacks (4) Jacks (3) Jacks (3)
Jacks (6)
Figure 2-1. System Architecture
This EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-BF533 Blackfin processor. The processor has an IO voltage of
3.3V. The core voltage is derived from this 3.3V supply and uses the inter-
nal regulator of the processor. The core voltage and the core clock rate can
be set up on the fly by the processor. Refer to the ADSP-BF533 Blackfin
Processor Hardware Reference for more information.

ADSP-BF533 EZ-KIT Lite Hardware Reference
The default boot mode for the processor is flash boot. See “Boot Mode
Switch (SW11)” on page 2-11 for information about changing the default.
External Bus Interface Unit

The external bus interface unit (EBIU) connects an external memory to
the ADSP-BF533 processor. The EBIU includes a 16-bit wide data bus,
an address bus, and a control bus. Both 16-bit and 8-bit access are sup-
ported. On the EZ-KIT Lite, the EBI unit connects to SDRAM and flash
memory.
64 MB (32M x 16 bits) of SDRAM connect to the synchronous memory
select 0 (~SMS0) pin. Refer to “SDRAM Interface” on page 1-9 for infor-
mation about SDRAM configuration. Note that SDRAM’s clock is the
processor’s clock out (CLK OUT), which frequency should not exceed
133 MHz.
Two flash memory devices connect to the asynchronous memory select
signals, ~AMS2 through ~AMS0. The devices provide a total of 2 Mbytes of
primary flash memory, 128 Kbytes of secondary flash memory, and
64 Kbytes of SRAM. The processor can use this memory for both booting
and storing information during normal operation. Refer to “Flash Mem-
ory” on page 1-10 for details.
All of the address, data, and control signals are available externally via the
extender connectors (J1–3). The pinout of the connectors can be found in
“ADSP-BF533 EZ-KIT Lite Schematic” on page B-1.
SPORT Audio Interface

The SPORT0 connects to the AD1836 audio codec and the expansion inter-
face. The AD1836 codec uses both the primary and secondary data
transmit and receive pins to input and output data from the audio inputs
and outputs.

System Architecture
The SPORT1 connects to the SPORT connector (P3) and the expansion
interface.
The pinout of the SPORT connector and the expansion interface connec-
tors can be found in “ADSP-BF533 EZ-KIT Lite Schematic” on page B-1.
SPI Interface
The serial peripheral interface (SPI) of the ADSP-BF533 processor con-
nects to the AD1836 audio codec and the expansion interface. The SPI
connection to the AD1836 is used to access the control registers of the
device. The PF4 flag of the processor is used as the devices select for the
SPI port.
The SPI signals are available on the expansion interface and on the SPI
connector (P6). The interface pinout can be found in “ADSP-BF533
EZ-KIT Lite Schematic” on page B-1.
Programmable Flags
The processor has 15 programmable flag pins (PFs). The pins are
multi-functional and depend on the processor setup. Table 2-1 is a sum-
mary of the programmable flag pins used on the EZ-KIT Lite.
Table 2-1. Programmable Flag Connections

Processor PF Pin Other Processor Function EZ-KIT Lite Function
PF0 SPI Slave Select Serial clock for programming ADV7171 and
ADV7183
PF1 SPI Select 1, Timer CLK Serial data for programming ADV7171 and
ADV7183
PF2 SPI Select 2 ADV7183 ~OE signal
PF3 SPI Select 3, FS3 ADV7183 FIELD pin. See “Video Configura-
tion Switch (SW3)” on page 2-11.

Table 2-1. Programmable Flag Connections (Cont’d)

Processor PF Pin Other Processor Function EZ-KIT Lite Function
PF4 SPI Select 4, PPI15 AD1836 SPI select
PF5 SPI Select 5, PPI14
PF8 PPI11 Push button (SW4). See “LEDs and Push But-
tons” on page 1-15 and “Push Button Enable
Switch (SW9)” on page 2-12 for information
on how to disable the push button.
PF12 PPI7 ADV7171 and ADV7183 data (MSB)
PF13 PPI6 ADV7171 and ADV7183 data

PPI Interface
The parallel peripheral interface (PPI) of the ADSP-BF533 processor is a
half-duplex, bi-directional port that can accommodate up to 16 bits of
data. The interface has a dedicated input clock (27 MHz), three multi-
plexed frame sync signals, and four bits of dedicated data. The remaining

System Architecture
data bits come from the re-configured programmable flag pins. For infor-
mation about the PFs multiplexed with the PPI pins, see “Programmable
Flags” on page 2-4. For information about the processor’s PPI interface,
refer to the ADSP-BF533 Blackfin Processor Hardware Reference.
Table 2-2 is a summary of the PPI pins used on the EZ-KIT Lite.
Table 2-2. PPI Connections

Processor PPI Pin Other Processor Function EZ-KIT Lite Function
PPI7 PF12 ADV7171 and ADV7183 data (MSB)
PPI6 PF13 ADV7171 and ADV7183 data
PPI3 ADV7171 and ADV7183 data
PF3 FS3 ADV7183 FIELD pin. For more information,

see “Video Configuration Switch (SW3)” on
page 2-11.
TMR1 PPI_HSYNC ADV7171 and ADV7183 HSYNC. For more
information, see “Video Configuration
Switch (SW3)” on page 2-11.
TMR2 PPI_FSYNC ADV7171 and ADV7183 VSYNC. For more
information, see “Video Configuration
Switch (SW3)” on page 2-11.
PPI_CLK Input from either the ADV7183 output clock
or the same 27 MHz oscillator driving the
processor. For more information, see “Video
Interface” on page 1-16.

The ADSP-BF533 EZ-KIT Lite board employs 8-bit PPI interface for
video output and video input.
Video Output Mode

In the video output mode, the PPI interface is configured as output and
connects to the on-board video encoder device, ADV7171. The
ADV7171 encoder generates three analog video channels on DAC B, DAC C,
and DAC D outputs. The PPI data connects to P7–0 of the encoder’s pixel
inputs. The encoder’s PPI input clock runs at 27 MHz, in phase with
CLK IN of the processor.
The encoder’s synchronization signals, HSYNC and VSYNC, can be config-

ured as inputs or outputs. Video blanking control signal is at level 1. The
HSYNC and VSYNC signals can connect the multiplexed sync pins of the pro-
cessor and the on-board ADV7183 video decoder via the SW3 switch, as
described in “Video Configuration Switch (SW3)” on page 2-11.
Video Input Mode

In the video input mode, the PPI interface is configured as input and con-
nects to the on-board video decoder device, ADV7183. The ADV7183
decoder receives three analog video channels on AIN1, AIN4, and AIN5
input. The decoder’s pixel data outputs P15–8 drive the PPI data (PPI3–0
and PF15–12). The decoder’s 27 MHz pixel clock output can be selected to
drive PPI clock, as shown in Table 1-7 on page 1-13.
Synchronization outputs of the decoder, HS/HACTIVE, VS/VACTIVE, and
FIELD, can connect the multiplexed sync pins of the ADSP-BF533 proces-
sor and the ADV7171 on-board video encoder via the SW3 DIP switch, as
described in “Video Configuration Switch (SW3)” on page 2-11.

System Architecture
UART Port
The universal asynchronous receiver/transmitter (UART) port of the pro-
cessor connects to the ADM3202 RS-232 line driver, as well as to the
expansion interface. The RS-232 line driver connects to the DB9 male
connector, providing an interface to a personal computer and other serial
devices.
Expansion Interface
The expansion interface consists of three 90-pin connectors. Table 2-3 on
page 2-8 shows the interfaces each connector provides. For the exact
pinout of the connectors, refer to “ADSP-BF533 EZ-KIT Lite Schematic”
on page B-1. The mechanical dimensions of the connectors can be found
on page 2-17.
Table 2-3. Expansion Connector Interfaces

Connector Interfaces
J1 5V, GND, address, data, PPI
J2 3.3V, GND, SPI, NMI, TMR2–0, SPORT0, SPORT1, PF15–0, EBIU control signals
J3 5V, 3.3V, GND, UART, flash IO, reset, video control signals
Limits to the current and to the interface speed must be taken into consid-
eration when using the expansion interface. The maximum current limit is
dependent on the capabilities of the used regulator. Additional circuitry
can also add extra loading to signals, decreasing their maximum effective
speed.
[ Analog Devices does not support and is not responsible for the
effects of additional circuitry.

JTAG Emulation Port

The JTAG emulation port allows an emulator to access the processor’s
internal and external memory through a 6-pin interface. The JTAG emu-
lation port of the processor also connects to the USB debugging interface.
When an emulator connects to the board at ZP4, the USB debugging
interface is disabled. See “JTAG (ZP4)” on page 2-21 for more informa-
tion about the JTAG connector.
To learn more about available emulators, contact Analog Devices (see
“Product Information”).

Jumper and Switch Settings

This section describes the operation of the jumpers and switches. The
jumper and switch locations are shown in Figure 2-2.
Figure 2-2. Jumper and Switch Locations
UART Loop Jumper (JP4)

The UART loop jumper (JP4) allows the loop back connection of transmit
and receive signals. The default is the OFF position.

Boot Mode Switch (SW11)

Positions 1 and 2 of SW11 set the boot mode of the processor as described
in Table 2-4.
Table 2-4. Boot Mode Switch (SW11)

Position 1 BMODE0 Position 2 BMODE1 Boot Mode
ON ON 16-bit external memory
OFF 1 ON Flash memory
ON OFF SPI host slave
OFF OFF SPI EEPROM
1 Default settings
Test DIP Switches (SW1 and SW2)

Two DIP switches (SW1 and SW2) are located on the bottom of the board.
The switches are used only for testing and should be in the OFF position.
Video Configuration Switch (SW3)

The video configuration switch (SW3) controls how some video signals
from the ADV7183 video decoder and ADV7171 video encoder are
routed to the processor’s PPI. The switch also determines if the PF2 pin
controls the ~OE signal of the ADV7183 video decoder outputs. Table 2-5
shows which processor’s signals connect to the encoder and decoder in the
default (ON) position.
Positions 1 thorough 5 of SW3 determine how and if the VSYNC, HSYNC, and
FIELD control signals are routed to the processor’s PPI. In standard config-
uration of the encoder and decoder, this is not necessary because the
processor is capable of reading the control information embedded in the
data stream.

Table 2-5. Video Configuration Switch (SW3)

Switch Position (Default) Processor Signal Video Signal
1 (OFF) TMR1 (HSYNC) HSYNC (ADV7171)
2 (OFF) TMR1 (HSYNC) HS (ADV7183)
3 (OFF) TMR2 (VSYNC) VS (ADV7183)
4 (OFF) TMR2 (VSYNC) VSYNC (ADV7171)
5 (OFF) PF3 (FIELD) FIELD (ADV7183)
6 (ON) PF2 ~OE (ADV7183)
Position 6 of SW3 determines whether PF2 connects to the ~OE signal of the
ADV7183. When the switch is OFF, PF2 can be used for other operations,
and the decoder output enable is held high with a pull-up resistor.
Push Button Enable Switch (SW9)

The push button enable (SW9) switch positions 1 through 4 disconnect the
drivers associated with the push buttons from the PF pins of the processor.
Positions 5 and 6 are used to connect the transmit and receive frame syncs
and clocks of SPORT0. This is important when the AD1836 audio codec
and the processor are communicating in I2S mode. Table 2-6 shows which
PF is driven when the switch is in the default (ON) position.
Table 2-6. Push Button Enable Switch (SW9)
Switch Position Default Setting Pin # Signal (Side 1) Pin # Signal (Side 2)
1 ON 1 SW4 12 PF8
2 ON 2 SW5 11 PF9
3 ON 3 SW6 10 PF10
4 ON 4 SW7 9 PF11
5 OFF 5 TFS0 8 RFS0
6 OFF 6 RSCLK0 7 TSCLK0

SPIS1/SPISS Select Switch (SW10)

The SPIS1/SPISS select switch (SW10) disconnects the SPIS1 and SPISS sig-
nals from the board, making them available on the SPI connector (P6).
The default is the ON position.
SPORT0 Switch (SW12)

When is set to OFF, SW12 disconnects SPORT0 from the audio codec. The
switch is used when SPORT0 signals are desired at the expansion interface.
The default is the ON position.

This section describes the functionality of the LEDs and push buttons.
Figure 2-3 shows the locations of the LEDs and push buttons.
Programmable Flag Push Buttons (SW4–7)

Four push buttons, SW4–7, are provided for general-purpose user input.
The buttons connect to the processor’s programmable flag pins PF8–11.
The push buttons are active high and, when pressed, send a high (1) to the
processor. Refer to “LEDs and Push Buttons” on page 1-15 for informa-
tion on PFs programming. The push button enable switch (SW9) is capable
of disconnecting the push buttons from the PFs (refer to “Push Button
Enable Switch (SW9)” on page 2-12 for more information). The pro-
grammable flag pins and their corresponding push buttons are shown in
Table 2-7.

Figure 2-3. LED and Push Button Locations
Table 2-7. Programmable Flag Switches

Processor Programmable Flag Pin Push Button Reference Designator
PF8 SW4
PF9 SW5
PF10 SW6
PF11 SW7

Reset Push Button (SW8)

The RESET push button resets all of the ICs on the board. One exception is
the USB interface chip (U34). The chip is not being reset when the push
button is pressed after the USB cable has been plugged in, and communi-
cation has been correctly initialized with the PC. After USB
communication has been initialized, the only way to reset the USB is by
powering down the board.
Power LED (LED1)

When LED1 is lit (green), it indicates that power is being supplied to the
board properly.
Reset LED (LED2)

When LED2 is lit, it indicates that the master reset of all the major ICs is
active.
User LEDs (LED4–9)

Six LEDs connect to six general-purpose IO pins of the flash memory
(U5). The LEDs are active high and are lit by writing a 1 to the correct
memory address in the flash memory. Refer to “LEDs and Push Buttons”
on page 1-15 for information on how to use the flash when programming
the LEDs.
Table 2-8. User LEDs

LED Reference Designator Flash Port Name
LED4 PB0
LED5 PB1
LED6 PB2

Table 2-8. User LEDs (Cont’d)

LED Reference Designator Flash Port Name
LED7 PB3
LED8 PB4
LED9 PB5
USB Monitor LED (ZLED3)

The USB monitor LED (ZLED3) indicates that USB communication has
been initialized successfully and you can connect to the processor using a
VisualDSP++ EZ-KIT Lite session. This should take approximately 15
seconds. If the LED does not light, try cycling power on the board and/or
reinstalling the USB driver.
L When VisualDSP++ is actively communicating with the EZ-KIT

Lite target board, the LED can flicker, indicating communications
handshake.

Connectors
This section describes the connector functionality and provides informa-
tion about mating connectors. The connector locations are shown in
Figure 2-4.
Figure 2-4. Connector Locations
Expansion Interface (J1–3)

Three board-to-board connector footprints provide signals for most of the
processor’s peripheral interfaces. The connectors are located at the bottom
of the board. For more information about the expansion interface, see
“Expansion Interface” on page 2-8. For the availability and pricing of the
J1, J2, and J3 connectors, contact Samtec.

Connectors
Part Description Manufacturer Part Number
90-position 0.05” spacing, SAMTEC SFC-145-T2-F-D-A

SMT (J1, J2, J3)
Mating Connectors
90-position 0.05” spacing SAMTEC TFM-145-x1 series

(through hole)
90-position 0.05” spacing SAMTEC TFM-145-x2 series

(surface mount)
90-position 0.05” spacing SAMTEC TFC-145 series

(low cost)
Audio (J4 and J5)
2x2 RCA jacks (J5) SWITCHCRAFT PJRAS2X2S01
Mating Connector
Two channel RCA interconnect cable MONSTER CABLE BI100-1M
Video (J8)

Power (J9)
The power connector provides all of the power necessary to operate the
EZ-KIT Lite board. The following table shows the power connector
pinout.

2.5 mm power jack (J9) SWITCHCRAFT RAPC712
DIGI-KEY RAPC712X-ND
Mating Power Supply (shipped with EZ-KIT Lite)
7.5V power supply GLOBTEK TR9CC2000LCP-Y
The power connector supplies DC power to the EZ-KIT Lite board.

Table 2-9 shows the power supply specifications.
Table 2-9. Power Supply Specifications

Terminal Connection
Center pin +7.5 VDC@2amps
Outer ring GND
FlashLINK (P1)
The FlashLINK connector allows you to configure and program the
STMicroelectronics DSM2150 flash/PLD chip. See “Configuring Flash
Memory” on page 1-14 for more information about the FlashLINK
connector.

Right-angle 7X2 shrouded 0.1” FCI 68737-414HLF
spacing (P1)
Mating Assembly
FlashLINK JTAG programmer ST MICRO FL-101B

Connectors
RS-232 (P2)
The RS-232 compatible connector is described in Table 2-10.
Table 2-10. RS-232 Connector

DB9, male, right angle (P2) TYCO 5747250-4
Mating Assembly
2m female-to-female cable DIGI-KEY AE1016-ND
SPORT1 (P3)
The SPORT1 connector is linked to a 20-pin connector. The connector’s
pinout can be found in “ADSP-BF533 EZ-KIT Lite Schematic” on
page B-1. For the flash (U5) connector pricing and availability, contact
AMP.
20-pin IDC header FCI 68737-420HLF
Mating Connector
IDC socket DIGI-KEY S4210-ND

JTAG (ZP4)
The JTAG header is the connecting point for a JTAG in-circuit emulator
pod. When an emulator connects to the JTAG header, the USB debug
interface is disabled.
L Pin 3 is missing to provide keying. Pin 3 in the mating connector

should have a plug.
L When using an emulator with the EZ-KIT Lite board, follow the
connection instructions provided with the emulator.
14-pin IDC header FCI 68737-414HLF
SPI (P6)
The SPI connector is linked to a 12-pin connector. The connector’s
pinout can be found in “ADSP-BF533 EZ-KIT Lite Schematic” on
page B-1.
IDC header FCI 68737-412HLF
Mating Assembly
IDC socket DIGI-KEY S4207-ND

Connectors

A ADSP-BF533 EZ-KIT LITE BILL
OF MATERIALS
The bill of materials corresponds to “ADSP-BF533 EZ-KIT Lite Sche-

matic” on page B-1.
Ref. Qty. Description Reference Manufacturer Part Number

Designator
1 2 74LVC14A U10,U33 TI 74LVC14AD

SOIC14
2 1 IDT74FCT32 U31 IDT IDT74FCT3244APYG

44APY
SSOP20
3 1 IDT74FCT38 U4 IDT IDT74FCT3807AQG

07AQ
QSOP20
4 1 SN74AHC1G U9 TI SN74AHC1G00DBVR
00 SOT23-5
5 1 12.288MHZ U11 DIGI-KEY SG-8002CA-PCC-ND

OSC003 (12.288M)
6 1 SN74LVC1G1 U7 TI 74LVC1G125DBVRE4
25 SOT23-5
7 1 MT48LC32M U8 MICRON MT48LC32M16A2P-75

16A2TG-75
TSOP54
8 2 27MHZ U3,U36 DIGI-KEY SG-8002CA-PCC-ND

OSC003 (27.00M)
9 1 32.768KHZ U2 EPSON MC-156-32.7680KA-A0:

OSC008 ROHS
ADSP-BF533 EZ-KIT Lite Evaluation System Manual A-1

Designator
10 1 IDT2305-1D U46 IDT IDT2305-1DCG
C SOIC8
11 1 SN74LVC1G3 U21 TI SN74LVC1G32DBVRE4

2 SOT23-5
12 1 BF533 U5 ST MICRO PSD4256G6V-10UI

PSD4256G6V
“U5”
13 1 BF533 U6 ST MICRO BF533 PSD4256G6V

PSD4256G6V “U5”
“U6”
14 1 FDS9431A U32 FAIRCHILD FDS9431A

SOIC8
15 1 FDC658P U34 FAIRCHILD FDC658P

SOT23-6
16 1 ADM708SAR U29 ANALOG ADM708SARZ

Z SOIC8 DEVICES
17 1 ADP3338AKC VR1 ANALOG ADP3338AKCZ-3.3-RL

Z-33 SOT-223 DEVICES
18 1 ADP3339AKC VR5 ANALOG ADP3339AKCZ-5-R7

Z-5 SOT-223 DEVICES
19 1 ADP3339AKC VR3 ANALOG ADP3339AKCZ-3.3-R7

Z-33 SOT-223 DEVICES
20 2 ADP3336AR VR2,VR6 ANALOG ADP3336ARMZ-REEL
MZ MSOP8 DEVICES
21 1 ADV7171KSU U27 ANALOG ADV7171KSUZ

Z TQFP44 DEVICES
22 1 10MA D1 ANALOG AD1580BRTZ-REEL7

AD1580BRTZ DEVICES
SOT23D
23 2 ADG752BRT U25-26 ANALOG ADG752BRTZ-REEL

Z SOT23-6 DEVICES
A-2 ADSP-BF533 EZ-KIT Lite Evaluation System Manual

ADSP-BF533 EZ-KIT Lite Bill Of Materials

Designator
24 3 AD8061ARTZ U22-24 ANALOG AD8061ARTZ-R2
SOT23-5 DEVICES
25 1 ADM3202AR U30 ANALOG ADM3202ARNZ

NZ SOIC16 DEVICES
26 8 AD8606ARZ U12-13,U15-20 ANALOG AD8606ARZ

SOIC8 DEVICES
27 1 AD1836AASZ U14 ANALOG AD1836AASZ

MQFP52 DEVICES
28 1 ADV7183BKS U28 ANALOG ADV7183BKSTZ

TZ LQFP80 DEVICES
29 1 ADSP-BF533- U1 ANALOG ADSP-BF533SKBCZ600

600 DEVICES
MINIBGA160
30 1 ADP1864 VR4 ANALOG ADP1864AUJZ-R7

SOT23-6 DEVICES
31 5 RUBBER M1-5 MOUSER 517-SJ-5018BK

FOOT
32 1 PWR J9 SWITCH- RAPC712X

2.5MM_JACK CRAFT
CON005
33 1 RCA 2X2 J5 SWITCH- PJRAS2X2S01X

CON013 CRAFT
34 5 MOMEN- SW4-8 PANASONIC EVQ-PAD04M
TARY
SWT013
35 3 .05 45X2 J1-3 SAMTEC SFC-145-T2-F-D-A

CON019
36 4 DIP6 SWT017 SW1-3,SW9 CTS 218-6LPST
37 2 RCA 3X2 J4,J8 SWITCH- PJRAS3X2S01X

CON024 CRAFT
38 1 DIP4 SWT018 SW12 ITT TDA04HOSB1

Designator
39 2 DIP2 SWT020 SW10-11 C&K TDA02H0SB1
40 1 IDC 2X1 JP4 FCI 90726-402HLF

IDC2X1
41 2 IDC 7X2 P1,ZP4 FCI 68737-414HLF

IDC7X2
42 1 IDC 10X2 P3 FCI 68737-420HLF

IDC10X2
43 1 2.5A F1 RAYCHEM SMD250F-2

RESETABLE
FUS001
44 1 IDC SJ1 DIGI-KEY S9001-ND

2PIN_JUMPE
R_SHORT
45 1 DB9 9PIN P2 TYCO 5747250-4

DB9M
46 1 IDC 6X2 P6 FCI 68737-412HLF

IDC6X2
47 14 0 1/4W R27-30,R148,R157- KOA 0.0ECTRk7372BTTED

5% 1206 158,R167,R174-
175,R177-178,
R182,R193
48 6 YELLOW LED4-9 PANASONIC LN1461C

LED001
49 12 330PF 50V C13,C18,C23,C28, AVX 08055A331JAT

5% 0805 C33,C38,C67-70,
C73-74


Designator
50 42 0.01UF 100V C82,C85,C87, AVX 08051C103KAT2A
10% 0805 C108,C112-113,
C123-124,C126-
128,C136,C146-
147,C149-155,
C159,C161,C163,
C165-169,C171-
174,C181,C183,
C188,C190,C194,
C196,C201,C204,
C208
51 8 0.22UF 25V C129-130, AVX 08053C224FAT

10% 0805 C137-142
52 58 0.1UF 50V C2,C6,C8,C71-72, AVX 08055C104KAT

10% 0805 C75-81,C84,C86,
C88-95,C98-100,
C105,C109-111,
C119,C125,C132,
C143-145,C148,
C156-158,C175-
180,C182,C184-
187,C189,C191-
193,C195,C197,
C209-210
53 8 1000PF 50V C7,C9-11,C49-50, AVX 08055A102JAT2A

5% 0805 C52-53
54 6 10UF 16V CT13,CT21-25 AVX TAJC106K016R

10% C
55 32 10K 1/10W R1-2,R4,R10,R12- VISHAY CRCW080510K0JNEA

5% 0805 13,R15-16,R18,R26,
R32-33,R106-108,
R128,R138-139,
R142-143,R145,
R150-151,R153,
R156,R166,R172-
173,R192,R214,
R225,R232

Designator
56 10 33 1/10W R5-9,R31,R144, VISHAY CRCW080533R0JNEA
5% 0805 R179,R183,R224
57 1 4.7K 1/10W R17 VISHAY CRCW08054K70JNEA

5% 0805
58 1 1.5K 1/10W R140 VISHAY CRCW08051K50FKEA

5% 0805
59 1 1.2K 1/8W R129 VISHAY CRCW12061K20JNEA

5% 1206
60 6 49.9K 1/8W R38,R45,R54,R62, VISHAY CRCW120649K9FKEA

1% 1206 R70,R78
61 12 100PF 100V C15,C20,C25,C30, AVX 12061A101JAT2A

5% 1206 C35,C40,C46-48,
C51,C54,C56
62 1 2.2UF 35V CT27 AVX TAJB225K035R

10% B
63 5 10UF 16V CT1-2,CT14-16 AVX TAJB106K016R

10% B
64 4 100 1/10W R149,R152, VISHAY CRCW0805100RJNEA

5% 0805 R154-155
65 6 220PF 50V C16,C21,C26,C31, AVX 12061A221JAT2A
10% 1206 C36,C41
66 4 600 100MHZ FER14-17 DIGI-KEY 490-1014-2-ND

200MA 0603
67 3 2A S2A D2-4 VISHAY S2A-E3

DO-214AA
68 15 600 100MHZ FER1-4,FER8-13, STEWARD HZ1206B601R-10

500MA 1206 FER18-22
69 4 237.0 1/8W R93,R95,R97,R99 VISHAY CRCW1206237RFKEA

1% 1206
70 4 750.0K 1/8W R86,R90,R94,R96 VISHAY CRCW1206750KFKEA

1% 1206


Designator
71 16 5.76K 1/8W R82-85,R87-89, VISHAY CRCW12065K76FKEA
1% 1206 R91-92,R98,
R100-105

1% 1206 R66,R74
73 8 120PF 50V C42-45,C55,C57-59 AVX 12065A121JAT2A

5% 1206
74 1 1UF 16V C5 PANASONIC ECJ2FB1E105K

10% 0805
75 12 75 1/8W R113-114,R116- VISHAY CRCW120675R0JNEA

5% 1206 117,R120-121,
R123-124,R127,
R133-134,R137
76 1 68UF 6.3V CT28 AVX TAJD686K016R

20% D
77 1 340.0K 1/8W R185 VISHAY CRCW0805-3403FRT1E3

1% 0805
78 6 680PF 50V C14,C19,C24,C29, AVX 08055A681FAT2A

1% 0805 C34,C39
79 3 10UF 25V C198-200 PANASONIC ECJ4YF1E106Z

+80-20% 1210

1% 1206 R73,R81

1% 1206 R51,R56,R59,R64,
R67,R72,R75,R80

1% 1206 R68,R76

1% 1206 R69,R77
84 10 10UF 16V CT3-12 PANASONIC EEE1CA100SR

20% CAP002

Designator
85 1 4A SSB43L D6 VISHAY SSB43L
DO-214AA
86 1 10UH L12 TDK 445-2014-1-ND

20% IND001
87 2 10K 50MW RN1-2 CTS RT230B7TR7

5% BGA36
88 25 0 1/10W R3,R19,R21-25, VISHAY CRCW08050000Z0EA

5% 0805 R110-111,R132,
R135-136,R141,
R169,R186-188,
R194,R210-211,
R222,R226-228,
R231
89 1 190 100MHZ FER23 MURATA DLW5BSN191SQ2

5A FER002
90 1 3.32K 1/10W R223 PANASONIC ERJ-6ENF3321V

1% 0805
91 4 22 1/10W R14,R109,R180-181 VISHAY CRCW080522R0JNEA

5% 0805
92 6 0.68UH L4-9 MURATA LQM21NNR68K10D
10% 0805
93 1 .082UF 50V C83 AVX 08055C823JAT2A

5% 0805
94 1 1A ZHCS1000 D5 ZETEX ZHCS1000TA pb-free
SOT23-312
95 3 2.2UH L1-3 DIGI-KEY 490-1119-2-ND

10% 0805
96 6 1UF 10V C4,C60-61, AVX 0805ZC105KAT2A

10% 0805 C102-104
97 2 18PF 50V C1,C3 AVX 08055A180JAT2A

5% 0805


Designator
98 1 10M 1/8W R20 VISHAY CRCW080510M0JMEA
5% 0805

1% 0805

1% 1206
101 1 147.0K 1/10W R191 VISHAY CRCW1206147KFKEA

1% 1206
102 1 68PF 50V C64 AVX 06035A680JAT2A

5% 0603
103 1 470PF 50V C63 AVX 06033A471JAT2A

5% 0603
104 1 0 1/10W R159 PHYCOMP 232270296001L

5% 0603
105 1 24.9K 1/10W R11 DIGI-KEY 311-24.9KHTR-ND

1% 0603
106 1 47UF 6.3V CT26 PANASONIC EEE0JA470WR

10% B
107 1 0.05 1/2W R165 SUSUMU PRL1632-R051-F-T1

1% 1206
108 1 10UF 16V C65 AVX 1210YD106KAT2A

10% 1210
109 1 680 1/8W R163 VISHAY CRCW1206680RFNEA

5% 1206
110 1 150.0 1/8W R122 VISHAY CRCW1206150RFKEA

1% 1206
111 1 GREEN LED1 PANASONIC LN1361CTR

LED001
112 1 RED LED001 LED2 PANASONIC LN1261CTR
113 2 1000PF 50V C96-97 AVX 12065A102JAT2A

5% 1206

Designator
114 6 2200PF 50V C12,C17,C22,C27, AVX 12065A222JAT050
5% 1206 C32,C37
115 6 1K 1/8W R115,R118-119, VISHAY CRCW12061K00FNEA

5% 1206 R125-126,R131
116 3 100K 1/8W R112,R130,R176 VISHAY CRCW1206100KFKEA

5% 1206
117 7 270 1/8W R146-147,R160- VISHAY CRCW1206270RJNEA

5% 1206 162,R164,R168
118 6 604.0 1/8W R39,R46,R55,R63, PANASONIC ERJ-8ENF6040V

1% 1206 R71,R79
119 4 1UF 25V CT17-20 AVX TAJA105K020R

20% A
120 1 255.0K 1/10W R171 VISHAY CRCW06032553FK

1% 0603
121 1 80.6K 1/10W R170 DIGI-KEY 311-80.6KHRCT-ND

1% 0603
122 1 6.8UH 25% L10 DIGI-KEY 308-1328-1-ND

IND009

A B C D
1 1
2 2
ADSP-BF533 EZ-KIT Lite
3 3
ANALOG 20 Cotton Road

Nashua, NH 03063
4 DEVICES PH: 1-800-ANALOGD 4
Title ADSP-BF533 EZ-KIT LITE

TITLE
Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 1 of 12
A B C D
A B C D
3.3V 3.3V R5
33
0805
ADV7183_27MHZ_CLK
U4
R6
3 33
O1 0805
5
R225 R1 O2 ADV7171_27MHZ_CLK
10K 10K 7 R7 3.3V
0805 0805 O3 33
9 0805
O4 DNP
1 11
R179 IN O5
U3 33 12
0805 O6 R8
1 3 14 33 R180
OE OUT O7 0805 U46 22
16 0805
1 27MHZ
OSC003
O8
O9
18 R9
PPI_27MHZ_CLK
CLK_OUT
1
REF CLKOUT
8
CLK_OUT_EXP1
RTXI RTC RTXO
1
33 3
19 0805 CLK1
O10 2 R181
DSP_CLK CLK2 22 R20
IDT74FCT3807AQ R19 6 5 0805 10M
QSOP20 0 VDD CLK3 0805
0805 4 7 CLK_OUT_EXP2
DNP GND CLK4 R109
Not populated in standard EZ-KIT Configuration. 22
Can be used to provide DSP clock frequency EXT_DSP_CLK IDT2305-1DC 0805
other than that of the Video Interface. R224 SOIC8 DNP U2
33
U36 0805 1 4
DNP TERM1 TERM2
1 3 2 3
OE OUT NC1 NC2
27MHZ C1 32.768KHZ C3
OSC003 18PF OSC008 18PF
DNP 0805 0805
SW10: Disconnects SPI signals when OFF

DEFAULT = ON
U1 U1
A[1:19] D[0:15] SW10
A1 J14 M9 D0 L1 D2 SPISS 1 4 PF0 PF[0:15]
ON
A1 D0 RSCLK0 RSCLK0 PF0/~SPISS
1
A2 K14 N9 D1 J3 C1 SPIS1 2 3 PF1
A2 D1 RFS0 RFS0 PF1/SPISEL1/TMRCLK
2
A3 L14 P9 D2 K1 C2 DIP2 SWT020 PF2
A3 D2 DR0PRI DR0PRI PF2/SPISEL2
A4 J13 M8 D3 J2 C3 PF3
A4 D3 DR0SEC DR0SEC PF3/SPISEL3/PPI_FS3
A5 K13 N8 D4 J1 B1 PF4
2 A5 D4 TSCLK0 TSCLK0 PF4/SPISEL4/PPI15 2
A6 L13 P8 D5 H3 B2 PF5
A6 D5 TFS0 TFS0 PF5/SPISEL5/PPI14
A7 K12 M7 D6 H1 B3 PF6
A7 D6 DT0PRI DT0PRI PF6/SPISEL6/PPI13
A8 L12 N7 D7 H2 B4 PF7
A8 D7 DT0SEC DT0SEC PF7/SPISEL7/PPI12
A9 M12 P7 D8 A2 PF8
A9 D8 PF8/PPI11
A10 M13 M6 D9 G1 A3 PF9
A10 D9 RSCLK1 RSCLK1 PF9/PPI10
3.3V A11 M14 N6 D10 G2 A4 PF10
A11 D10 RFS1 RFS1 PF10/PPI9
A12 N14 P6 D11 G3 A5 PF11
A12 D11 DR1PRI DR1PRI PF11/PPI8
A13 N13 M5 D12 F3 B5 PF12
A13 D12 DR1SEC DR1SEC PF12/PPI7
A14 N12 N5 D13 F1 B6 PF13
A14 D13 TSCLK1 TSCLK1 PF13/PPI6 SW2: BOOT MODE SELECT
A15 M11 P5 D14 E1 A6 PF14 (Default : 1 = OFF, 2 = ON)
A15 D14 TFS1 TFS1 PF14/PPI5
A16 N11 P4 D15 F2 C6 PF15 BOOT MODE 1 2
A16 D15 DT1PRI DT1PRI PF15/PPI4
R4 R12 A17 P13 E3 Execute from 16-bit external ON ON
10K 10K A17 DT1SEC DT1SEC memory (bypass boot ROM)
0805 0805 A18 P12 E14 C8 PP0 PP[0:3]
A18 AMS0 AMS0 PP0 Boot from 8-bit or 16-bit flash OFF ON DEFAULT
A19 P11 F14 L3 B8 PP1
A19 AMS1 AMS1 RX RX PP1 Boot from SPI host slave mode ON OFF
F13 K3 A7 PP2
AMS2 AMS2 TX TX PP2 Boot from SPI serial EEPROM OFF OFF
E13 G12 B7 PP3 (8, 16 or 24-bit address range)
ARDY ARDY AMS3 AMS3 PP3
G13 D3
AOE AOE MOSI MOSI
G14 D13 E2 C9
ARE ARE SRAS SRAS MISO MISO PPI_CLK PPI_CLK 3.3V
H14 C14 D1
AWE AWE SCAS SCAS SCK SCK
D12 P2
SWE SWE R14 TCK TCK
3 H13 B13 22 L2 N3 3
~ABE0/SDQM0 ~ABE0/SDQM0 SCKE SCKE 0805 TMR0 TMR0 TDO TDO
H12 B14 M1 M3
~ABE1/SDQM1 ~ABE1/SDQM1 CLKOUT CLK_OUT TMR1 TMR1/PPI_FS1 TDI TDI
E12 K2 N2
SA10 SA10 TMR2 TMR2/PPI_FS2 TMS TMS
D14 C13 N1 R2 R10
BR BR SMS SMS TRST TRST 10K 10K
P10 A9 M2 0805 0805
BG BG RTXI RTXI EMU EMU
N10 A12 A8
BGH BGH CLKIN DSP_CLK RTXO RTXO SW11
A11 N4 1 4
ON
XTALO BMODE0
1
B10 P3 2 3
NMI NMI BMODE1
2
A13 DIP2
VROUT1 VROUT SWT020
C10 B12 C2
RESET RESET VROUT2 0.1UF R17
0805 ADSP-BF533-600 4.7K
DNP MINIBGA160 0805
R13 ADSP-BF533-600
10K MINIBGA160
0805

Nashua, NH 03063

DSP
Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 2 of 12
A B C D
A B C D
3.3V
3.3V
FlashLINK JTAG HEADER

3.3V
R26 RN1
10K
0805 B2 L2 RN2
COM1 COM4
P1 R22 A1 K1 B2 L2
1 2 0 PD0_A R1 R32 COM1 COM4
0805 A2 K2 A1 K1
3 4 PD1_A R2 R31 PB4_B R1 R32 PC5_B
FLASH_TDI FLASH_TDI_A A3 K3 A2 K2
5 6 R23 PD2_A R3 R30 PB5_B R2 R31 PA0_B
FLASH_TDI FLASH_TSTAT 0 B1 L1 A3 K3
U9 U33 PE7_A R4 R29 PB6_B R3 R30 PD2_B
7 8 FLASH_RESET_C 1 0805
FLASH_TMS 4 1 2 DNP B3 L3 B1 L1
1 FLASH_RESET R5 R28 FLASH_TMS PB3_B R4 R29 PC4_B 1
1
U7 9 10 2
RESET FLASH_TDI_B C1 M1 B3 L3
SN74AHC1G00 74LVC14A FLASH_TSTAT R6 R27 PC5_A PB7_B R5 R28 FLASH_TDO
4 2 FLASH_TCK_IN 11 12
FLASH_TCK SOT23-5 SOIC14
C2 M2 C1 M1
13 14 PE6_A R7 R26 PC4_A PB1_B R6 R27
SN74LVC1G125 FLASH_TERR R25 C3 M3 C2 M2
SOT23-5 IDC7X2 0 FLASH_TDI_A R8 R25 FLASH_TERR PB2_B R7 R26 FLASH_RESET_C
R21 0805 E2 H2 C3 M3
FLASH_TDO 0 COM2 COM3 PE6_B R8 R25 FLASH_TCK_IN
0805 D1 G1 E2 H2
DNP PB7_A R9 R24 PA6_A COM2 COM3
D2 G2 D1 G1
FLASH_TDO FLASH_TDO_A PB6_A R10 R23 PPICLK_ONBOARD_SELECT PD0_B R9 R24 PA4_B
LED6 D3 G3 D2 G2
R24 R11 R22 PA7_A PB0_B R10 R23 PA3_B
C125 C5 0 LED5 E1 H1 D3 G3
0.1UF 1UF 0805 R12 R21 PPICLK_AD7183_SELECT PE7_B R11 R22
0805 0805 LED4 E3 H3 E1 H1
FLASH_TDO_B R13 R20 ADV7183_RESET PD1_B R12 R21
LED2 F1 J1 E3 H3
R14 R19 ADV7171_RESET PA7_B R13 R20 PA2_B
LED3 F2 J2 F1 J1
R15 R18 AD1898_RESET PA6_B R14 R19 PA1_B
LED1 F3 J3 F2 J2
LED[6:1] R16 R17 AD1836_RESET PA5_B R15 R18
10K F3 J3
BGA36 R16 R17
10K
BGA36
FLASH A (1MB) FLASH B (1MB)

SDRAM 512Mb
512K x 16 512K x 16
(64MB - 32M x 16)
2 D[0:15] 2
A[1:19]
U5 U6 U8
3 31 D0 3 31 D0
~ABE0/SDQM0 AD0 PF0 ~ABE0/SDQM0 AD0 PF0 A1 23 2 D0
A1 4 32 D1 A1 4 32 D1 A0 DQ0
AD1 PF1 AD1 PF1 A2 24 4 D1
A2 5 33 D2 A2 5 33 D2 A1 DQ1
AD2 PF2 AD2 PF2 A3 25 5 D2
A3 6 34 D3 A3 6 34 D3 A2 DQ2
AD3 PF3 AD3 PF3 A4 26 7 D3
A4 7 35 D4 A4 7 35 D4 A3 DQ3
AD4 PF4 AD4 PF4 A5 29 8 D4
A5 10 36 D5 A5 10 36 D5 A4 DQ4
AD5 PF5 AD5 PF5 A6 30 10 D5
A6 11 37 D6 A6 11 37 D6 A5 DQ5
AD6 PF6 AD6 PF6 A7 31 11 D6
A7 12 38 D7 A7 12 38 D7 A6 DQ6
AD7 PF7 AD7 PF7 A8 32 13 D7
A8 13 A8 13 A7 DQ7
AD8 AD8 A9 33 42 D8
A9 14 21 D8 A9 14 21 D8 A8 DQ8
AD9 PG0 AD9 PG0 A10 34 44 D9
A10 15 22 D9 A10 15 22 D9 A9 DQ9
AD10 PG1 AD10 PG1 22 45 D10
A11 16 23 D10 A11 16 23 D10 SA10 A10 DQ10
AD11 PG2 AD11 PG2 A12 35 47 D11
A12 17 24 D11 A12 17 24 D11 A11 DQ11
AD12 PG3 AD12 PG3 A13 36 48 D12
A13 18 25 D12 A13 18 25 D12 A12_NC DQ12
AD13 PG4 AD13 PG4 50 D13
A14 19 26 D13 A14 19 26 D13 DQ13
AD14 PG5 AD14 PG5 A18 20 51 D14
A15 20 27 D14 A15 20 27 D14 BA0 DQ14
AD15 PG6 AD15 PG6 A19 21 53 D15
28 D15 28 D15 BA1 DQ15
PG7 PG7
3 A16 41 A16 41 3
PC0 PC0 16 19
A17 42 51 A17 42 51 SWE WE CS SMS
PC1 PA0 AD1836_RESET PC1 PA0 PA0_B 17 37
A18 43 52 A18 43 52 SCAS CAS CKE SCKE
PC2 PA1 AD1898_RESET PC2 PA1 PA1_B 18 38
A19 44 53 A19 44 53 SRAS RAS CLK CLK_OUT
PC3 PA2 ADV7171_RESET PC3 PA2 PA2_B
45 54 45 54
PC4_A PC4 PA3 ADV7183_RESET PC4_B PC4 PA3 PA3_B 15
46 55 46 55 ~ABE0/SDQM0 DQML
PC5_A PC5 PA4 PPICLK_AD7183_SELECT PC5_B PC5 PA4 PA4_B 39
47 56 47 56 ~ABE1/SDQM1 DQMH
AMS0 PC6 PA5 PPICLK_ONBOARD_SELECT AMS1 PC6 PA5 PA5_B
48 57 48 57
AMS2 PC7 PA6 PA6_A AMS2 PC7 PA6 PA6_B MT48LC32M16A2TG-75
58 58 TSOP54
PA7 PA7_A PA7 PA7_B
59 59
AWE CNTL0/~WR AWE CNTL0/~WR
60 61 LED1 60 61 External Memory Map
AOE CNTL1/~RD PB0 LED[6:1] AOE CNTL1/~RD PB0 PB0_B
40 62 LED2 40 62 Start Adress End Address Content
~ABE1/SDQM1 CNTL2 PB1 ~ABE1/SDQM1 CNTL2 PB1 PB1_B
63 LED3 63 0x0000 0000 0x07FF FFFF SDRAM Bank 0 (SDRAM)
PB2 PB2 PB2_B
71 64 LED4 71 64 0x2000 0000 0x200F FFFF ASYNC Memory Bank 0 (Primary Flash A)
FLASH_TMS PE0/TMS PB3 FLASH_TMS PE0/TMS PB3 PB3_B
72 65 LED5 72 65 0x2010 0000 0x201F FFFF ASYNC Memory Bank 1 (Primary Flash B)
FLASH_TCK PE1/TCK PB4 FLASH_TCK PE1/TCK PB4 PB4_B
73 66 LED6 73 66 0x2020 0000 0x202F FFFF ASYNC Memory Bank 2 (Flash A and B Secondary Memory, SRAM and Internal Registers)
FLASH_TDI_A PE2/TDI PB5 FLASH_TDI_B PE2/TDI PB5 PB5_B
74 67 74 67
FLASH_TDO_A PE3/TDO PB6 PB6_A FLASH_TDO_B PE3/TDO PB6 PB6_B
75 68 75 68
FLASH_TSTAT PE4/TSTAT PB7 PB7_A FLASH_TSTAT PE4/TSTAT PB7 PB7_B
76 76
FLASH_TERR
PE6_A
77
PE5/~TERR
PE6 PD0
79
PD0_A
FLASH_TERR
PE6_B
77
PE5/~TERR
PE6 PD0
79
PD0_B
Nashua, NH 03063
78 80 78 80
4 PE7_A PE7 PD1
PD2
1
PD1_A
PD2_A
R228
0
0805
PE7_B PE7 PD1
PD2
1
PD1_B
PD2_B
DEVICES PH: 1-800-ANALOGD 4
39 2 FLASH_B_RESET 39 2
FLASH_RESET RESET PD3 AWE FLASH_RESET RESET PD3 AWE
R231
PSD4256G6V 0 PSD4256G6V
TQFP80 0805
DNP
TQFP80
MEMORY
Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 3 of 12
A B C D
A B C D
3.3V
DAC3
DAC2
DAC1
ADC1
ADC2
R32
10K
0805
R31
U11 33
0805 LEFT (WHITE)
1 3
OE OUT AD1836_CLK
1 RIGHT (RED) 1
12.288MHZ
OSC003
R42 C20
5.49K 100PF
OUT (J4) IN (J5) 1206 1206
R48 R43
11.0K 3.32K
1206 1206
3.3V
OUT1R-
C18
330PF
U13
0805 6
5
R33 DAC1 RIGHT C19
AD8606ARZ
10K 680PF
SOIC8
0805 R49 0805 R44 R46
5.49K 1.65K 604.0
1206 1206 1206
CT3
J4
AUDIO CODEC OUT1R+ 10UF
CAP002
CON024
U14 DAC1_RIGHT 7
SW12
1 8 47 8
ON
DR0PRI ASDATA1 OUT1L+ OUT1L+

1
R47 C21
DR0SEC
2 7 48
ASDATA2 OUT1L-
9
OUT1L-
DAC1 LEFT 2.74K 220PF 9
2
1206 1206 C17 R45

3 6 44 2200PF 49.9K
RFS0 ALRCLK AD1836_VREF
3
1206 1206
4 5 43 31
RSCLK0 ABCLK OUT1R+ OUT1R+
4
2 DIP4
OUT1R-
30
OUT1R-
DAC1 RIGHT 2
SWT018
45
AD1836_CLK MCLK
6
OUT2L+ OUT2L+
PF4
50
CLATCH OUT2L-
7
OUT2L-
DAC2 LEFT
51
SCK CCLK AGND
2 33
MOSI CDATA OUT2R+ OUT2R+
MISO
49
COUT OUT2R-
32
OUT2R-
DAC2 RIGHT
16 4
R108 R107 R106 IN1L+ IN1L+ OUT3L+ OUT3L+
10K 10K 10K ADC1 LEFT IN1L- 17
IN1L- OUT3L-
5
OUT3L-
DAC3 LEFT R35 C15
0805 0805 0805 5.49K 100PF
1206 1206
18 35
IN1R+ IN1R+ OUT3R+ OUT3R+ R34 R36
ADC1 RIGHTIN1R- 19
IN1R- OUT3R-
34
OUT3R-
DAC3 RIGHT 11.0K 3.32K
1206 1206
OUT1L-
20 38
IN2L+/CL2/CL2 DSDATA1 DT0PRI
21 41 C13
IN2L-/CL1/CL1 DSDATA2 DT0SEC 330PF
U13
22 42 0805 2
IN2L1 NC/IN2L1/IN2L+ DSDATA3
ADC2 LEFT IN2L2
23
NC/IN2L2/IN2L- DLRCLK
36
TFS0
1
DBCLK
37
TSCLK0
DAC1 LEFT 3
R30 C14
AD8606ARZ
24 0 680PF
IN2R2 NC/IN2R2/IN2R- SOIC8
1206 R40 0805 R37 R39
ADC2 RIGHT IN2R1 25
NC/IN2R1/IN2R+ FILTR
13 5.49K 1.65K 604.0
1206 1206 1206
3 CT4 3
26 12 J4
IN2R-/CR1/CR1 FILTD OUT1L+ 10UF
CON024
CAP002
27
IN2R+/CR2/CR2 DAC1_LEFT 8
CT1 C6 CT2 C8
10UF 0.1UF 10UF 0.1UF
3 B 0805 B 0805 R41 C16
AD1836_RESET PD/RST 2.74K 220PF 9
1206 1206 C12 R38
AD1836AASZ 2200PF 49.9K
MQFP52 AD1836_VREF 1206 1206
SOIC8
AD8606ARZ
C7 C9 C10 C11
1000PF 1000PF 1000PF 1000PF 3
0805 0805 0805 0805
AGND 1 AD1836_VREF
2
U12
R28 R27 AGND

0 0
SOIC8
1206 1206
AD8606ARZ
5
AGND SW1: Audio Loopback
For Test Purposes 7
Default = All Off
6
U12
SW1
1 12
ON
ADC1_LEFT DAC1_LEFT
1
R29
2 11 R193 0
ADC1_RIGHT DAC1_RIGHT
2
0 1206
3 10 1206
ADC2_LEFT DAC2_LEFT
3
4 9
Nashua, NH 03063
ADC2_RIGHT DAC2_RIGHT
DEVICES
4
4 PH: 1-800-ANALOGD 4
5 8
DAC3_LEFT
5
6 7
DAC3_RIGHT
ADSP-BF533 EZ-KIT LITE
6
SWT017
Title
DIP6
AGND
AUDIO CODEC
Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 4 of 12
A B C D
A B C D
1 1
R67 C35
5.49K 100PF
1206 1206
R59 C30
R66 R68 5.49K 100PF
11.0K 3.32K 1206 1206
1206 1206
OUT2R- R58 R60
11.0K 3.32K
1206 1206
C33
330PF OUT3R-
U16
0805 2
1 C28
330PF
DAC2 RIGHT 3 0805 6
U15
C34
AD8606ARZ
680PF 7
R72 0805 R69
SOIC8
R71 DAC3 RIGHT
5.49K 1.65K 604.0 5
1206 1206 1206 C29
CT7 AD8606ARZ
J4 680PF
OUT2R+ 10UF SOIC8
CON024 R64 0805 R61 R63
CAP002
5.49K 1.65K 604.0
DAC2_RIGHT 4 1206 1206 1206
CT6
J4
OUT3R+ 10UF
CON024
CAP002
R73 C36
2.74K 220PF 6 DAC3_RIGHT 1
1206 1206 C32 R70
2200PF 49.9K
AD1836_VREF 1206 1206 R65 C31
2.74K 220PF 3
1206 1206 C27 R62
2200PF 49.9K
2 AD1836_VREF 1206 1206 2
AGND
AGND
R75 C40
5.49K 100PF
1206 1206
R51 C25
5.49K 100PF
R74 R76 1206 1206
11.0K 3.32K
1206 1206
R50 R52
OUT2L- 11.0K 3.32K
1206 1206
C38 OUT3L-
330PF
U16
0805 6
C23
7 330PF
U15
0805 2
DAC2 LEFT 5
3 C39 1 3
680PF
AD8606ARZ
SOIC8
DAC3 LEFT
R80 0805 R77 R79 3
5.49K 1.65K 604.0 C24
AD8606ARZ
1206 1206 1206 680PF
CT8 SOIC8
J4 R56 0805 R53 R55
OUT2L+ 10UF
CON024 5.49K 1.65K 604.0
CAP002
1206 1206 1206
CT5
DAC2_LEFT 5 J4
OUT3L+ 10UF
CON024
CAP002
R81 C41 DAC3_LEFT 2
2.74K 220PF 6
1206 1206 C37 R78
2200PF 49.9K R57 C26
AD1836_VREF 1206 1206 2.74K 220PF 3
1206 1206 C22 R54
2200PF 49.9K
AD1836_VREF 1206 1206
AGND
AGND

Nashua, NH 03063

AUDIO OUT
Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 5 of 12
A B C D
A B C D
1 J5 FER3
CT12
R91 R98 J5 FER1
CT10
R105 R87
1
10UF 10UF
CON013 600 5.76K 5.76K CON013 600 5.76K 5.76K
CAP002 CAP002
1206 1206 1206 1206 1206 1206
2 ADC1_LEFT 5 ADC2_LEFT
C57 C45
3 C54 120PF 6 C46 120PF
100PF 1206 100PF 1206
1206 1206
R99
U19 U18
2 237.0 2
AGND 1206 AGND
1 1
AGND IN1L- AGND IN2L2
3 3
AD1836_VREF AD1836_VREF
AD8606ARZ AD8606ARZ
C53
SOIC8 SOIC8
1000PF
0805
R102 R101 R85 R84
5.76K 5.76K 5.76K 5.76K
1206 1206 C51 1206 1206
100PF
1206
ADC1 LEFT C43 ADC2 LEFT
C58 120PF
120PF 1206
1206
AGND C50 R86
R96 1000PF 750.0K
750.0K 0805 1206
U18
1206 R97 6
U19
6 237.0
1206 7
7 IN2L1
IN1L+ 5
5 AD1836_VREF
2 AD1836_VREF AD8606ARZ 2
AD8606ARZ SOIC8
SOIC8
AGND
AGND
CT9
J5 FER2 R89 R88
CT11 10UF
J5 FER4 R100 R92 CON013 600 5.76K 5.76K
10UF CAP002
CON013 600 5.76K 5.76K 1206 1206 1206
CAP002
1206 1206 1206 4 ADC2_RIGHT
1 ADC1_RIGHT
C44
C59 6 C47 120PF
3 C56 120PF 100PF 1206
100PF 1206 1206
1206
U17
R95 2
U20
2 237.0 AGND
AGND 1206 1
1 AGND IN2R2
AGND IN1R- 3
3 AD1836_VREF
AD1836_VREF AD8606ARZ
AD8606ARZ SOIC8
C52
3 SOIC8 3
1000PF
0805 R82 R83
R104 R103 5.76K 5.76K
5.76K 5.76K 1206 1206
1206 1206 C48
100PF
1206 C42 ADC2 RIGHT
ADC1 RIGHT 120PF
C55 1206
120PF
1206
AGND C49 R90
R94 1000PF 750.0K
750.0K 0805 1206
U17
1206 R93 6
U20
6 237.0
1206 7
7 IN2R1
IN1R+ 5
5 AD1836_VREF
AD1836_VREF AD8606ARZ
AD8606ARZ SOIC8
SOIC8
AGND
AGND

Nashua, NH 03063

AUDIO IN
Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 6 of 12
A B C D
A B C D
PPICLK_ONBOARD_SELECT PPICLK_AD7183_SELECT PPCLK
0 0 PPI_27MHZ_CLK (DEFAULT)
0 1 ADV7183_CLKOUT DAC B DAC C DAC D
1 X EXPANSION_CLK Composite Video CVSB CVSB
Component Video B R G
Differential Component Video U V Y

U25
3 S Video C Y
PPI_27MHZ_CLK U26 R132
1 3 0
0805
6 1
ADV7183_CLKOUT PPI_CLK R125
1 6 1K
1
4 1206
PPICLK_AD7183_SELECT
4
ADG752BRTZ
SOT23-6 A3V
ADG752BRTZ
SOT23-6
EXPANSION_PPI_CLK
PPICLK_ONBOARD_SELECT U24
R127 J8
4 5 75 CON024
L5 L3 L4 1206
0.68UH 2.2UH 0.68UH 1 VIDEO_DAC_B 5
0805 0805 0805 DAC B
3 AD8061ARTZ
3V_B 2 SOT23-5
6
R126
R123 C69 C70 R124 1K
75 330PF 330PF 75 1206
1206 0805 0805 1206
SW2: Video Loopback
For Test Purposes
Default = All Off
R128 C71 C72 R129
VIDEO ENCODER 10K 0.1UF 0.1UF 1.2K
TP4 0805 0805 0805 1206
SW2
U27 1 12
ON
VIDEO_AVIN1 VIDEO_DAC_D
1
AGND2
AGND2 2 11
VIDEO_AVIN4 VIDEO_DAC_B
2
14 32
P15 DAC_A 3 10
VIDEO_AVIN5 VIDEO_DAC_C
3
13 31 R119
2 P14 DAC_B 1K 4 9 2
4
12 26 1206
P13 DAC_C 5 8
5
9 27
P12 DAC_D 6 7
6
8 A3V
P11 DIP6
7 25 SWT017
P10 COMP
6 33
P9 VREF
5 34
P8 RSET U23
PF12 4 R117 J8
PF[15:12] P7 4 5 75 CON024
PF13 3 15 L6 L2 L7 1206
P6 HSYNC ADV7171_HSYNC 0.68UH 2.2UH 0.68UH 1 VIDEO_DAC_C 2
PF14 2
P5 FIELD/VSYNC
16
ADV7171_VSYNC
0805 0805 0805 DAC C
3 AD8061ARTZ
PF15 42 17 2 SOT23-5
P4 BLANK 3
PP3 41
PP[3:0] P3
1
PP2 40 R118
P2 D1
3V_B R122 R121 C67 C68 R120 1K
AD1580BRTZ
PP1 39 150.0 75 330PF 330PF 75 1206
P1 SOT23D
1206 1206 0805 0805 1206
2
PP0 38
P0
44 11
ADV7171_27MHZ_CLK CLOCK VAA1
1
VAA2
22 20
3V_B ADV7171_RESET RESET VAA3 AGND2
30 AGND2
VAA4
18 28
ALSB VAA5 R131
3 24 1K 3
PF1_SDATA SDATA 1206
23 21
R130 PF0_SCLOCK SCLOCK GND1
100K 29
1206 GND2 A3V
35 43
SCRESET/RTC GND3
37 19
TTX GND4
36 10
TTXREQ GND5
U22
R116 J8
ADV7171KSUZ 4 5 75 CON024
R112 TQFP44 L8 L1 L9 1206
100K 0.68UH 2.2UH 0.68UH 1 VIDEO_DAC_D 8
1206 0805 0805 0805 DAC D
3 AD8061ARTZ
2 SOT23-5
9
R115
R113 C73 C74 R114 1K
75 330PF 330PF 75 1206
1206 0805 0805 1206
R182
0
1206
AGND2
R226
AGND2
Nashua, NH 03063
0
4
PF1
0805
PF1_SDATA
R227
0
0805
AGND2 Title ADSP-BF533 EZ-KIT LITE
PF0 PF0_SCLOCK
VIDEO OUT
Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 7 of 12
A B C D
A B C D
3.3V
DAC_C
DAC_D
DAC_B
(WHITE) OUT R142 R143 R139 R138
10K 10K 10K 10K
0805 0805 0805 0805
(RED) IN
1 VIDEO DECODER 1
U28
AVIN5
AVIN4
AVIN1 ADV7183_27MHZ_CLK
29
XTAL P15
73 PF12
PF[15:12]
28 74 PF13
XTAL1 P14
75 PF14
P13
66 76 PF15
ALSB P12
67 5 PP3
PF1_SDATA SDA P11 PP[3:0]
AVIN1 AVIN4 AVIN5 68 6 PP2
PF0_SCLOCK SCLK P10 R144
Composite Video CVBS CVBS CVBS 7 PP1 33 R183
P9 0805 33
Differential Component Video Y U V U21
64 8 PP0 1 0805
ADV7183_RESET RESET P8 4
S Video Y C 36 19 2 ADV7183_CLKOUT
PWRDN P7
SN74LVC1G32
20
P6 SOT23-5
65 21
J8 R141 C90 NC[ISO] P5
CON024 0 0.1UF 22
0805 0805 P4
7 VIDEO_AVIN1 42 23
AVIN1 AIN1 P3
41 24
AIN7 P2 PVDD_ADV7183
9 32
P1
TP7
44 33
AIN2 P0
43
J8 R136 C88 AIN8
CON024 0 0.1UF AGND2 27
2 0805 0805 LLC1 C82 C83 2
TP6
4 VIDEO_AVIN4 46 26 0.01UF .082UF
AVIN4 AIN3 LLC2 0805 R140 0805
45 25 1.5K
AIN9 NC[LLCREF] 0805
6 37
ELPF
58
AIN4
57 2
J8 R135 C89 AIN10 HS ADV7183_HS
CON024 0 0.1UF 1
0805 0805 VS ADV7183_VS
1 VIDEO_AVIN5 60 80
AVIN5 AIN5 FIELD ADV7183_FIELD 3.3V
59 69
AIN11 NC[VREF] ADV7183_VREF
3 70 SW3: Video Loopback
NC[HREF] ADV7183_HREF For Test Purposes
TP5
62 Default = All Off
AIN6
61 16
CT16 AIN12 NC[CLKIN] SW3
10UF 11 12 1
ON
NC[AFF] ADV7171_HSYNC TMR1
1
B C75 R145
0.1UF 51 12 10K 11 2
REFOUT SFL[HFF] ADV7183_HS
2
0805 0805
R137 R134 R133 52 13 10 3
CML NC[AEF] ADV7183_VS TMR2
3
75 75 75 C81
1206 1206 1206 0.1UF 78 9 4
NC[DV] ADV7171_VSYNC
4
0805
48 77 8 5
CAPY1 NC[RD] ADV7183_FIELD PF3
5
49 79 7 6
CAPY2 OE PF2
6
CT15 C80 DIP6
10UF 0.1UF SWT017
C78 B 0805 54 17
0.1UF CAPC1 NC[GPO3]
0805 55 18
CAPC2 NC[GPO2]
3 34 1.8V 3.3V R232 3
NC[GPO1] 10K
C77 35 0805
AGND2 0.1UF NC[GPO0] FER8
0805 600
1206
50 30 DVDD_ADV7183
AVDD DVDD1
A3V A5V 10 FER9
CT14 C79 DVDD2 600
10UF 0.1UF 72 1206
FER10 C76 B 0805 DVDD3 DNP
600 0.1UF 38 4
1206 0805 PVDD DVDDIO1
DNP 15
DVDDIO2
39
AGND1
40 3
FER12 AGND2 DGND1
600 47 9
1206 AGND3 DGND2
53 14
AGND4 DGND3
FER11 56 31
600 AGND5 DGND4
1206 63 71
DNP NC[AGND6] DGND5
PVDD_ADV7183
A1.8V
ADV7183BKSTZ
LQFP80
FER13 C84 C85 C86 C87
600 0.1UF 0.01UF 0.1UF 0.01UF
1206 0805 0805 0805 0805

Nashua, NH 03063
AGND2
VIDEO IN
Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 8 of 12
A B C D
A B C D
3.3V
R150
10K
0805
PF8 R149 R157

100 0 3.3V
U10
0805 1206
3 4
SW4
74LVC14A
1 SWT013 1
SOIC14
MOMENTARY 3.3V
CT17
1UF 3.3V
A RESET
LED2
RED
LED001
R172
10K
0805
R164
U10
R166 270
10K 1206 13 12
RESET 0805
3.3V U29 RESET
74LVC14A
SOIC14
1 8 U31
MR RESET
SW8 4 7 2 18
SWT013 PFI RESET 1A1 1Y1
MOMENTARY 5 4 16
PFO 1A2 1Y2
LED1 6 14
ADM708SARZ 1A3 1Y3
R151 SOIC8 LED2 8 12 5V
10K 1A4 1Y4
0805
LED3 11 9
PF9 R155 R167 2A1 2Y1
100 0 LED4 13 7
U10 2A2 2Y2
0805 1206
11 10 DA_SOFT_RESET LED5 15 5
2A3 2Y3
SW5 LED6 17 3
74LVC14A LED[6:1] 2A4 2Y4
SWT013
SOIC14
MOMENTARY
CT18 1
1UF OE1 POWER
A 19 LED9 LED8 LED7 LED6 LED5 LED4 LED1
2 OE2 YELLOW YELLOW YELLOW YELLOW YELLOW YELLOW GREEN-SMT 2
LED001 LED001 LED001 LED001 LED001 LED001 LED001
IDT74FCT3244APY
SSOP20
3.3V R160 R161 R168 R162 R147 R146 R163

270 270 270 270 270 270 680
1206 1206 1206 1206 1206 1206 1206
R156
10K
0805
PF10 R154 R148

100 0
U10
0805 1206
9 8
SW6 SJ1
74LVC14A
SWT013 3.3V SHORTING
SOIC14
MOMENTARY JUMPER
CT20 DEFAULT=OFF
1UF
A
C92 UART JP4

0.1UF U30 C91 1
0805 0.1UF
1 0805 2
3 C1+ 3
3 IDC2X1
C94 C1- 2
0.1UF V+ FER15
0805 4 6 600
3.3V C2+ V- 0603
5
C2- P2
R110 FER17
0 600
0805 11 14 0603 1
DNP TX T1IN T1OUT
10 7 6
PF6 T2IN T2OUT FER14
12 13 600 2
R153 SW9 RX R1OUT R1IN 0603
10K 1 12 9 8 7
ON
PF8 R2OUT R2IN

1
0805 R111
2 11 0 ADM3202ARNZ FER16 3
PF9
2
PF11 R152 R158 R169 0805 SOIC16 C93 600

100 0 3 10 0 0.1UF 0603 8
U10 PF10
3
0805 1206 0805 0805

5 6 4 9 DNP 4
PF11
4
SW7 5 8 PF7
74LVC14A 9
TFS0 RFS0
5
SWT013
SOIC14
MOMENTARY 6 7 5
RSCLK0 TSCLK0
6
CT19
1UF DIP6
A SWT017
DB9M
SW8 PB Enable Switch

Position Function ANALOG 20 Cotton Road
Nashua, NH 03063
Connects the push buttons to the Programmable Flags of the DSP
4 1-4
Useful if using the PFs for another purpose. DEVICES PH: 1-800-ANALOGD 4
Connects SPORT0 frame sync and clock together external to the DSP
5,6
Required when AD1836 is in I2S mode Title ADSP-BF533 EZ-KIT LITE
IO/RESET/UART
Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 9 of 12
A B C D
A B C D
EXPANSION INTERFACE (TYPE B)

5V
3.3V 5V 3.3V
D[0:15]
A[1:19]
J1
2 1 PF[0:15] J3
J2 2 1
4 3 2 1
1 4 3 1
A1 6 5 4 3
6 5
A3 8 7 A2 6 5 TX RX
8 7
A5 10 9 A4 8 7
10 9
A7 12 11 A6 10 9 PA1_B PA0_B
MOSI SCK 12 11
A9 14 13 A8 12 11 PA3_B PA2_B
MISO 14 13
A11 16 15 A10 14 13 PA5_B PA4_B
16 15
A13 18 17 A12 16 15 PA7_B PA6_B
18 17
A15 20 19 A14 18 17 PA7_A PA6_A
NMI 20 19
A17 22 21 A16 20 19 PB7_A PB6_A
22 21
A19 24 23 A18 22 21
24 23
26 25 24 23
TMR2 26 25
28 27 26 25
P6 TMR0 TMR1 28 27
1 2 30 29 28 27 RESET
MOSI DT1SEC DR1SEC 30 29
3 4 32 31 30 29 RESET CLK_OUT_EXP1
SPISS DT1PRI DR1PRI 32 31
5 6 34 33 32 31 ADV7183_HS EXT_DSP_CLK
SCK TFS1 RFS1 34 33
7 8 36 35 34 33 ADV7183_FIELD ADV7183_VS
TSCLK1 RSCLK1 36 35
9 10 38 37 36 35 ADV7183_HREF ADV7183_VREF
SPIS1 DT0SEC DR0SEC 38 37
11 12 D1 40 39 D0 38 37
MISO DT0PRI DR0PRI 40 39
IDC6X2 D3 42 41 D2 40 39
TFS0 RFS0 42 41
D5 44 43 D4 42 41
TSCLK0 RSCLK0 44 43
D7 46 45 D6 PF14 44 43 PF15
2 SPI 46 45 2
D9 48 47 D8 PF12 46 45 PF13
48 47
D11 50 49 D10 PF10 48 47 PF11
50 49
D13 52 51 D12 PF8 50 49 PF9
52 51
D15 54 53 D14 PF6 52 51 PF7
54 53
56 55 PF4 54 53 PF5
56 55
58 57 PF2 56 55 PF3
58 57
60 59 PF0 58 57 PF1
60 59
62 61 60 59
AMS3 62 61
64 63 62 61
AMS2 64 63
66 65 64 63
~ABE1/SDQM1 AMS1 66 65
68 67 66 65
~ABE0/SDQM0 AMS0 68 67
70 69 68 67
AOE ARDY 70 69
72 71 70 69
PP0 EXPANSION_PPI_CLK AWE ARE 72 71
74 73 72 71
PP2 PP1 74 73
76 75 74 73
PP3 SMS 76 75
78 77 76 75
78 77
80 79 78 77
80 79
82 81 80 79
~ABE0/SDQM0 ~ABE1/SDQM1 82 81
84 83 82 81 BR
SRAS SCKE 84 83
86 85 84 83 BG
SA10 SCAS 86 85
3 All USB interface circuitry is considered proprietary and has 88 87 86 85 BGH 3
SWE CLK_OUT_EXP2 88 87
been omitted from this schematic. 90 89 88 87
90 89
90 89
3.3V When designing your JTAG interface please refer to the CON019
CON019
Engineer to Engineer Note EE-68 which can be found at CON019
http://www.analog.com
DSP JTAG HEADER 3.3V

R173
10K
0805
R16 R15 R18

10K 10K 10K
0805 0805 0805
3V
ZP4
DA_EMULATOR_SELECT TMS TMS
SPORT1
1 2 P3
DA_EMULATOR_SELECT 1 2
3 4 DA_EMULATOR_EMU TCK TCK RFS1 TFS1
DA_EMULATOR_EMU 3 4
5 6 DA_EMULATOR_TMS TRST TRST RSCLK1 TSCLK1
DA_EMULATOR_TMS 5 6
7 8 DA_EMULATOR_TCK TDI TDI DR1PRI DT1PRI
DA_EMULATOR_TCK 7 8
9 10 DA_EMULATOR_TRST TDO TDO
DA_EMULATOR_TRST 9 10
11 12 DA_EMULATOR_TDI EMU EMU R174 R175
DA_EMULATOR_TDI 0 11 12 0
13 14 DA_EMULATOR_TDO 1206 1206
IDC7X2
RESET
DA_EMULATOR_TDO
RESET
DA_GP0
DA_GP1
DR1SEC
13
15
14
16
DT1SEC ANALOG 20 Cotton Road
Nashua, NH 03063
4 DA_SOFT_RESET DA_SOFT_RESET
DA_GP2
DA_GP3
17
19
18
20
SHGND
ADSP-BF533 EZ-KIT LITE

GND
IDC10X2 Title
DEBUG_AGENT
CONNECTORS
Size Board No. Rev
C A0167-2001 2.2
SHGND
Date 5-24-2007_14:20 Sheet 10 of 12
A B C D
A B C D
5V A5V
D2
F1 FER23 S2A R177 FER18 UNREG_IN 3V_B A3V
2.5A 190 2A VR5 0 600
FUS001 FER002 DO-214AA 1206 1206
4 3 UNREG_IN 3 2 R178 FER19
INPUT OUTPUT VR1 0 600
1 2 GND 1206 1206
1 ADP3339AKCZ-5 3 2
J9 INPUT OUTPUT
SOT-223
1 D3
GND
S2A
C97 R176 CT22 C98 CT23 C175 1 ADP3338AKCZ-33
2A
1000PF 100K 10UF 0.1UF 10UF 0.1UF SOT-223
DO-214AA
2 1206 1206 C 0805 C 0805 C104 CT21 C143
1 1UF 10UF 0.1UF 1
3 0805 C 0805
7.5V_POWER
CON005
C96
1000PF
1206
R186
0
0805
SHGND SW10: Core Voltage Source Select
VDDRTC DEFAULT: Not Populated
Position Function
R187
0 1 and 2 DSP_VDD_INT = DSP Internal Voltage Regulation
0805
DSP_VDD_EXT 2 and 3 DSP_VDD_INT = 1.4V Fixed
Note: For boards without a 750MHz processor this jumper will not
be populated and the DSP_VDD_INT will be hard-wired with R222
3.3V 3.3V 1.8V A1.8V R223 to use the processor internal regulator.
3.32K
0805
FER20 DSP_VDD_INT
600 TP15
VR2 1206
7 1
2 R192 IN1 OUT1 UNREG_IN 2
10K 8 2
0805 IN2 OUT2 R188 U32 L12 R222
3 R190 VR3 0 10UH 0
OUT3 76.8K C103 0805 IND001 0805
6 5 1206 1UF 3 2 1 5
SD GND FB 0805 INPUT OUTPUT
4 ADP3336ARMZ GND 2 6
MSOP8 1 ADP3339AKCZ-33
SOT-223 3 7
CT28
C102 CT25 C100 CT24 4 8 68UF
VROUT D5
1UF R191 10UF 0.1UF 10UF D
ZHCS1000
0805 147.0K C 0805 C
1A
1206
SOT23-312
FDS9431A JP3
SOIC8 1
C105
0.1UF 2
0805
3
IDC3X1
DNP
R211
0
0805
VR6 DNP
7 1 1V4
R214 IN1 OUT1
10K 8 2
UNREG_IN 0805 IN2 OUT2
3 R184
OUT3 64.9K
6 5 R210 0805
C65 C62 SD GND FB 0
3 10UF 10UF 4 ADP3336ARMZ 0805 C61 CT13 3
1210 0805 MSOP8 1UF 10UF
DNP 0805 C
C60
1UF R185
0805 340.0K
0805
3.3V
R165
R11 VR4 0.05
24.9K 1206
0603 5 TP1
1 IN U34
COMP
4 4 1
CS L10
C63 C64 2 6.8UH
470PF 68PF 3 6 R159 IND009
0603 0603 FB PGATE 0 5
GND 0603
R170 2 ADP1864 3 6
80.6K SOT23-6
0603
D6
FDC658P CT26 CT27 C4
SSB43L
SOT23-6 47UF 2.2UF 1UF DSP_VDD_EXT
4A
B B 0805
DO-214AA
DNP DNP
PGND
R171
255.0K D4
0603 S2A
2A
DO-214AA

Nashua, NH 03063
PGND
4 R3
0
0805
DSP_VDD_INT
POWER
PGND Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 11 of 12
A B C D
A B C D
DSP_VDD_EXT
DSP_VDD_INT BBBYP
RES IN PLACE OF C188
C181 C183 C184 C182 C185 C180 C199 C200 C198 C190 C188 C187 C189 C186 C191 C196 C194 C193 C195 C192 C197 C179 R194
0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 10UF 10UF 0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0
0805 0805 0805 0805 0805 0805 1210 1210 1210 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805
DNP
1 1
ADSP-21533
U1
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V A5V A5V
C159 C153 C155 C154 C150 C149 C136 C126 C127 C124 C169 C123 C174 C173 C166 C168 C167 C201 C208 C151 C130 C138
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.22UF 0.22UF
0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805
AGND AGND
IDT74FCT3807 PSD4265 A PSD4265 B SN74LVC1G125 SDRAM 74LVC00AD 74LVC14A
U4 U5 U6 U7 U8 U9 U10 AD8606 AD8606
U12 U13
2 2
3.3V 5V A5V A5V A5V A5V A5V A5V A5V 3.3V A3V A3V A3V 3.3V 3.3V
C165 C177 C99 C176 C178 C129 C137 C139 C141 C140 C142 C210 C110 C108 C111 C112 C109 C113 C172 C171
0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.1UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.01UF 0.01UF
0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805
AGND AGND AGND AGND AGND AGND AGND AGND2 AGND2 AGND2
AD1836 ADG752 ADG752
U14 AD8606 AD8606 AD8606 AD8606 AD8606 AD8606 SN74AHC1G08 AD8061 AD8061 AD8061 U25 U26
U15 U16 U17 U18 U19 U20 U21 U22 U23 U24
3V_B 3.3V 3.3V 3.3V 3.3V 3.3V
DVDD_ADV7183
3 3
C146 C147 C145 C148 C144 C95 C119 C132 C128 C204 C156 C157 C158 C152 C163 C161 C209
0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.1UF
0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805
ADV7171 ADV7183 ADM708SAR ADM3202 IDT74FCT3244APY IDT2305

U27 U28 U29 U30 U31 U46
FER21
600
1206
M1 M2 M3
MH1 MH2 MH3 MH4 MH5 MH7 MH8 MH9
TP12 TP14 TP13 TP11 TP8 TP9 TP10
RUBBER FOOT RUBBER FOOT RUBBER FOOT
MSC009 MSC009 MSC009
FER22 SHGND
Nashua, NH 03063
600
4
M4 M5
1206
RUBBER FOOT RUBBER FOOT

MSC009 MSC009
SHGND BYPASS CAPS

SHGND Size Board No. Rev
C A0167-2001 2.2
Date 5-24-2007_14:20 Sheet 12 of 12
A B C D
I INDEX
A clock
AD1836 audio codecs, xi, 1-13, 1-15, 2-4, 2-12 frequency, 1-9
ADV7171 video encoders, xi, 1-16, 2-6, 2-7, in (CLK IN) signal, 2-7
2-11 out (CLK OUT) signal, 2-3
ADV7183 video decoders, xi, 1-16, 2-6, 2-7, codecs, See 1836 audio codecs
2-11 configuration, of this EZ-KIT Lite, 1-3
AINx analog video channels, 2-7 connectors
~AMS2-0 memory select pins, 1-8, 1-10, 2-3 diagram of locations, 1-3, 2-17
analog DB9 (UART), 2-8, 2-20
audio interface, See SPORT0, SPORT1 J1-3 (expansion interface), 2-8, 2-17
video interface, See video interface J4-5 (audio), 2-18
architecture, of this EZ-KIT Lite, 2-2 J8 (video), 2-18
ASYNC (asynchronous memory control) J9 (power), 1-4, 2-18
control registers, 1-11 P1 (FlashLINK), 2-19
external memory banks 0-2, 1-8, 1-10 P2 (RS-232), 2-8, 2-20
audio P3 (SPORT1), 2-4, 2-20
codecs, See AD1836 audio codecs P6 (SPI), 2-4, 2-13, 2-21
connectors (J4-5), 2-18 ZP4 (JTAG), 2-9, 2-21
contents, of this EZ-KIT Lite package, 1-2
core
B frequency, 1-9
background telemetry channel (BTC), 1-17 voltage, 2-2
bill of materials, A-1 customer support, xiv
board schematic (ADSP-BF533), B-1
boot mode switch (SW11), 2-11
D
DAC analog video channels, 2-7
C Data In/Out registers, 1-12
CCLK pin, 1-9 DB9 (UART) connector, 2-8, 2-20
default configuration, of this EZ-KIT Lite, 1-3
ADSP-BF533 EZ-KIT Lite Evaluation System Manual I-1

INDEX
DIP switches flash memories

diagram of locations, 1-3 See also flash A, flash B
SW1-2 (test), 2-11 configuration registers, 1-7
SW3 (video config), 1-16, 2-7, 2-11 EBIU connection, 2-3
SW9 (push button enable), 1-16, 2-12, 2-13 general-purpose IO pins, 1-10, 1-12, 2-15,
Direction registers, 1-12 2-20
internal SRAM, 1-7
primary/secondary, 1-7, 1-10, 2-3
E
programming/configuring, 1-14
EBIU, See external bus interface unit reserved, 1-11
EBIU_AMBCTLx registers, 1-11 flash ports (PB5-0), 2-15
EBIU_SDx registers, 1-9 frequency, 1-9
example programs, 1-17
expansion interface, 2-3, 2-4, 2-8, 2-17
external bus interface unit (EBIU), 2-3 G
external memory general-purpose IO pins, 1-10, 1-12, 1-15, 1-16
See also flash memories, SDRAM, ASYNC GND signal, 2-8, 2-19
via JTAG, 2-9
H
F Help, online, xix
features, of this EZ-KIT Lite, x HSYNC signal, 2-6, 2-7, 2-12
FIELD pin, 2-4, 2-7, 2-12
flag pins, See programmable flags (PFs)
I
flash A
configuration registers, 1-11, 1-12 installation, of this EZ-KIT Lite, 1-5
port A controls, 1-13 interfaces, See video, SPORT, PPI, SPI,
port B controls, 1-13 expansion
primary/secondary/SRAM, 1-11 internal memory
flash B core MMRs, 1-8
configuration registers, 1-11, 1-13 data banks A, B (SRAM), 1-8
primary/secondary/SRAM, 1-11 instruction SRAM, 1-8
FlashLINK connector (P7), 2-19 instruction SRAM/CACHE, 1-8
reserved, 1-8
scratch pad SRAM, 1-8
system MMRs, 1-8
via JTAG, 2-9
IO
port registers, 1-12
voltage, 2-2
I-2 ADSP-BF533 EZ-KIT Lite Evaluation System Manual

INDEX
J power
JTAG connector (J9), 2-18
cable, 1-14 specifications, 2-19
connector (ZP4), 2-21 PPI7-0 pins, 2-6
emulation port, 2-9 PPI_CLK pin, 1-13, 2-6
jumpers PPI_FSYNC signal, 2-6
diagram of locations, 2-10 PPI_HSYNC signal, 2-6
default settings, 1-3 primary memory, See flash memories, flash A,
flash B
programmable flags (PFs)
L connections, 2-4
LEDs PF0 (serial clock), 1-17, 2-4
diagram of locations, 1-3, 2-13 PF12-15 (PPI7-4 and video MSB signal), 2-5,
LED1 (power), 1-4, 2-15 2-6
LED2 (reset), 1-4, 2-15 PF1 (serial data), 1-17, 2-4
LED4-9 (general-purpose IO), 1-14, 1-15, PF2 (ADV7183 OE signal), 1-17, 2-4, 2-11
2-15 PF3 (ADV7183 FIELD pin), 2-4, 2-6, 2-12
ZLED3 (USB monitor), 1-5, 2-16 PF4 (AD1836 SPI select), 1-16, 2-4, 2-5
license restrictions, 1-7 PF5-7 (PPI14-12), 2-5
PF8-11 (PPI11-8 and SW4-7), 1-15, 2-5,
2-12, 2-14
M
push buttons
Media Instruction Set Computing (MISC), ix See also switches by name (SWx)
memory diagram of locations, 2-13
map, of this EZ-KIT Lite, 1-7, 1-11
select pins, See ~AMS2-0, ~SMS0
MSB pin, 2-5, 2-6 R
RCA jacks, x, 2-18
registration, of this product, 1-3
N
reset
notation conventions, xx AD1836 codec, 1-13
ADV7171/ADV7183 decoder/encoder, 1-13
O LED (LED2), 2-15
oscillators, 1-13 processor, 1-9, 1-10, 1-12
push button (SW8), 2-15
restrictions, of the licence, 1-7
P RFS0 pin, 1-15, 2-12
package contents, 1-2 RS-232 connector (P2), xi, 2-8, 2-20
parallel peripheral interface (PPI), 1-13, 1-16, RSCLK0 pin/register, 1-15, 2-12
1-17, 2-5, 2-7, 2-11

INDEX
S SW8 (reset) push button, 2-15

schematic, of ADSP-BF533 EZ-KIT Lite, B-1 SW9 (push button enable) DIP switch, 1-16,
SCLK pin, 1-9 2-12, 2-13
SDRAM switches
connection, 2-3 See also switches by name (SWx)
interface, 1-8, 1-9 diagram of locations, 2-10
optimum settings, 1-9 synchronous dynamic random access memory,
secondary memory, See flash memories, flash A, See SDRAM
flash B system
serial architecture, 2-2
clock (SCL), 1-17 clock register (SCLK), 1-9
data (SDAT), 1-17
serial peripheral interface (SPI) T
connector (P6), 2-4, 2-13, 2-21 Target Options dialog box, 1-9
other connections, 2-8 test DIP switches (SW1-2), 2-11
port, 1-16 TFS0 pin, 1-15, 2-12
setup, of this EZ-KIT Lite, 1-3 time-division multiplexed (TDM) mode, 1-15
~SMS0 memory select pin, 1-7, 2-3 TMR0 pin, 2-8
SPIS1/SPISS select switch (SW10), 2-13 TMR2-1 pins, 2-6, 2-8, 2-12
SPORT0 TSCLK0 pin/register, 1-15, 2-12
frame sync/clock signals, 2-12 two-wire interface (TWI) mode, 1-15
interface, 2-3, 2-8
switch (SW12), 2-13
SPORT1 U
connector (P3), 2-20 UART
interface, 2-4, 2-8 loop jumper (JP4), 2-10
SPORT audio interface, 1-15 port, xi, 2-8
SRAM (internal flash memory), 1-7, 2-3 universal asynchronous receiver transmitter, See
startup, of this EZ-KIT Lite, 1-5 UART
SW10 (SPIS1/SPISS select) switch, 2-13 USB
SW11 (boot mode) switch, 2-11 cable, 1-3, 1-4
SW12 (SPORT0) switch, 2-13 interface chip (U34), 2-15
SW1-2 (test) DIP switches, 2-11 monitor LED (ZLED3), 2-16
SW3 (video config) DIP switch, 1-16, 2-7, 2-11 user LEDs (LED4-9), 1-14, 1-15, 2-15
SW4-7 (general input) push buttons, 1-15, 2-5,
2-12, 2-14
I-4 ADSP-BF533 EZ-KIT Lite Evaluation System Manual

INDEX
V VisualDSP++
video documentation xviii
configuration switch (SW3), 2-11 environment, 1-5
connector (J8), 2-18 online Help, xvii, xix
control signals, 2-8 voltage regulators, 1-9
decoders, See ADV7171 VSYNC signal, 2-6, 2-7, 2-12
encoders, See ADV7183
input mode, 2-7 X
interface, 1-16 XML register reset values, 1-9
output mode, 2-7

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ADSP-BF533 EZ-KIT Lite®

Evaluation System Manual

Revision 3.1, September 2007

Analog Devices, Inc.

Trademark and Service Mark Notice

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge)

ADSP-BF533 EZ-KIT Lite Evaluation System Manual v

Notation Conventions .................................................................... xx

USING ADSP-BF533 EZ-KIT LITE

ADSP-BF533 EZ-KIT LITE HARDWARE REFERENCE

vi ADSP-BF533 EZ-KIT Lite Evaluation System Manual

PPI Interface ........................................................................... 2-5

ADSP-BF533 EZ-KIT Lite Evaluation System Manual vii

Video (J8) ............................................................................. 2-18

ADSP-BF533 EZ-KIT LITE BILL OF MATERIALS

viii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Thank you for purchasing the ADSP-BF533 EZ-KIT Lite®, Analog

ADSP-BF533 EZ-KIT Lite Evaluation System Manual ix

The ADSP-BF533 EZ-KIT Lite provides example programs to demon-

L The ADSP-BF533 EZ-KIT Lite installation is part of the Visu-

x ADSP-BF533 EZ-KIT Lite Evaluation System Manual

• Analog video interface

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xi

The parallel peripheral interface (PPI) of the processor connects to both a

Purpose of This Manual

xii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Programmers who are unfamiliar with VisualDSP++ should refer to the

L Appendix B now is part of the online Help. The PDF version of

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xiii

What’s New in This Manual

Technical or Customer Support

• E-mail tools questions to

• E-mail processor questions to

• Phone questions to 1-800-ANALOGD

xiv ADSP-BF533 EZ-KIT Lite Evaluation System Manual

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xv

Processor Product Information

• Fax questions or requests for information to

Table 1. Related Processor Publications

ADSP-BF533 Embedded Processor Datasheet General functional description, pinout, and

ADSP-BF533 Blackfin Processor Hardware Ref- Description of internal processor architecture

xvi ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Table 2. Related VisualDSP++ Publications

VisualDSP++ User’s Guide Description of VisualDSP++ features and usage.

Online Technical Documentation

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xvii

Each documentation file type is described as follows.

.chm Help system files and manuals in Help format

.pdf VisualDSP++ and processor manuals in Portable Documentation Format (PDF).

If documentation is not installed on your system as part of the software

Accessing Documentation From VisualDSP++

Accessing Documentation From Windows

xviii ADSP-BF533 EZ-KIT Lite Evaluation System Manual

Accessing Documentation From Web

Hardware Tools Manuals

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xix

xx ADSP-BF533 EZ-KIT Lite Evaluation System Manual

filename Non-keyword placeholders appear in text with italic style format.

Note: For correct operation, ...

L A Note provides supplementary information on a related topic. In the

Caution: Incorrect device operation may result if ...

Warning: Injury to device users may result if ...

ADSP-BF533 EZ-KIT Lite Evaluation System Manual xxi

xxii ADSP-BF533 EZ-KIT Lite Evaluation System Manual