High Precision Duty Cycle Correction Circuit Design For 5.2Ghz Speed I/O Applications

A
Dissertation Report
on
High Precision Duty Cycle Correction
Circuit Design for 5.2GHz Speed I/O
Applications
Submitted to the Department of Electronics Engineering
in Partial Fulfillment of the Requirements for the Degree of
Master of Technology
(VLSI & Embedded Systems)
by
Upadhyay Bhargav S
(P13VL003)
Guided by
Dr. A. D. Darji
Assistant Professor, ECED
&
Mr. Venkatesh Rao

Circuit Design Manager, Intel Technology Pvt. Ltd.
DEPARTMENT OF ELECTRONICS ENGINEERING

SARDAR VALLABHBHAI NATIONAL INSTITUTE OF TECHNOLOGY
JULY 2015
Sardar Vallabhbhai National Institute Of Technology
Surat - 395 007, Gujarat, India
ELECTRONICS ENGINEERING DEPARTMENT
CERTIFICATE
This is to certify that Upadhyay Bhargav S, (Adm. No. P13VL003), Full-time
M.Tech student has presented his Dissertation Preliminary Report on High Precision
Duty Cycle Correction Circuit Design for 5.2GHz Speed I/O Applications , in par-
tial fulfillment of the requirement for the award of the degree Master of Technology in
Electronics Engineering with specialization in VLSI & Embedded Systems during
the year 2014 - 15.
Guide Intel Supervisor Examiner Chairman
P. G. Incharge Head of The Department
Seal of The Department

JULY 2015
Acknowledgements
I take this opportunity to express my gratitude to my guide Dr. Anand D. Darji for
his guidance, monitoring and constant encouragement throughout the course of this
dissertation. I am grateful to Mr. Venkatesh Rao, Mr. Bhimisethhi Chakravarti and Mr.
Rao Mallikharjuna from Intel Corporation, India for their constant helpful technical
guidance, discussions, suggestions and doubt solving. A special thanks to Mr. Sunil
Ramanathan of Intel for providing useful guidance in drawing layout and post-layout
simulations.
I also take this opportunity to thank to Dr. (Ms.) U. D. Dalal, Head of the Electron-
ics Engineering Department, SVNIT for their co-operation and suggestions throughout
the work. I would also like to thank my colleagues of M. Tech. (VLSI & Embedded
Systems) 2013-15 batch, who in one way or the other provided me assistance and moti-
vation whenever required. Lastly, but importantly, I am thankful to my family for their
understanding, constant support and encouragement.
Bhargav Upadhyay
SVNIT, Surat
July, 2015
v
Abstract
With enhancement in the technology, requirement for high speed data communication
becomes very important. The data communication system has receiver (Rx) and trans-
mitter (Tx) at physical layer. To achieve high speed date rate ( 10 gbps) between
Rx and Tx data should be sampled at this rate. To sample data at high data-rate, half
rate clock data recovery (Rx)/sampling (Tx) circuit is used. This circuit samples data
on both the edges of clock to double the data rate. For such circuits which operates
on both the edges, 50% duty cycle is very important. To sample the data correctly it
should meet setup and hold margin specifications of sampling flop. In the present day
technology setup and hold margin ranges in 20-50 ps including all uncertainty of man-
ufacturing process. The application for which duty cycle correction circuit is designed
is operating at 5.2 GHz (period = 192.3 ps). At such high frequency if duty cycle degra-
dation is there then probability of false sampling is very high which eventually results
in poor performance of over all data communication system. To avoid this duty cycle
correction is needed before feeding clock to the sampling circuit and DCC circuit plays
crucial role in robust and effective performance of data communication system.
The main cause of degradation is buffers used in the clock paths. Mismatch between
driving strength of nMOS and pMOS of the buffer changes rising and falling slopes
of the clock signals which eventually results in duty cycle change. This mismatch is
mainly duo to manufacturing and process variations, temperature variation also plays
part in degradation but very less compare to process variation.
In this report, a DCC architecture is presented to correct duty cycle of clock fre-
quency 5.2 GHz. Duty cycle adjuster and Duty cycle corrector circuits are chosen to
have minimum chip area and power consumption. As calibration of this DCC is done
during start up of the application, correction time require to correct the duty cycle is
not concern here. As operating frequency is very high it is challenging to get accuracy
up to 0.1 % (0.2ps). The design of the circuit is expected to meet 0.1% accu-
racy and should support 5% (10ps) correction range across 9 Process, Voltage and
Temperature (PVT) variations.
vii
Declaration
I declare that this written submission represents my ideas in my own words and where
others ideas or words have been included, I have adequately cited and referenced the
original sources. I also declare that I have adhered to all principles of academic honesty
and integrity and have not misrepresented or fabricated or falsified any idea or data or
fact or source in my submission. I understand that any violation of the above will be
cause for disciplinary action by the Institute and can also evoke penal action from the
sources which have thus not been properly cited or from whom proper permission has
not been taken when needed.
Date: 23/07/2015 Bhargav Upadhyay

Place: Bangalore (P13VL003)
SVNIT, Surat
ix
Table of Contents
Page
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
Chapters
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Importance of DCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Cause of Degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Design Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Basic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 Thesis Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.7 Organization of thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Digital Duty Cycle Corrector . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Basic Digital DCC Architecture . . . . . . . . . . . . . . . . . 7
2.1.2 Recent Architecture of Digital DCC . . . . . . . . . . . . . . . 9
2.2 Analog Duty Cycle Corrector . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 Basic Architecture of Analog DCC . . . . . . . . . . . . . . . 13
2.2.2 Recent Architecture of Analog DCC . . . . . . . . . . . . . . . 14
2.3 Mixed Mode Duty Cycle Corrector . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Basic Architecture of Mixed Mode DCC . . . . . . . . . . . . 17
2.3.2 Recent Architecture of Mixed Mode DCC . . . . . . . . . . . . 19
2.4 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 Architecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Duty Cycle Adjuster . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Coarse Correction Circuit . . . . . . . . . . . . . . . . . . . . 27
3.1.2 Fine Correction Circuit . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Single to Differential . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Low pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.1 Design of Dynamic Comparator Circuit . . . . . . . . . . . . . 33
3.5 Digital Feedback Mechanism . . . . . . . . . . . . . . . . . . . . . . . 34
xi
Table of Contents
3.6 System Level Working . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4 Results and Summery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1 Duty Cycle Adjuster . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.1 Coarse Correction . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.2 Fine Correction Circuit . . . . . . . . . . . . . . . . . . . . . . 41
4.2 Single to Differential . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3 Low Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4 Dynamic Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5 Digital Feedback Mechanism . . . . . . . . . . . . . . . . . . . . . . . 50
4.6 Close loop Simulation Results . . . . . . . . . . . . . . . . . . . . . . 53
4.7 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 57
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
xii
List of Figures
1.1 DCC inside Transmitter/ Receiver . . . . . . . . . . . . . . . . . . . . 2

1.2 Clock signal with 50% duty cycle . . . . . . . . . . . . . . . . . . . . 2
1.3 Clock signal with duty cycle degradation . . . . . . . . . . . . . . . . 3
1.4 Design Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.5 Basic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 Conventional Classification of DCC . . . . . . . . . . . . . . . . . . . 4
2.1 Basic Architecture of Digital DCC [1] . . . . . . . . . . . . . . . . . . 8

2.2 Timing Diagram of basic Digital DCC Architecture [1] . . . . . . . . . 8
2.3 Recent Architecture of Digital DCC [2] . . . . . . . . . . . . . . . . . 10
2.4 Overall Timing Diagram [2] . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Timing Diagram at Low frequency [2] . . . . . . . . . . . . . . . . . . 12
2.6 Timing Diagram at High frequency [2] . . . . . . . . . . . . . . . . . . 12
2.7 Analog DCC Basic Architecture [3] . . . . . . . . . . . . . . . . . . . 13
2.8 Schematic of delay cell [3] . . . . . . . . . . . . . . . . . . . . . . . . 14
2.9 (a)Pulse Stretching Mechanism,(b)Pulse Shrinking Mechanism [3] . . . 15
2.10 Recent Analog DCC Architecture [4] . . . . . . . . . . . . . . . . . . 15
2.11 Duty Cycle Adjuster [4] . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.12 Duty Cycle Detector [4] . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.13 Basic Architecture of Mixed Mode DCC [5] . . . . . . . . . . . . . . . 17
2.14 Flow Chart of Basic Mixed Mode DCC [5] . . . . . . . . . . . . . . . 18
2.15 Timing diagram of the 6-bit SAR-DCC with input clock duty cycle is
39% [5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.16 Recent Mixed Mode DCC Architecture [6] . . . . . . . . . . . . . . . . 20
2.17 Flow Chart of Latest Mixed Mode DCC Architecture [6] . . . . . . . . 21
3.1 Block Diagram of Proposed Architecture . . . . . . . . . . . . . . . . . 26

3.2 DCA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 Coarse Correction Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4 Equally weighted Coarse Correction Circuit . . . . . . . . . . . . . . . 30
3.5 DCA waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.6 single to differential . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7 single to differential circuit . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8 single to differential waveform . . . . . . . . . . . . . . . . . . . . . . 32
3.9 Low Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10 Dynamic Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Comparator Working . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
xiii
List of Figures
3.12 DFM block level RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.13 Basic Flowchart of Proposed Architecture . . . . . . . . . . . . . . . . 36
3.14 Flowchart of Coarse Correction Mechanism . . . . . . . . . . . . . . . 37
3.15 Flowchart of Fine Correction Mechanism . . . . . . . . . . . . . . . . 38
4.1 Binary Weighted Coarse Correction Pre-layout result . . . . . . . . . . 40

4.2 Binary Weighted Coarse Correction Post-layout result . . . . . . . . . . 40
4.3 Binary Weighted Coarse Correction min code Post-layout waveforms . 41
4.4 Binary Weighted Coarse Correction mid code Post-layout waveforms . 41
4.5 Binary Weighted Coarse Correction max code Post-layout waveforms . 41
4.6 Fine Correction Across PVT pre-layout simulation result summery . . . 42
4.7 Fine Correction Across PVT post-layout simulation result summery . . 43
4.8 Fine Correction min code Post-layout waveforms . . . . . . . . . . . . 43
4.9 Fine Correction mid code Post-layout waveforms . . . . . . . . . . . . 44
4.10 Fine Correction max code Post-layout waveforms . . . . . . . . . . . . 44
4.11 s2d across PVT pre-layout simulation result . . . . . . . . . . . . . . . 45
4.12 s2d across PVT post-layout simulation result . . . . . . . . . . . . . . 45
4.13 s2d post-layout waveforms across PVT . . . . . . . . . . . . . . . . . . 46
4.14 s2d pre-layout waveforms measurement . . . . . . . . . . . . . . . . . 46
4.15 s2d post-layout waveforms measurement . . . . . . . . . . . . . . . . . 46
4.16 Low pass filter simulation result at beginning . . . . . . . . . . . . . . 47
4.17 Low pass filter simulation result after correction steps . . . . . . . . . 47
4.18 Comparator Working Mechanism . . . . . . . . . . . . . . . . . . . . . 48
4.19 Comparator Working at 12.5 MHz . . . . . . . . . . . . . . . . . . . . 48
4.20 Comparator Input Offset @ 12.5 MHz across PVT . . . . . . . . . . . 49
4.21 Comparator Inverter DC gain simulation waveforms across PVT . . . . 49
4.22 Comparator Inverter DC gain simulation results across PVT . . . . . . 50
4.23 DFM Coarse code change simulation result:case 1 . . . . . . . . . . . 51
4.24 DFM Coarse code change simulation result: case 2 . . . . . . . . . . . 51
4.25 DFM Initial fine correction code . . . . . . . . . . . . . . . . . . . . . 52
4.26 DFM fine correction code change simulation result . . . . . . . . . . . 52
4.27 DFM Internal variables . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.28 Input signal with 55% Duty cycle . . . . . . . . . . . . . . . . . . . . 53
4.29 Pre-layout Simulation waveforms of close loop coarse correction . . . 54
4.30 Pre-layout simulation waveform after coarse correction . . . . . . . . . 54
4.31 Post-layout simulation waveform after coarse correction . . . . . . . . 54
4.32 Simulation waveforms of close loop fine correction . . . . . . . . . . . 55
4.33 Pre-layout simulation waveform after fine correction . . . . . . . . . . 55
4.34 Post-layout simulation waveform after fine correction . . . . . . . . . . 56
xiv
List of Figures
4.35 Corrected Duty Cycle After Pre-layout Close loop Correction Across
PVT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.36 Corrected Duty Cycle After Post-layout Close loop Correction Across
PVT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
xv
List of Tables
2.1 Working of Basic Analog Architecture . . . . . . . . . . . . . . . . . . 14

2.2 Performance comparison of reviewed Architecture . . . . . . . . . . . 22
2.3 Comparison of Duty Cycle Adjuster Architectures . . . . . . . . . . . . 24
4.1 Performance comparison with Proposed Architecture . . . . . . . . . . 58
xvii
Chapter 1
Introduction
With enhancement in the technology, requirement for high speed data communication
becomes very important. Receiver (Rx) and transmitter (Tx) are the part of physical
layer of the data communication system. To support transfer of data at high data rate (
10gbps) either clock of equal frequency is needed or data can be sampled on both the
edges of clock. It is very difficult to generate stable clock with frequency in terms of
tens of GHz. Thus practical solution is to design a hardware so that it can sample data at
both the edges of clock and transfer rate can be twice of clock frequency. For this pur-
pose half rate clock data recovery (in Rx) / sampling (in Tx) circuit is used. Using both
the edges of clock helps to double the data rate but in this case duty cycle of the clock
becomes very crucial especially when the clock period is several pico seconds.Here
the application for which Duty Cycle Correction(DCC) circuit is designed has clock
frequency of 5.2GHz (clock period=192.3ps, data-rate = 10.4 gbps). In present day
technologies uncertainty margin (time window in which flop may sample false data) of
flops approximately varies from 40 to 80 ps. In case of duty cycle degradation there is
very high chance that data sample by Half clock rate data sampling circuit is incorrect,
this fact is explained in more detail in next section. This false data sampling directly
affects performance of the data communication system. Thus for robust and effective
performance of high speed I/O applications design of DCC circuit is very crucial. Based
on the application, design constrains of DCC varies widely, e.g. Half rate Clock Data
Recovery (CDR) application in high speed serial I/O (10 Gbps) requires DCC with
very high precision (10 20 ps) and correction cycles can be relaxed (DCC settles dur-
ing booting of system). Whereas DCC designed for double sampling ADC expected to
support some frequency range, with optimum hardware and power consumption (Spe-
cially ADC used in SoC). Thus researchers are putting their efforts in designing DCC
with (1) high correction accuracy, (2) less correction time, (3) less chip area, (4) less
power consumption, (5) high frequency/ large frequency range, (6) support high correc-
tion range.
1.1 Importance of DCC

Fig.1.1 shows, for high speed I/O applications DCC is placed before Half rate clock data
recovery/ sampling (recovery in Receiver and sampling in Transmitter) circuit. Duo to
buffers in the clock path duty cycle of the input clock is degraded which is recovered
by DCC circuit before giving to next block as it is using both the edges of clock for
operation. Fig.1.2 shows a clock signal with 5.2 GHz frequency (192.3ps period) and
1
Chapter 1. Introduction
50% duty cycle. It is clear from the figure that setup and hold margin will be same for
both on and off time of the clock. In Fig.1.3 the clocks duty cycle is not 50%, in this
case setup and hold margin is different for both, on and off time. Now this become very
critical when clock frequency is very high. Here clock period is 192.3 ps thus half cycle
period is 96.15 ps, if duty cycle is degraded by 10% then on time equals to 76.92 ps.
Approximative uncertainty margin of flops varies in the range of 40 to 80 ps. Thus with
degraded duty cycle it is quite possible to read false data due to setup or hold violation.
Figure 1.1: DCC inside Transmitter/ Receiver
Figure 1.2: Clock signal with 50% duty cycle
1.2 Cause of Degradation

As the complexity of the digital circuits increases, complexity of clock distribution
network also increases. The main cause of degradation is buffers used in the clock paths.
Mismatch between driving strength of nMOS and pMOS of the buffer changes rising
and falling slopes of the clock signals which eventually results in duty cycle change.
This mismatch is mainly due to manufacturing and process variation. Temperature
variation also plays part in degradation but very less compared to process variation.
2
1.3. Design Parameters
Figure 1.3: Clock signal with duty cycle degradation
1.3 Design Parameters

To design DCC for particular application, these are the parameters given to the designer.
1. Operating Frequency
2. Correction Time (in terms of clock cycles)
3. Correction Accuracy
4. Correction Range
5. Power consumption (Max. allowable)
6. Chip Area (Max. possible chip area)
Fig.1.4 shows that how each parameter is interrelated with all others and creates trade-
off in the design.
Figure 1.4: Design Parameters
3
1.4 Basic Block Diagram

As Shown in Fig.1.5 function of DCC can be divide into two blocks: (1) Duty Cycle
Adjuster (DCA) and (2) Duty Cycle Detector. There are different circuit approaches are
available to implement each function. For Duty cycle adjuster mainly used circuits are
(1) Pulse shrinking/ stretching, (2) Controlled Delay line and (3) Changing DC level.
For Duty Cycle Detection (1) Low pass Filter followed by Comparator, (2) Integrator
followed by comparator, (3) Phase/ Frequency Detector and (4) MUTUX (Mutual Ex-
clusion Element) is used. These all circuit mechanism are discussed in Chapter 2. This
detector circuits generates feedback signal based on which DCA adjust the input clock
signal, this iterative process stops after getting signal with desire accuracy at the output
side.
Figure 1.5: Basic Block Diagram
1.5 Classification
DCC can be classified in to: Digital DCC, Analog DCC and Mixed Mode DCC. This
classification is based on the approach used for implementing DCC. As shown in Fig.1.6
digital DCC can be implement in, with and without feedback. Without-feedback mech-
anism corrects duty cycle with very less correction time but it does not provide correc-
tion against PVT variation and correction accuracy is also less compared to feedback
mechanism. Each approach is discussed in detail in the chapter 2 with performance
comparison.
Figure 1.6: Conventional Classification of DCC
4
1.6. Thesis Contribution
1.6 Thesis Contribution

This thesis work is focused on designing a DCC circuit with high accuracy and correc-
tion time. DCC circuit should be able to correct degradation of 505% to 500.1%.
Here accuracy requirement is high but correction time is more, the aim is to achieve
this with optimum chip area and power consumption across 9 Process, Voltage and
Temperature (PVT) variations.
In [2] concept of coarse and fine delay cells are used in controlled delay line which
results in optimum hardware for higher accuracy. Using this concept to achieve high
accuracy, proposed architecture is with two blocks in DCA block, one for coarse cor-
rection and another is for fine correction. But the duty cycle correction will be done by
changing slope of input clock signal. Important thing is here only one and simple detec-
tion mechanism is used compare to the architecture in [6] which has used two different
feedback path to add fine correction and in [2] with complex detection mechanism like
Phase Frequency Detector (PFD) followed by digital circuits. Digital Feedback Mech-
anism (DFM) in the proposed architecture is designed to achieve the coarse and fine
correction with only one detection mechanism.
In Duty cycle Detection, differential clock has generated from single clock to achieve
high accuracy across PVT variation. Knowing the fact that given correction is in s,
switched capacitor dynamic comparator is used, in which input offset is not introduce
because of mismatch between differential pair of preamplifier used in conventional
comparators. This is a simple circuit consist of two pass gate transistors, a capacitor, an
inverter followed by a latch. Resolution of this comparator circuit purely depends on
the value of capacitor used. The DCC circuit in the thesis is an area and power efficient
solution to achieve below mentioned specifications across 9 PVT variations.
1. Technology : 28nm
2. Simulator : Specter
3. Input Clock Frequency : 5.2 GHz
4. Correction Range: 50 5 %
5. Correction Accuracy: 50 0.1 %
6. Correction Time: 5 s
Correction range parameter for design is calculated based on (i) Possible Degradation
by Process variation and (ii) Possible degradation by manufacturing variation, addition
of both this gives required correction range for DCC.
5
1.7 Organization of thesis

Thesis is organized in four chapters. Chapter 1 is for introduction and basic understand-
ing of DCC circuits.
In chapter 2 varies existing architectures are classified and discussed in detail. Also
summery is presented at the end of chapter which compares performance of several
architectures and indicates that which architecture is more suitable for specific applica-
tion.
In chapter 3 proposed architecture is discussed. It includes limitations of existing
architectures, basic block diagram, in detail explanation of each block, designing of
each block of proposed architecture.
In chapter 4 results are discussed to support all the claims of proposed architecture.
Result of individual blocks and close loop simulation are added.
6
Chapter 2
Literature Review
As shown in section 1.5 DCC can be classified in Digital DCC, Analog DCC and Mixed
Mode DCC. In this chapter varies architectures available for these approaches will be
presented followed by a performance comparison. In all sections a vary basic architec-
ture is discussed first to explain basic working mechanism followed by latest architec-
tures. Chapter is divided in sections based on the classification.
2.1 Digital Duty Cycle Corrector
Most of the digital DCC [1] [7] [2] uses positive edge of input clock and Clock Period of
input clock to generate output clock with 50 % duty cycle. For this approach controlled
delay line is used as DCA. Phase or Frequency detector mainly used as duty cycle
detector. Some circuits [2] uses Time to Digital (TDC) for fast locking. Also latest
proposed architectures [2] [7] are having delay line with coarse and fine tuning which
helps to achieve higher accuracy with lesser chip area and hardware cost. In digital
DCC output clock is phase aligned with input clock [1] [7] [2] [8], thus digital DCC is
more suitable for applications having multiphase phase clocks requirements [8]. Digital
DCC stores the correction code in registers thus when DRAM is being operated in
power-down mode it can hold correction information whereas in analog DCC feedback
voltage to the DCA stored in capacitor which cannot be maintained during power-down
mode.
Digital DCC uses Finite State machine (FSM) in the feedback path which used to
update and store the correction code. Thus applications which support power down
mode (No input clock while circuit is not in use) digital DCC is more suitable compare
to Analog DCC in which feedback signal is usually voltage signal stored in capacitor.
Because when circuit starts again from power down mode, in digital DCC correction
is not required again where as in Analog DCC as feedback voltage gets change due to
discharging of capacitor, correction needed to be done again.
2.1.1 Basic Digital DCC Architecture
Fig. 2.1 shows the basic architecture of digital DCC. This is the most basic architecture
without any additional features like Fast locking, Fine tuning.
7
Chapter 2. Literature Review
Figure 2.1: Basic Architecture of Digital DCC [1]
Figure 2.2: Timing Diagram of basic Digital DCC Architecture [1]
8
2.1. Digital Duty Cycle Corrector
Working Mechanism
From Fig.2.1 and 2.2 it is easy to understand that output of the clock generator (clock
C) block goes high at the rising edge of the input clock. Clock C will be at logic 0 at
the rising edge of clock B. Clock B is delayed version of Clock A. Thus the rising and
falling edge of output clock is controlled by rising edge of input clock. By adjusting
delay of delay line equal to half of the clock period output clock duty cycle set to 50 %.
The duty cycle detector detects the duty cycle of output clock. The delay line used here
is consist of five stage inverters with 4-bit binary weighted NMOS capacitors placed at
the output of each inverter. The delay of each stage is controlled by a 4-bit control signal
coming from the duty cycle detector. The correction range supported by the circuit is
limited by the minimum pulse width that can be passed through the delay line.
2.1.2 Recent Architecture of Digital DCC

DCC Architecture in Fig.2.3 has proposed in 2013 with some new ideas and tried to
make some improvement in convention architecture. These modifications are
1. Use of Delay Recycled architecture which reduces the required length of de-
lay line to (0.5 * Clock period) thus with the same operating frequency, power
consumption and chip area are less compare to conventional circuit.
2. Delay line used with coarse and fine tuning for higher accuracy also tuning range
is set in such a way that delay increases monotonically with increase in control
codes which reduces Jitter at the output clock
3. Balanced rise time and fall time delay line architecture makes it has a high toler-
ance to the unbalanced process variations (SF and FS corners).
Fig.2.3 shows the block diagram of latest Digital DCC. The block diagram composed of
pulse generator (PG), a half-cycle delay line (HCDL), a phase and frequency detector
(PFD), a ADDCC controller, a Time-to-Digital converter(TDC) encoder and a D-Flip-
Flop. The HCDL is composed of a 5-bit fine-tuning delay line (FDL) and a 4-bit TDC-
embedded coarse-tuning delay line (CDL). The total correction range covered by FDL is
always equal to one coarse tuning delay step at all PVT variations. Thus this delay line
always gives a monotonic response between the delay line control code (ctrl code[8:0])
and the output delay.
Working Mechanism
Fig.2.4 shows the overall timing diagram of the proposed architecture. Working of the
architecture is described in the below given steps. After the circuit is reset,
9
Figure 2.3: Recent Architecture of Digital DCC [2]
PG generates the short pulses from the input clock (CLK IN), and the coarse-tuning
control code (ctrl code[8:5]) of the HCDL is set to the maximum value (i.e. 4b1111) at
this cycle. Subsequently, the short pulses propagate through the HCDL.
At the next rising edge of the input clock (CLK IN), the TDC captures the propa-
gated pulse signals and stores as tdc data [15:0].
The signal is half cycle is used to determine if the period of the input clock (CLK IN)
is larger than the maximum delay time of the HCDL.
The TDC encoder will search for the bit location of the first 1 in tdc data[15:0] from
the most significant bit to the least-significant bit.
The TDC encoder outputs the initial delay control code (tdc code[3:0]) for the AD-
DCC controller to achieve fast lock-in.
After setting the initial control code, the proposed ADDCC increases or decreases
the delay line control code (ctrl code[8:0]) according to the PFDs output until the output
clock (CLK OUT) is phase aligned with the input clock (CLK IN).
A binary search scheme is adopt in the ADDCC controller to speed up the fine-
tuning process.
Whenever the PFDs output is changed from UP to DOWN or vice versa, the search
step (step[4:0]) is divided by 2 until the step is reduced to 1.
Once the step is equal to one fine-tuning control code, the ADDCC is locked.
Working at Low Frequency
As shown in Fig.2.5, when input clock period is grater than the maximum delay pro-
vided by the delay line then it is considered as low frequency signal for given archi-
tecture. In this case before coming next rising edge the small pulse propagates through
delay line trigger the DFF then generate the feedback pulse (fb pulse). The signal
is half cycle is pulled high in this case. In Figure 2.5, the first 1 bit location of tdc data
10
2.2. Analog Duty Cycle Corrector
Figure 2.4: Overall Timing Diagram of Latest Digital DCC Architecture [2]
[15:0] from the most significant bit to the least significant bit is 3. Therefore, the period
of the input clock (CLK IN) can be quantized as 20 (=16+4) coarse-tuning delay units
delay time. Since the lock condition is to have half delay than the input clock period,
the tdc code[3:0] outputs by the TDC encoder is 10(=20/2) in this case.
Working at High Frequency
As shown in Fig.2.6,when input clock period is less than the maximum delay provided
by the delay line then it is considered as high frequency signal for given architecture.
In this case small pulse is not able to propagate fully through the delay before the next
rising edge of the input clock signal comes. Thus the signal is half cycle is having value
zero. In Figure 2.6, the first 1 bit location of tdc data [15:0] from the most significant
bit to the least-significant bit is 11. Therefore, the period of the input clock (CLK IN)
can be quantized as 12 coarse-tuning delay units delay time. In addition,to have delay
of delay line equal to half clock period, the tdc code[3:0] is 6(=12/2) in this example.
2.2 Analog Duty Cycle Corrector

Most of Analog DCC [3] [9] uses pulse stretching/shrinking mechanism or offset
cancellation [4] in Duty Cycle Adjuster (DCA). This uses both rising and falling edge
of the input clock signal. Duty cycle detection mechanism is less complex compare to
digital DCC. Integrator [5] or Low pass filter [10] followed by comparator is used for
duty cycle detection. There is no any special mechanism for fast locking so correction
time is purely depends of the degradation of input clock signal and required output
clock signals accuracy. Duty cycle is controlled by changing rise-time and fall-time of
11
Figure 2.5: Timing Diagram at Low frequency of Latest Digital DCC Architecture [2]
Figure 2.6: Timing Diagram at High frequency of Latest Digital DCC Architecture [2]
12
input clock signal thus corrected output signal doesnt hold phase information of input
clock.
2.2.1 Basic Architecture of Analog DCC

Basic architecture for analog DCC is shown in Fig.2.7. As shown in architecture a volt-
age controlled pulse shrinking/stretching delay line is used as duty cycle adjuster. The
buffer is used to convert the single ended signal in differential signal which generates
output clock Q,Qb also increases the output driving capability. These differential sig-
nal passes through differential low-pass filter composed mainly of two resisters, two
capacitors and an operational amplifier to generate feedback voltage Vbias . This Vbias
voltage controls the amount of pulse shrinking/stretching of the delay line to get 50%
duty cycle at the output side.
Figure 2.7: Analog DCC Basic Architecture [3]
Working Mechanism of basic Analog Architecture
Fig.2.8 shows the delay cell with tunable internal rising and falling times for pulse
shrinking/stretching delay line. The transistors M1 and M2 are used to adjust the sourc-
ing current Ip and sinking current In respectively. The pulse shrinking/stretching is done
based on the Value of Vbias . Logical explanation correction mechanism is described in
table 2.1. Dummy transistors M3 and M4 are used to shape the output waveforms.
Waveforms to understand shrinking and stretching mechanism are given in Fig.2.9.
13
Table 2.1: Working of Basic Analog Architecture
Input Clock Vbias Changes Current Changes Final Impact per

Duty Cycle Delay Cell
< 50% Increases Ip Increases, In Decreases tphl > tplh , Shrunk by
W = tphl tplh
> 50% Decreases Ip Decreases, In Increases tphl < tplh , Stretch by
W = tplh tphl
= 50% No Change Ip No Change, In No Change tphl = tplh , No
Change
Figure 2.8: Schematic of delay cell [3]
2.2.2 Recent Architecture of Analog DCC
Fig.2.10 shows latest architecture of analog DCC. This architecture is proposed in 2014.
In this offset cancellation approach is used for duty cycle adjustment. Thus frequency
of input clock is limited only due to loop gain of the architecture. There is a CML-
CMOS buffer is used after DCA to have full swing at the output. Duty Cycle detection
if done by differential Duty Amplifier through which an analog feedback voltage is
generated which is used to set DC level of input clock signal in such a way that after
passing it through CML-CMOS buffer, the output signal should have 50% duty cycle.
14
Figure 2.9: (a)Pulse Stretching Mechanism,(b)Pulse Shrinking Mechanism [3]
Figure 2.10: Recent Analog DCC Architecture [4]
Working Mechanism
Fig.2.11 shows the circuit diagram of the DCA, which is composed of the AC coupled
buffer to reset common mode voltage, the two NMOS differential-pair amplifiers to
correct the input offset and the CMLCMOS buffer. CML-CMOS buffer is simply a level
converter. The Duty Cycle Detection is performed within the differential duty amplifier
which causes the feedback loop architecture to provide high operating frequency, high
15
loop stability, and a wide duty cycle correction range. As shown in Fig.2.12, in order to
track the duty error rapidly, the duty detector is designed with a cross-coupled circuit,
which can increase their isolation, thus improving the duty-correction accuracy and
achieving a large gain bandwidth. This differential duty amplifier and loop filter convert
the duty cycle error of the complementary waveform into offset voltages. The loop filter
outputs the differential voltage which feeds back to the second differential-pair amplifier
in the Duty Cycle Amplifier, and the DCA adjusts the duty cycle error every cycle until
the output duty cycle is balanced at 50%.
Figure 2.11: Duty Cycle Adjuster [4]
Figure 2.12: Duty Cycle Detector [4]
2.3 Mixed Mode Duty Cycle Corrector

As seen in the earlier sections 2.1 and 2.2, both (1) Digital and (2) Analog DCC are hav-
ing some advantages and some disadvantages. In Mixed Mode Duty Cycle Correction
(MMDCC) researchers has focused to combine advantages of both the approaches (e.g.
16
2.3. Mixed Mode Duty Cycle Corrector
higher accuracy and operating frequency of Analog DCC, Fast locking and digitally
saved correction codes of digital DCC).
2.3.1 Basic Architecture of Mixed Mode DCC

Fig.2.13 shows the block diagram of basic architecture of Mixed mode DCC. Here
Controlled delay line is used as duty cycle adjuster, comparator is used as duty cycle
detector whose output will be given to a FSM(SAR controller). This FSMs output
code will control the adjustment provided by DCA. Thus this architecture is made of
both,Analog components (Comparator, controlled delay line) and Digital Components
(SAR controller). This SAR controller adopts binary search algorithm. Whenever con-
trolled delay line is used in any architecture then some additional is used to get maxi-
mum delay with minimum delay line length to reduce chip area and power consumption.
In this architecture an additional sign bit is there in SAR controller and one MUX is
there before delay line in DCA block.
Figure 2.13: Basic Architecture of Mixed Mode DCC [5]
Working Mechanism
Fig.2.14 shows flow chart of working of this architecture. Working can be divided in
to two parts, First it detects whether the duty cycle of the input clock cycle is greater
or less than 50%. Based on this it makes sign bit of SAR controller 0 or 1. Then
according to binary search algorithm SAR controller sets the delay of the delay line to
get 50% duty cycle at the output. Waveforms of working for 6bit SAR controller is
shown in Fig.2.15.
17
Figure 2.14: Flow Chart of Basic Mixed Mode DCC [5]
18
Figure 2.15: Timing diagram of the 6-bit SAR-DCC with input clock duty cycle is
39% [5]
2.3.2 Recent Architecture of Mixed Mode DCC

Fig.2.16 shows the latest architecture presented in 2013. In this Duty Amplifier as Duty
cycle Adjuster, Charge Pump as Duty Cycle Detector. Here Analog as well as digital
both the kind of feedback is used. Level converter is used to convert generate full
swing output clock signal. Duty cycle correction procedure of this architecture is not as
straight forward as the earlier architectures. This procedure is briefly written in terms
of steps here:
1. Analog Feedback loop used for Duty cycle correction
2. Duty cycle correction done by Digital feedback loop by SAR controller using
19
binary search algorithm
3. To provide correction for real time temperature changes, digital feedback loop is
used and SAR controller uses sequential search algorithm.
Figure 2.16: Recent Mixed Mode DCC Architecture [6]
Working Mechanism
As shown in Fig.2.16, feedback path includes dual loop: digital feedback loop and
analog feedback loop. In the analog feedback loop, the charge pump (CP) generates
the analog control voltage Vctrl/Vctrlb based on the duty-cycle of the output clock
(OU TCLK /OU T bCLK ). The control voltage Vctrl/Vctrlb is also used in the digital feed-
back loop to generate the digital control voltage VDctrl/VDctrlb. The digital feedback
loop consists of a comparator, an 8-bit digital-to-analog converter (DAC) and an 8-bit
SAR. The comparator generates the up or down signals depending on the CP outputs.
The operating frequency of SAR clock (SAR CLK) is 1/64 of the input clock frequency
. This slow SAR using binary search scheme gives enough timing margin for the ana-
log charge pump and DAC operation, resulting in wider duty-cycle correction range and
minimized integrated errors in duty-cycle without increasing the lock time. By adapting
binary search algorithm, the digital output Q[7:0] of the SAR is then used for the DAC
input. The 8-bit DAC provides the quantized bias current IDAC/IDACb to generate
20
VDctrl/VDctrlb. The two control voltages, Vctrl/Vctrlb and VDctrl/VDctrlb, are then
used for the DA to correct the clock duty-cycle of the input clock, INCLK/INbCLK.
Figure 2.17: Flow Chart of Latest Mixed Mode DCC Architecture [6]
The Duty Amplifier corrects external differential input clock signals with duty-cycle
distortions and generates a small-swing 50% duty-cycle clock as output. The level
converter, which converts a small swing to full-swing, produces a full-swing output
clock signal, (OU TCLK /OU T bCLK ).
When the DCC is enabled, the digital and analog feedback block starts together.
Since the analog feedback block has a fast duty-correction capability by increasing the
gain of the CP , the output clock duty-cycle is corrected to 50% in about only 40 clock
cycles in this design. Then the digital feedback block with an initial value of the 8-bit
SAR Q[7:0]=[10000000] slowly replaces the analog feedback block.
Fig.2.17 shows the flowchart of the mixed search (binary + sequential) algorithm.
At the end of the binary search mode, the DCC enters into the sequential search mode
automatically . By converting the binary search SAR into a sequential search counter
after the first DCC lock-in, this architecture keeps the closed-loop characteristic and
21
tracks variations due to PVT variations.
2.4 Performance Comparison

Table 2.2 shows performance comparison of above discussed architectures.
Table 2.2: Performance comparison of reviewed Architecture
Parameters Architecture
- Basic Recent Basic Recent Basic Recent
Digi- Digi- Ana- Ana- Mixed Mixed
tal [1] tal [2] log [3] log [4] Mode [5] Mode [6]
CMOS 180nm, 90nm, 1V 350 nm 55 nm, 130 nm, 180nm,
Technol- 1.8V 1.2V 1.2 V 1.8V
ogy
Correction 20%-80% 20%-80% 30%-70% 20%-80% 40% - 15% -
Range 60% 85%
Duty Cy- 500.25% 1.4 @ 450 501% 500.1% 501% 500.86%
cle Error MHz, 1.9 @ 2 Ghz
@ 1 GHz
Operating 0.8-1.7 450 Mhz - 3 Mhz - 1 - 5 Ghz 312.5 0.5 - 2
Fre- Ghz 1GHz 660 MHz Mhz - GHz
quency 1Ghz
Power 3.2 mW 1.7 mW 1.1 mW 3.6 mW 3.2 mW 3.8 mW
Con- @ 450 @ 3 Ghz @ 1GHz @ 1 Ghz
sumption Mhz, 3.45
mW @ 1
GHz
Chip 100m x 0.0049 0.06 mm2 0.00174 0.048 0.075
Area 75m mm2 mm2 mm2 mm2
2.5 Architecture Summary

From the architectures discussed in the above section it can be said that different DCC
architectures are suitable for different applications. Duty cycle adjuster (DCA) is the
most critical design part to meet correction range and accuracy. Objective of DCC
22
2.5. Architecture Summary
circuits used in high speed I/O are designed to get high accuracy with minimum chip
area and power consumption. Thus DCA architecture design plays an important role.
Table 2.3 shows brief summery of various DCA architectures used in DCC circuits
discussed in this chapter.
After reviewing several architecture it can be concluded that for high precision duty
cycle correction circuit, DCA block should be designed to meet below specifications.
Different mechanisms for Course and Fine Correction with only one type of feed-
back. (To have optimum chip area)
Design should have minimum variation across PVT variations (less sensitive to
PVT variations)
Tight control on correction step size.
23
Table 2.3: Comparison of Duty Cycle Adjuster Architectures
Architecture Parameters
- Duty Cycle Fine & Conclusion
Adjuster Coarse
Mechanism Correc-
tion
Basic Digi- Controlled De- No DCC mainly delays rising/falling edge
tal [1] lay line of input clock, thus Delay line is prefer-
able for Digital DCC
Advance Digi- Controlled De- Yes Important concept of Separate Coarse
tal [2] lay line and Fine delay line is used. This can be
also applicable to other DCA architec-
ture
Basic Ana- Pulse Stretch- No Feedback mechanism is analog in na-
log [3] ing/Shrinking ture thus highly sensitive to supply
Delay Line voltage noise when designed very high
precision. Correction accuracy is less
Advance Ana- Duty Ampli- No Extra CML to CMOS buffer required,
log [4] fier To support high Frequency device
width needed to keep high to increase
bandwidth of the amplifier. Analog
feedback is highly sensitive to sup-
ply noise, No support for power down
mode.
Basic Mixed Controlled De- No No mechanism for coarse and fine tun-
Mode [5] lay Line ing. Correction accuracy is less. More
suitable for application with less accu-
racy and correction time
Advanced Duty Ampli- Yes Two different feedback mechanism are
Mixed fier used to add fine and coarse correction
Mode [6] which increases chip area, no support
for power down mode. To support
high frequency, bandwidth of amplifier
should be high which increases chip
area
24
Chapter 3
Proposed Architecture
As presented in sections 2.4 and 2.5, highest accuracy obtain by existing DCC architec-
tures is 1ps that is also without considering PVT variations. But as per specifications
required accuracy is 0.192 ps across 9 PVT variations. To meet this accuracy, DCA
mechanism should have very tight control and feedback path must able to sense duty
cycle error up to 500.1%. In chapter 2, 6 different DCC architectures has been dis-
cussed with their advantages and limitations. From literature review it is clear that
Mixed mode architectures include advantages of both, Analog and Digital DCC which
enables to have high accuracy with less hardware, better control on feedback etc. Thus
the proposed architecture is also a Mixed mode DCC where Correction mechanism is
analog with digital feedback as shown in Fig.3.1. The proposed architecture includes
some important observations from existing architectures addition to that design level
modifications to meet specifications. The architecture has following properties.
DCA with Coarse and fine correction mechanism.
single to differential block
1. To generate differential symmetric clock signals

2. For proper shaping of output signal of DCA
Comparator with offset value less than 2 mV
Digital feedback mechanism to provide feedback based on the comparators out-

put.
3.1 Duty Cycle Adjuster

Fig.3.2 shows block diagram of DCA. There are two blocks inside DCA, one is for
coarse correction and second is for fine correction. DCA is used to correct duty cycle
degradation from 45-55 % with accuracy of 50 0.1 %. Coarse Correction circuit cor-
rects duty cycle degradation up to 501% and covers range of 505%. Fine correction
circuit corrects duty cycle degradation up to 500.1% and covers range of 501%.
This mechanism of using two separate circuits for coarse and fine correction makes
this design area efficient. Next subsection will describe circuit level presentation and
design.
25
Chapter 3. Proposed Architecture
Figure 3.1: Block Diagram of Proposed Architecture
Figure 3.2: DCA block diagram
26
3.1. Duty Cycle Adjuster
3.1.1 Coarse Correction Circuit

Fig.3.3 shows circuit for coarse correction. Here pMOS transistors M3,M5-M10 and
nMOS transistors M4,M11-M16 act as current source whereas M1 and M2 work as
switch. In this configuration (W/L) ratios of M5-M10 (M11-M16) are in binary weighted
fashion. Designing (W/L) of these transistors is an iterative process which is described
in detail in next subsection. This coarse correction circuit design can varies widely,
values of (W/L) of pMOS (nMOS) depends upon value of load capacitor. Because
cload cload
tphl (W/L) and tplh (W/L) .
Number of pMOS (nMOS) depends upon correction accuracy and correction range.
Ideal calculation can be done in this way. From the information of correction range
and accuracy decide number of steps required. E.g. if correction range is 505% and
accuracy is 501%. In this 5 steps are required to cover the correction range. 5 is
greater than 22 = 4 thus number of pMOS (nMOS) required is 3. This is an optimistic
calculation when only one PVT is there. To meet the specification in post layout results
and across various PVT corners calculation can be done as described below.
In the proposed design, for pre-layout simulations correction accuracy per step is
kept as 0.4% of 192.3 ps = 0.77ps for slow corner (To ensure that design will meet
specification in post-layout and montecarlo simulations ). For this step size in slow
corner, fast corner step size is 0.2% of 192.3 ps 0.38 ps (refer results in Fig. 4.2).
Correction accuracy and range must meet for all PVT corners, ideally 25 (practically
it may take more as current may not increase linearly with increment in (W/L)) steps
are needed for fast corner to meet correction range of 505%. Which are greater than
16, thus need to have < 5 : 0 > control signal. Similar calculation is applicable to fine
correction block.
Design Procedure
In this section design steps of DCA is described. Also dependency of correction range
and accuracy depends on circuit elements. In Fig.3.3 transistors M1 and M2 are act
as switches and other will act as current sources. Though this current is not constant
throughout charging and discharging of load capacitor. But (W/L) of these transistors
can be approximated by calculating average current, then after more accurate value
can be derived from simulations. Here the first thing to be decided is the correction
step size which means how much correction is required per code change, from the
specification of step size and correction range, number of MOSFETs required to use as
current source can be determined. While designing for 9 PVT variations, design should
meet specifications for worst case corner. For same (W/L) ratio rise and fall slopes
and thus delay will be the highest for slow corner and the lowest for fast corner. Thus
27
Figure 3.3: Coarse Correction Circuit
for the specification of step size, slow corner is the worst case and for the correction
range, fast corner is the worst case. In the present design 6 pMOS (nMOS) are used
thus total 26 = 64 steps to cover the correction range of 505%. Further design steps
are mentioned below.
1. Fix value of load capacitor.
2. Calculation for sizing of M3(M4) can be done by knowing the fact that when
control code is maximum (111111b) only M3 is on. Thus value of low to high
delay Tplh for M3 = 192.35
100
= 9.615ps. This value should be placed in (3.5) to
find equivalent value of average current. For a given size,voltage and temperature,
fast corner has minimum value of slope and thus delay. So this calculation should
be done for fast corner MOSFET. For M4, same procedure is required except one
needed to consider high to low delay of 3.4.
Q = Cload V out (3.1)

Current
dQ dV out
Iaverage = = Cload (3.2)
dt dt
Where
Iaverage = [I(vout = 20%vcc) + I(vout = 80%vcc)]/2 (3.3)
3. To calculate (W/L) of M16 to M11 (M10 to M5) first calculate for M16 (M10),
for which procedure is mentioned below. In DCA, Duty cycle is adjusted by
28
3.2. Single to Differential
changing High to low delay (Tphl ) and low to high delay (Tplh ). Original clock
signal is with 20ps rise and fall slope. Tphl and Tplh can be change according to
(3.4) and (3.5). Here Tr and Tf are accordingly rise and fall time of input clock
signal. q
2
Tphl = Tphl (stepi nput) + (Tr /2) (3.4)
q
2
Tplh = Tplh (stepi nput) + (Tf /2) (3.5)
2 Cload
Tphl (stepi nput) = (3.6)
[I(vout = vcc) + I(vout = 50%vcc)]
2 Cload
Tplh (stepi nput) = (3.7)
[I(vout = 0) + I(vout = 50%vcc)]
For coarse correction circuit total 26 = 64 correction steps are there to cover
505%. Size of M1 and M2 are large enough compare to M11 to M16 (M5
to M10) thus when both are on, approximate equivalent (W/L) will be equal to
(W/L) of M11 to M16 (M5 to M10). Now to calculate (W/L) for M16, it is clear
192.3ps 5%
that it should provide Tphl = = 0.3ps. For this value of Tphl
32
find average current from (3.4) and (3.5). Find (W/L) from the average value of
current.
4. To set (W/L) of M1 and M2, One thing should be consider that it must be capable
enough to handle, current coming from M11 to M16 (M5 to M10). Thus it can
be set as equivalent (W/L) of M11 to M16 (M5 to M10).
3.1.2 Fine Correction Circuit

Fig.3.4 shows circuit diagram for fine correction circuit. From design perspective, pro-
cedure is same as equally weighted coarse correction circuit. The only change here is
this circuit is to cover 501% range with accuracy of 500.1%. Thus for design of
192.3 1%
M4 (M3), value of Tphl = = 0.096ps.For this value of Tphl find average
20
current from 3.4 and 3.6. Find (W/L) from the average value of current. Sizing M1,
M2, M5 and M6 is done using same way as Binary weighted coarse correction circuit.
Waveform in Fig.3.5 gives basic idea about working of DCA.
3.2 Single to Differential

Fig.3.6 shows block diagram of single differential. This block is design to fulfill below
mentioned purposes.
29
Figure 3.4: Equally weighted Coarse Correction Circuit
Figure 3.5: DCA waveform
30
3.3. Low pass filter
Generate differential clock from single clock.
Shaping output signal of DCA block to use as clock at Half rate clock data recov-
ery/sampling circuit.
To meet these specifications, circuit diagram is shown in Fig.3.7. Here back to back
inverters are used as output stage to get very sharp edges. Here positive feedback in
back to back inverter causes fast charging and discharging thus output signal slope will
be sharp. Basic function of this block can understood by the waveform in Fig.3.8.
Figure 3.6: single to differential
Figure 3.7: single to differential circuit
3.3 Low pass filter

RC low pass filter is common circuit used in pulse width modulation (PWM) to generate
DC value according to duty cycle. From circuit perspective it is very simple arrange-
ment as shown in Fig.4.17 . Value of resistor and capacitor is decided based on below
parameters.
Accuracy
Response time
31
Figure 3.8: single to differential waveform
Ideal value of RC is , but it also take time to response change in the duty cycle.
Thus it is always a trade-off between these two parameters. Cutoff frequency of a first
order RC filter is given by 3.8.
1
fc = (3.8)
2RC
Here operating frequency is very high and correction frequency is 12.5 Mhz thus RC
value is kept large enough to get accuracy of 500.1%.
Figure 3.9: Low Pass Filter
3.4 Comparator
Design of comparator plays important role in achieving high accuracy. Comparator is
very important circuit used in many applications like ADC. Below are the specifications,
32
3.4. Comparator
required for comparator design.
Input offset (Resolution)
Response time (Operating frequency)
Power consumption
Chip area
Output of comparator is given to digital feedback system which is a clock driven circuit,
thus dynamic comparator is more suitable for this application which also works on clock
to save static power consumption. Dynamic comparator based on switched capacitor are
very simple in design and consume less chip area. As the major duty cycle correction
done by the DCC circuit is performed during initialization of the hardware which takes
time in microseconds. Thus For whole coarse correction available time is approximately
5s. Thus operation speed of comparator can be several MHz. But input offset should
less enough to sense difference of vcc(mV)1%.
3.4.1 Design of Dynamic Comparator Circuit

Fig.3.10 shows a dynamic comparator based on the inverter. Here 0, 1 and 2 are
non-overlapping clocks.
When 0 is high (Reset), the voltage on the vn input is connected to node A, while
the voltage on Node B is set via M3 so that input and output voltage of inverter are
equal.During this the inverter is acting as an linear amplifier where both M1 and M2
are operating in saturation regions. When 1 goes high (Pre-charge), the vp input is
connected to Node A. If Capacitor C is much larger than the input capacitance of the
inverter (Cg ) then the voltage change on the input of the inverter is vin = vp vn .
Provided the gain of the inverter is large, this change causes the inverter output to rail,
that is, either VDD or ground. The output will be latched when 2 is high (Evaluation).
This all waveforms are plotted in Fig.3.11.
Typical comparator circuit consist of an amplifier stage, which is used to amplify
input signals to increase sensitivity of comparator. But the mismatch in the amplifier
circuit will create input offset. But this configuration uses capacitor to sense difference
between inputs. Thus to achieve high accuracy capacitor value should be high. Here is
the trade off between operating frequency, chip area and accuracy. This configuration
is suitable for medium operating frequency, high accuracy with optimum chip area.
33
Figure 3.10: Dynamic Comparator
Figure 3.11: Comparator Working
3.5 Digital Feedback Mechanism

Digital feedback mechanism(DFM) is used to control DCA block based on the output
of comparator. Working of the DFM can be understood from the flowcharts in section
3.6. Implementation of DFM is done in veriloga. Block level RTL is given in Fig.3.12.
FSM block carry the logic that initially coarse correction codes should vary and after
completion of coarse correction, fine correction codes should vary. Coarse and fine
correction counter blocks have select signal (SE). Selection is done by FSM block.
Coarse correction counter is initialized with binary value 100000b. Fine correction
counter is initialized with value 01010b.
During coarse correction if comparator output is logic 0 then, DEB signal of FSM
set to logic 1, which results in decrement by 1 in coarse correction counter. If compara-
34
3.6. System Level Working
tor output is logic 1 then, INB signal of FSM set to logic 1, which results in increment
by 1 in coarse correction counter.
During fine correction if comparator output is logic 0 then, INT signal of FSM
set to logic 1, which results in increment by 1 in fine correction counter. If comparator
output is logic 1 then, DET signal of FSM set to logic 1, which results in decrement
by 1 in coarse correction counter.
Binary to Thermal block converts fine correction codes from binary to thermal code.
Thus one extra block is required to generate thermal codes. Fine correction gives high
accuracy and control on correction. To control then thermal codes are required. But
to generate thermal codes one additional block is required in DFM. Thus in the main
design only fine correction block is controlled by thermal code whereas binary codes
are used for fine correction.
Figure 3.12: DFM block level RTL
3.6 System Level Working

To have clear understanding regarding working of the proposed architecture, flowcharts
are presented in this section. Fig.3.13 shows very basic flow chart which shows how
working of proposed architecture is divided in two parts: Coarse correction and Fine
Correction. Coarse correction is against process and manufacturing variations and fine
correction is against temperature variations after hardware initialization. Duty cycle
degradation due to process and manufacturing variation is larger compare to tempera-
ture variations thus to correct duty cycle for part 1 the correction in each iteration is
high.During this correction procedure output clock does not feed to the main appli-
35
cation block. Thus this correction take place during startup of the system. After this
correction, architecture tries to correct duty cycle as best as it can, during this procedure
BFM uses thermal code to control duty cycle adjustment, change in the duty cycle per
iteration is also very small compare to part 1. During this correction the output clock is
feeding to the main application block, this adjustment helps to correct duty cycle caused
by any temperature changes.
Figure 3.13: Basic Flowchart of Proposed Architecture
Coarse correction in Proposed Architecture
Fig.3.14 shows working of architecture when used to correct duty cycle against process
and manufacturing variations. Initially all codes are set at the middle values of its
range. One counter is used in the DFM which helps in deciding the end of correction
procedure of part 1. When clock signal arrives at the input of DCC in the first iteration it
get adjusted based on the middle codes, this adjusted clock signal passes through single
to differential block which generates two clock one is the buffered version of the clock
at its input and other is inverted version of it. It also helps in shaping slope at the output
side. These clock signals are given to differential low-pass filter (LPF), made up of
series combination of resister and capacitor. This differential LPF gives average values
of the input clock signals which will be fed to comparator. If input clocks duty cycle
is less than 50% then comparators output will be logic zero else one which goes as an
input to DFM. Working of DFM is described in Fig.3.14. When duty cycle reaches less
than 1 step resolution, comparators output start toggling in 0101 pattern. When such
behavior repeats successively 4 times then coarse correction stops.
36
3.6. System Level Working
Figure 3.14: Flowchart of Coarse Correction Mechanism
37
Fine correction in Proposed Architecture
Proposed architecture is also facilitated to correct duty cycle degradation caused by

temperature variation. In Fig.3.1 there are two correction blocks inside DCA. The sec-
ond block is used to adjust duty cycle for this case. Thermometric code is used by DFM
to control this adjustment. This is a continuous iterative process. The flowchart for this
correction process is shown in Fig.3.15.
Figure 3.15: Flowchart of Fine Correction Mechanism
38
Chapter 4
Results and Summery
In this chapter simulation results are discussed to support performance of the proposed
architecture. Simulation results of individual design block is discussed first then close
loop simulation results are mentioned.
4.1 Duty Cycle Adjuster

As discussed in chapter 3, DCA consist of two circuit blocks, one for coarse and other
is for fine correction. For coarse correction two different mechanism are used. In sub
sequent sections results of all the blocks with waveform are presented.
4.1.1 Coarse Correction

This section contents result to support performance of coarse correction circuit. To
check functionality of coarse correction block, a signal with 50% duty cycle should be
applied at the input side, then control codes should be vary from minimum to maximum
code, from this we can have idea about correction range and accuracy.
Coarse Correction Circuit
In this section, graphs and waveforms are presented of pre and post-layout simulations.
Fig.4.1 shows pre-layout result summery across 9 PVT corners. Objective of the circuit
is to meet 505% correction range across PVT variations. From Fig.4.1 it is clear
that in pre-layout simulations circuit is meeting specifications and worst case corner is
FF FFF PR,0C,1.05V. Fig.4.2 shows result summery for post-layout simulation.
Fig.4.3 shows duty cycle change when minimum control code (0) is used. It is clear
that at this code all the pMOS are on and all nMOS are off (except nenable nMOS) thus
rising edge have very less slope and falling edge having large slope value which results
in duty cycle increment. Thus if in close loop when duty cycle of the signal is needed
to be increase then control code should be decrease towards minimum code.
Fig.4.4 shows duty cycle change at mid code. From this it can be observed that when
code is set to mid code the duty cycle is near about 50%. From design it is expected that
for this code if the input duty cycle is 50% then out duty cycle should be about 501%.
In Fig.4.4 on time period is 95.47 ps which means duty cycle is 49.64% , which is in
the allowable range.
39
Chapter 4. Results and Summery
Fig.4.5 shows duty cycle change when maximum code (63) is used. It is clear that at
this code all the nMOS are on and all pMOS are off (except penable pMOS) thus rising
edge is having large slope value and falling edge is with very sharp slope. Which results
in decrement of duty cycle. Thus if in close loop when duty of the signal is needed to
be decreased then control code should be increased towards maximum value.
Figure 4.1: Binary Weighted Coarse Correction Pre-layout result
Figure 4.2: Binary Weighted Coarse Correction Post-layout result
40
4.1. Duty Cycle Adjuster
Figure 4.3: Binary Weighted Coarse Correction min code Post-layout waveforms
Figure 4.4: Binary Weighted Coarse Correction mid code Post-layout waveforms
Figure 4.5: Binary Weighted Coarse Correction max code Post-layout waveforms
4.1.2 Fine Correction Circuit

Fine correction circuit is used to correct duty cycle up to 500.1% and covers range of
501%. Fig.4.6 shows pre-layout simulation result summery. Pre-layout circuit is able
to meet specifications of correction range and accuracy across 9 PVT variations. Fig.4.7
41
presents post-layout simulation result summery. Fig.4.8 present waveforms of duty

cycle change at minimum code. Fig.4.9 and Fig.4.10 presents post-layout waveform of
duty cycle change at mid and max code respectively. Same as coarse correction circuit
in fine correction, decrement codes towards zero to increase duty cycle and vica versa.
Figure 4.6: Fine Correction Across PVT pre-layout simulation result summery
4.2 Single to Differential
Single to differential block is used to serve two purposes. First is to generate differ-
ential clock from single ended clock and second is to shape the output clock signal.
Fig.4.11 and Fig.4.12 present pre-layout and post-layout simulation results summery
respectively. Here it can be observed that slope of the output clock signal is very sharp
and almost equal for both the clocks. Fig.4.13 shows waveforms of post-layout simula-
tion across PVT. Fig.4.14 and Fig4.15 shows measurement using waveform for pre and
post-layout simulation.
42
Figure 4.7: Fine Correction Across PVT post-layout simulation result summery
Figure 4.8: Fine Correction min code Post-layout waveforms
43
Figure 4.9: Fine Correction mid code Post-layout waveforms
Figure 4.10: Fine Correction max code Post-layout waveforms
44
Figure 4.11: s2d across PVT pre-layout simulation result
Figure 4.12: s2d across PVT post-layout simulation result
45
Figure 4.13: s2d post-layout waveforms across PVT
Figure 4.14: s2d pre-layout waveforms measurement
Figure 4.15: s2d post-layout waveforms measurement
46
4.3. Low Pass Filter
4.3 Low Pass Filter

Low pass filter (LPF) generates dc voltage equivalent to input clock signals duty cycle.
Fig.4.16 shows output of LPF when duty cycle of non inverted signal is 44.01% and
inverted signal is 55.48%. Output of LPF is 440.7 mV and 553.4 mV. Fig.4.17 shows
output of LPF when duty cycle of non inverted signal is 49.49% and inverted signal is
49.97%. Output of LPF is 494.9 mV and 499.2 mV.
Figure 4.16: Low pass filter simulation result at beginning
Figure 4.17: Low pass filter simulation result after correction steps
4.4 Dynamic Comparator

As discussed in chapter 3, dynamic switched capacitor comparator is used. Working
mechanism of this comparator is discussed in section 3.4.1, Fig4.18 is the circuit simu-
lation waveform to support working of the comparator. Fig.4.19 shows the simulation
mechanism used for Input offset (resolution) measurement of the comparator. Fig.4.20
47
shows simulation results of offset measurement across PVT. Maximum offset is less
than 1 mV, which is the required resolution to achieve 0.1% accuracy.
In the inverter comparator design, inverter acts as linear amplifier during evaluation
thus it should have enough DC gain to produce rail to rail output. Fig.4.21 shows
waveform of inverter gain across PVT and Fig.4.22 shows result summery in graph.
Figure 4.18: Comparator Working Mechanism
Figure 4.19: Comparator Working at 12.5 MHz
48
4.4. Dynamic Comparator
Figure 4.20: Comparator Input Offset @ 12.5 MHz across PVT
Figure 4.21: Comparator Inverter DC gain simulation waveforms across PVT
49
Figure 4.22: Comparator Inverter DC gain simulation results across PVT
4.5 Digital Feedback Mechanism
Digital feedback mechanism(DFM) is used to control DCA circuit based on the out-
put of comparator. Working of DFM is presented in flowcharts of section 3.6. While
designing DFM for coarse correction, one important thing should be kept in mind that
coarse correction stage have a fine correction stage directly connected at the load end.
These both the stages generates inverted results of its input signal with change in the
duty cycle. Thus the signal going at the input of coarse correction will pass through
fine correction block before single to differential block. This fact should taken in to
consideration while designing DFM.
Thus for coarse correction block if duty cycle of input signal is needed to increase
then correction code also needed to increase and vice-versa. But for fine correction it is
exactly opposite from the coarse correction that is to increase duty cycle of input signal
correction code should be decreased and vice versa.
Fig.4.23 shows coarse code initialization and change with respect to comparator
output. Fig.4.24 shows coarse correction code change when comparator output in in-
verted from Fig.4.23. From these figures it can be observed that coarse code initialize as
mid code (32) and it changes till 0101 or 1010 pattern take place at comparator output.
50
4.5. Digital Feedback Mechanism
Figure 4.23: DFM Coarse code change simulation result:case 1
Figure 4.24: DFM Coarse code change simulation result: case 2
As coarse correction code freezes, further correction is done by fine correction

block. Fig.4.25 shows that fine correction code is also initialize with mid code (10)
and remain constant still coarse correction mechanism stops. Fig.4.26 shows change
in fine correction code as per comparator output. The important note discussed in the
beginning about direction of change in correction codes to increase or decrease duty
cycle is opposite for coarse and fine correction blocks, this fact can be observed from
Fig.4.23 and Fig.4.26.
51
Figure 4.25: DFM Initial fine correction code
Figure 4.26: DFM fine correction code change simulation result
Fig.4.27 shows change in the internal design variables with respect to comparator
output.
52
4.6. Close loop Simulation Results
Figure 4.27: DFM Internal variables
4.6 Close loop Simulation Results
This section presents close loop simulation results of DCC circuit. Working and simu-
lation results of individual blocks has discussed in chapter 3 and 4. In this section graph
and waveforms of the simulation results are presented to support design of DCC circuit.
Fig.4.28 shows input signal with 55% duty cycle. Fig.4.29 shows how coarse correction
take place in close loop. Initially comparator output is zero only because it is reset at
the beginning. As comparator output is one, to decrease duty cycle, coarse correction
codes are also decreasing as discussed in section 4.4. After Detecting 1010 pattern at the
comparators output coarse correction codes are frozen. Fig.4.30 and Fig.4.31 shows
the duty cycle of the output signal after coarse correction for pre-layout and post-layout
respectively.
Figure 4.28: Input signal with 55% Duty cycle
53
Figure 4.29: Pre-layout Simulation waveforms of close loop coarse correction
Figure 4.30: Pre-layout simulation waveform after coarse correction
Figure 4.31: Post-layout simulation waveform after coarse correction
54
4.6. Close loop Simulation Results
Further correction is done by fine correction circuit. Fig.4.32 shows how fine cor-
rection has taken place in close loop simulation. As during coarse correction only duty
cycle of the clock signal has reached near about 50%, fine correction code has also
started toggling very early. In the case when result of coarse correction is not near to
50% then it takes few more steps before toggling around a specific code. In real situa-
tions, duty cycle degradation also happens due to ambient temperature variation at that
time this fine correction correct the degradation and gives clock signal with allowable
degradation. Fig.4.33 and Fig.??hows output signal duty cycle after fine correction.
Figure 4.32: Simulation waveforms of close loop fine correction
Figure 4.33: Pre-layout simulation waveform after fine correction
55
Figure 4.34: Post-layout simulation waveform after fine correction
Finally Fig.4.35 and 4.36 shows corrected Duty cycle across PVT variations for
pre-layout and post-layout respectively.
Figure 4.35: Corrected Duty Cycle After Pre-layout Close loop Correction Across
PVT
56
4.7. Performance Comparison
Figure 4.36: Corrected Duty Cycle After Post-layout Close loop Correction Across
PVT
4.7 Performance Comparison

Table 4.7 presents comparison of proposed architecture with the existing architectures.
As DFM block is written in Variloga and not synthesized power consumption and chip
area of DFM cant be calculated. In all the existing architectures, recent analog archi-
tecture [4] gives the best performance in terms of power delay product and chip area.
The DFM block in the proposed architecture is operating at 12.5 Mhz, thus power con-
sumption of the block will not be dominating. Without DFM proposed architecture has
1.4 times less power delay product number with respect to [4]. In case of chip area
without DFM, proposed architecture has 3 times less chip area from [4]. Thus proposed
architecture has big difference from the best existing architecture which will be surely
decreased if synthesized DFM is used for simulation.
57
Table 4.1: Performance comparison with Proposed Architecture
Parameters Architecture
- Basic Recent Basic Recent Basic Recent Proposed
Digi- Digi- Ana- Ana- Mixed Mixed Architec-
tal [1] tal [2] log [3] log [4] Mode Mode ture
[5] [6]
CMOS 180nm, 90nm, 350 nm 55 nm, 130 nm, 180nm, 28nm, 1V
Technol- 1.8V 1V 1.2V 1.2 V 1.8V
ogy
Correction20%- 20%- 30%- 20%- 40% - 15% - 45% -
Range 80% 80% 70% 80% 60% 85% 55%
Duty Cy- 500.25% 1.4 @ 501% 500.1% 501% 500.86% 500.1%
cle Error 450 @ 2 Ghz @ 5.2
MHz, GHz
1.9 @ 1
GHz
Operating 0.8-1.7 450 Mhz 3 Mhz 1 - 5 Ghz 312.5 0.5 - 2 5.2 GHz
Fre- Ghz - 1GHz - 660 Mhz - GHz
quency MHz 1Ghz
Power 3.2 mW 1.7 mW 1.1 mW 3.6 mW 3.2 mW 3.8 mW 4.474mW
Con- @ 450 @ 3 Ghz @ 1GHz @ 1 Ghz @ 5.2
sumption Mhz, GHz
3.45
mW @ 1
GHz
Power 1.88 3.45 1.67 1.2 3.2 3.8 8.60
Delay 1012 1012 1012 1012 12
10 Ws 12
10 Ws 13
10 Ws
Product Ws Ws Ws Ws
Chip 0.075 0.0049 0.06 0.00174 0.048 0.075 0.000579
2
Area mm mm2 mm2 mm2 mm2 mm2 mm2
58
Conclusion and Future Scope
From the results presented in chapter 4 it can be concluded that the proposed design is
meeting the design specifications very closely in post-layout simulations and exactly in
pre-layout simulations for 9 PVT variations. The purpose of the proposed architecture
is to design DCC circuit with high precision and correction time is high (5s).Different
circuits used for fine and coarse correction in DCA results in high accuracy with opti-
mum chip area. From performance comparison table it can be concluded that proposed
architecture gives highest correction accuracy with least power delay product and chip
area.
In future while designing DCC circuit for higher than 5.2 GHz frequency, it is really
critical to attend such high accuracy across PVT variations. Thus some new mechanism
should be designed which does not depended on clock frequency. The feedback mech-
anism used here is quite suitable for high accuracy provided correction time is in s.
In this design fine correction code always toggles even there is no change in the duty
cycle, this introduces jitter in the output clock signal, thus DFM should be modified in
such a way that fine correction code should vary only when there is more than on step
size degradation in the clock signal.
59
References
[1] Y. Jang, S. Bae, and H. Park, Cmos digital duty cycle correction circuit for multi-
phase clock, Electronics Letters, vol. 39, no. 19, pp. 13831384, Sept 2003.
[2] C.-C. Chung and C.-J. Li, A low-power delay-recycled all-digital duty-cycle cor-
rector with unbalanced process variations tolerance, in VLSI Design, Automation,
and Test (VLSI-DAT), 2013 International Symposium on, April 2013, pp. 14.
[3] P. Chen, S.-W. Chen, and J.-S. Lai, A low power wide range duty cycle corrector
based on pulse shrinking/stretching mechanism, in Solid-State Circuits Confer-
ence, 2007. ASSCC 07. IEEE Asian, Nov 2007, pp. 460463.
[4] Y. Qiu, Y. Zeng, and F. Zhang, 1-5 ghz duty-cycle corrector circuit with wide
correction range and high precision, Electronics Letters, vol. 50, no. 11, pp. 792
794, May 2014.
[5] Y.-J. Min, C. hui Jeong, K.-Y. Kim, W. H. Choi, J.-P. Son, C. Kim, and S. won
Kim, A 0.31 - 1 ghz fast-corrected duty-cycle corrector with successive approx-
imation register for ddr dram applications, Very Large Scale Integration (VLSI)
Systems, IEEE Transactions on, vol. 20, no. 8, pp. 15241528, Aug 2012.
[6] S. Han and J. Kim, A 0.5 2.0 ghz dual-loop sar-controlled duty-cycle corrector
using a mixed search algorithm, vol. 13, no. 2, pp. 152156.
[7] R. Swathi and M. Srinivas, All digital duty cycle correction circuit in 90nm based
on mutex, in VLSI, 2009. ISVLSI 09. IEEE Computer Society Annual Symposium
on, May 2009, pp. 258262.
[8] J. Ha, J. Lim, Y. Kim, W. Jung, and J. Wee, Unified all-digital duty-cycle and
phase correction circuit for qdr i/o interface, Electronics Letters, vol. 44, no. 22,
pp. 13001301, October 2008.
[9] L. Raghavan and T. Wu, Architectural comparison of analog and digital duty
cycle corrector for high speed i/o link, in VLSI Design, 2010. VLSID 10. 23rd
International Conference on, Jan 2010, pp. 270275.
[10] T.-H. Lin, C.-C. Chi, W.-H. Chiu, and Y.-H. Huang, A synchronous 50% duty-
cycle clock generator in 0.35m cmos, Very Large Scale Integration (VLSI) Sys-
tems, IEEE Transactions on, vol. 19, no. 4, pp. 585591, April 2011.
[11] C.-C. Chung, D. Sheng, and S.-E. Shen, High-resolution all-digital duty-cycle
corrector in 65-nm cmos technology, Very Large Scale Integration (VLSI) Sys-
tems, IEEE Transactions on, vol. 22, no. 5, pp. 10961105, 2014.
61
References
[12] R. Mehta, S. Seth, S. Shashidharan, B. Chattopadhyay, and S. Chakravarty, A

programmable, multi-ghz, wide-range duty cycle correction circuit in 45nm cmos
process, in ESSCIRC (ESSCIRC), 2012 Proceedings of the, Sept 2012, pp. 257
260.
[13] F. Lin, All digital duty-cycle correction circuit design and its applications in high-
performance dram, in Microelectronics and Electron Devices (WMED), 2011
IEEE Workshop on, April 2011, pp. 14.
[14] R. J. Baker, CMOS Circuit Design, Layout, and Simulation, 3rd ed. Wiley-IEEE
Press, 2010.
[15] S. Patil and S. Rudraswamy, Duty cycle correction using negative feedback loop,
in Mixed Design of Integrated Circuits Systems, 2009. MIXDES 09. MIXDES-
16th International Conference, June 2009, pp. 424426.
[16] S.-K. Kao and S.-I. Liu, All-digital fast-locked synchronous duty-cycle correc-
tor, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 53,
no. 12, pp. 13631367, Dec 2006.
[17] K. Agarwal and R. Montoye, A duty-cycle correction circuit for high-frequency

clocks, in VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on,
2006, pp. 106107.
[18] K.-H. Cheng, C.-W. Su, and K.-F. Chang, A high linearity, fast-locking
pulsewidth control loop with digitally programmable duty cycle correction for
wide range operation, Solid-State Circuits, IEEE Journal of, vol. 43, no. 2, pp.
399413, 2008.
[19] S.-K. Kao and S.-l. Liu, A wide-range all-digital duty cycle corrector with a pe-
riod monitor, in Electron Devices and Solid-State Circuits, 2007. EDSSC 2007.
IEEE Conference on. IEEE, 2007, pp. 349352.
[20] C. Yoo, C. Jeong, and J. Kih, Open-loop full-digital duty cycle correction circuit,
Electronics letters, vol. 41, no. 11, pp. 635636, 2005.
[21] R. Tajizadegan and A. Abrishamifar, A low-power closed-loop duty-cycle correc-

tion integrated circuit, in Mixed Design of Integrated Circuits and Systems, 2008.
MIXDES 2008. 15th International Conference on. IET, 2008, pp. 173175.
62

High Precision Duty Cycle Correction Circuit Design For 5.2Ghz Speed I/O Applications

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

High Precision Duty Cycle Correction Circuit Design For 5.2Ghz Speed I/O Applications

Caricato da

Copyright:

Formati disponibili

A

Mr. Venkatesh Rao

DEPARTMENT OF ELECTRONICS ENGINEERING

ELECTRONICS ENGINEERING DEPARTMENT

Guide Intel Supervisor Examiner Chairman

P. G. Incharge Head of The Department

Seal of The Department

Date: 23/07/2015 Bhargav Upadhyay

3.6 System Level Working . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.1 DCC inside Transmitter/ Receiver . . . . . . . . . . . . . . . . . . . . 2

2.1 Basic Architecture of Digital DCC [1] . . . . . . . . . . . . . . . . . . 8

3.1 Block Diagram of Proposed Architecture . . . . . . . . . . . . . . . . . 26

3.12 DFM block level RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1 Binary Weighted Coarse Correction Pre-layout result . . . . . . . . . . 40

2.1 Working of Basic Analog Architecture . . . . . . . . . . . . . . . . . . 14

4.1 Performance comparison with Proposed Architecture . . . . . . . . . . 58

1.1 Importance of DCC

Figure 1.1: DCC inside Transmitter/ Receiver

Figure 1.2: Clock signal with 50% duty cycle

1.2 Cause of Degradation

Figure 1.3: Clock signal with duty cycle degradation

1.3 Design Parameters

2. Correction Time (in terms of clock cycles)

5. Power consumption (Max. allowable)

6. Chip Area (Max. possible chip area)

Figure 1.4: Design Parameters

1.4 Basic Block Diagram

Figure 1.5: Basic Block Diagram

Figure 1.6: Conventional Classification of DCC

1.6 Thesis Contribution

3. Input Clock Frequency : 5.2 GHz

5. Correction Accuracy: 50 0.1 %

1.7 Organization of thesis

2.1 Digital Duty Cycle Corrector

2.1.1 Basic Digital DCC Architecture

Figure 2.1: Basic Architecture of Digital DCC [1]

Figure 2.2: Timing Diagram of basic Digital DCC Architecture [1]

2.1.2 Recent Architecture of Digital DCC

Figure 2.3: Recent Architecture of Digital DCC [2]

Working at Low Frequency

Working at High Frequency

2.2 Analog Duty Cycle Corrector

2.2.1 Basic Architecture of Analog DCC

Figure 2.7: Analog DCC Basic Architecture [3]

Working Mechanism of basic Analog Architecture

Table 2.1: Working of Basic Analog Architecture

Input Clock Vbias Changes Current Changes Final Impact per

Figure 2.8: Schematic of delay cell [3]

2.2.2 Recent Architecture of Analog DCC

Figure 2.9: (a)Pulse Stretching Mechanism,(b)Pulse Shrinking Mechanism [3]

Figure 2.10: Recent Analog DCC Architecture [4]

Figure 2.11: Duty Cycle Adjuster [4]

Figure 2.12: Duty Cycle Detector [4]

2.3 Mixed Mode Duty Cycle Corrector

2.3.1 Basic Architecture of Mixed Mode DCC

Figure 2.13: Basic Architecture of Mixed Mode DCC [5]

Figure 2.14: Flow Chart of Basic Mixed Mode DCC [5]

2.3.2 Recent Architecture of Mixed Mode DCC

1. Analog Feedback loop used for Duty cycle correction

binary search algorithm

Figure 2.16: Recent Mixed Mode DCC Architecture [6]

tracks variations due to PVT variations.

2.4 Performance Comparison