Multilevel AC/DC/AC converter for AC drives

B.-R.Lin and H.-H.Lu

Abstract: A novel pulse width modulation (PWM) scheme for a multilevel AC/DC/AC converter is
proposed. A power factor corrector using the hysteresis current control technique is presented to
improve the power quality at the rectifier side. The circuit configuration of the adopted five-level
rectifier has two AC power switches and one diode bridge. The proposed control scheme of the five-
level rectifier is based on a look-up table that is implemented by programmable array logic (PAL).
According to the proposed control method, the line current will follow the reference current with
unity power factor. The reference supply current is derived from a DC link voltage regulator and an
output power estimator. A three-level diode clamped voltage source inverter is used to reduce the
output voltage harmonics and blocking voltage of each power device in each leg. The high power
factor and low current distortion at the input of the rectifier and the low total harmonic distortion at
the output of the inverter are verified by the experimental results.

List of symbols SMR = switching mode rectifier

PAL = programmable array logic
VDC = DC bus voltage
IEC = International Electrotechnical Commission
s = line voltage
s,peak = peak line voltage PWM = pulse width modulation
ab = AC-side voltage of the rectifier 1 Introduction
1, 2 = output capacitor voltages
, = stator voltage in the reference frame With the increasing use of switching mode power convert-
d, q = stator voltage in the synchronous reference ers, the power quality due to the effects of harmonic and
frame reactive currents is becoming a problem for the utility. The
single-phase unidirectional AC to DC converter with boost
dr, qr = rotor flux in the synchronous reference
topology has been widely used as a front-end power factor
frame
pre-regulator due to the high power factor requirement.
min(1, 2) = minimum value of the DC bus voltage 1 For a conventional diode rectifier, the low power factor
and 2 and high harmonic currents from the AC mains are the
is = line current major drawbacks. Inserting an inductor on the AC mains is
i1, i2, il1, il2 = DC bus currents the simplest approach to improve the current waveform
is = line current error and power factor. However, the current harmonics are still
is* = line current command not satisfied for international standards such as IEC 1000-
3-2. Active current waveshaping techniques have been
ids, iqs = stator current in the synchronous reference developed to provide a nearly sinusoidal current. The boost
frame topology [1, 2] has the properties of a step-up voltage ratio,
S1, S2 = bidirectional power switches simple control and continuous input current. Several cur-
Tx1 ~ Tx4 = power switches for three-phase inverter, x = rent control techniques [35] for an AC to DC PWM recti-
a, b, c fier have been proposed in the past few years. Among the
C1, C2 = DC bus capacitors various current control techniques, the fixed band hystere-
L = boost inductor sis current control technique is the simplest method that
has fast current dynamics and an inherent peak current
Ls, Lr = stator and rotor inductance
limiting capability. For high DC-link voltage applications,
Rs, Rr = stator and rotor resistance the high voltage stress of the power device is generally
k1 ~ k4 = digital control signals required in the conventional AC to DC PWM rectifiers.
k1 ~ k4 = complement of a logic signal k1 ~ k4 This drawback results in additional cost for power switch-
ing devices. To overcome this disadvantage, a single-phase
IEE, 1999 five-level rectifier is proposed to reduce the voltage stress
IEE Proceedings online no. 19990253 and power losses on the power devices. A conventional sin-
DOI: 10.1049/ip-epa:19990253
gle-phase three-level rectifier requires 8 power switches to
Paper first received 3rd November 1998 and in revised form 11th February
perform bi-directional power flow. The disadvantage of this
1999 topology is the large number of power devices. If only uni-
The authors are with the Power Electronics Research Laboratory, Department directional power flow is required, the number of power
of Electrical Engineering, National Yunlin University of Science and Technol- devices can be reduced significantly. Two AC power
ogy, Toulin, Yunlin 640, Taiwan, Republic of China switches are required in the adopted single-phase five-level
IEE Proc.-Electr. Power Appl., Vol. 146, No. 4, July 1999 397
rectifier. The voltage rating of the power device is only half
that of the conventional two-level rectifier under the same
DC link voltage. The generated harmonics of the adopted
rectifier are also less than those of the traditional two-level
rectifier under the same switching frequency.
For the DC to AC inverter, carrier based pulse-width
modulation, such as sinusoidal pulse-width modulation,
harmonic injection PWM, random pulse position PWM or
space vector PWM, is generally used. Multilevel converters
[6, 7] are based on the neutral point clamped inverter. Mul-
tilevel inverters are generally adopted for a high voltage,
high power utility, such as a static var compensator and
active power filter, and drive applications, due to their abil-
ity to obtain waveforms with better harmonic spectrum
and attain higher voltages with a lower maximum device
rating. The topologies of the multilevel inverter can be clas-
sified into the transformer coupled multilevel inverter, the
series H-bridge multilevel inverter, the flying capacitor mul-
tilevel inverter, and the diode clamped multilevel inverter.
Transformer coupled multilevel inverters are based on add-
ing the series connected transformer windings through
phase shifting of multiple two-level inverters. A series con-
nection of a single-phase full-bridge inverter with a multiple
isolated DC bus is an alternative method to achieve multi-
level waveforms. The flying capacitor inverter is an alterna-
tive structure to obtain multilevel waveforms. The voltage
stress on the open power devices is constrained by clamp-
ing capacitors. The advantages of the multilevel diode
clamped inverters are an improvement in the waveform
quality and a reduction in the voltage stress on the power
devices. Usually, an n-level diode clamped inverter has n
distinct voltage levels in each leg, (2n 1) distinct levels in
Fig.1 Circuit configuration of the proposed multilevel AC/DC/AC converter
398
the line voltage, (n 1) DC capacitors in the DC link, and
2(n 1) power switches in each phase. The advantages of
the multilevel converters compared to the conventional
two-level converters are a better voltage waveform, low
total harmonic distortion, a lower power device rating, and
low dv/dt stress, although the voltage unbalance problem is
the drawback of the diode clamped inverter. Usually, the
voltage balance problem can be improved by using the
redundant states of the multilevel inverter or by using the
voltage balance compensator of the power factor correction
circuit.
In this paper, a novel control scheme of the single-phase
five-level rectifier is proposed to draw a sinusoidal input
current with low current distortion and a high power fac-
tor. Two AC power switches of the adopted rectifier are
controlled to draw a supply current that is in phase with
the supply voltage. To implement the five-level PWM at
the AC side of the rectifier, the DC link voltage is control-
led in the range 2s,peak > VDC > s, peak. The voltage bal-
ance problem, which is inherent in the multilevel converter,
can be solved using a voltage balancing compensator. The
switching scheme and circuit modelling equations of the
adopted single-phase five-level rectifier are developed and
described in this paper. A three-level inverter for AC drives
is adopted to produce low harmonic contents of output
voltage and reduce the voltage stress of the power devices.
The space vector PWM is used to control the three-level
inverter. The vector control scheme with a three-level
PWM is proposed to drive an induction motor for variable
speed applications. The overall multilevel AC/DC/AC con-
verter was simulated and tested to verify the proposed con-
trol algorithm.
IEE Proc.-Electr. Power Appl., Vol. 146, No. 4, July 1999
2 System configuration

The proposed multilevel AC/DC/AC converter configura-

tion, which consists of a single-phase switching mode recti-
fier in the left side to supply two balance capacitor voltages,
and a three-phase voltage source inverter in the right side,
is shown in Fig. 1. The adopted single-phase five-level
PWM rectifier consists of a single-phase diode bridge and
two AC power switches. An inductance L is placed
between the AC mains and the diode bridge rectifier to
minimise the current ripple. A single-phase five-level PWM
rectifier connected to the supply line is operated to reduce
the line harmonic currents and give a high input power fac-
tor. The control scheme of the adopted rectifier is based on
a look-up table with hysteresis current control to improve
dynamic response. The DC link voltage regulator is used to
determine the reference current of the mains. The given
variable of the five-level PWM rectifier is the AC line volt- Fig.3 Equivalent circuits of the adopted five-level rectifier for S1 = 1, S2 = 0
age, and the control variables are the DC link voltage, the Top: is > 0
voltage difference between two split capacitors, and the Bottom: is < 0
harmonic content of the mains current. The inverter mod-
ule connected to the AC machine is controlled to produce
the proper stator voltages or currents. Three-level pulse-
width modulation based on constant carrier frequency for a
three-phase inverter system is adopted to reduce the har-
monic contents in the output voltage and decrease the volt-
age rating of the power device. The given variable of the
three-level inverter is DC link voltage, and the control vari-
able is the output voltage or current.

3 Modelling and control system design of the

single-phase five-level PWM rectifier

In the past few years, many circuit configurations [810] of

the single-phase two-level switching mode rectifier (SMR)
have been proposed to reduce utility harmonic currents and
increase the power factor. The half-bridge and full-bridge
SMR have properties of bi-directional power flow and
reactive power control. In this paper, a single-phase five-
level PWM rectifier with unidirectional power flow is pro- Fig.4 Equivalent circuits of the adopted five-level rectifier for S1 = 0, S2 = 1
Top: is > 0
posed to provide two balance capacitor voltages for three- Bottom: is < 0
level inverter applications. The objectives of the adopted
five-level rectifier are to draw a sinusoidal current with
unity power factor from the AC mains, and maintain the
balanced DC voltages for stable inverter operation. A sin-
gle-phase five-level rectifier, shown in the left side of Fig. 1,
feeds a split capacitor voltage. Two AC power switches and
four fast recovery diodes are used in the adopted five-level

Fig.5 Equivalent circuit of the adopted five-level rectifier for S1 = S2 = 1

rectifier. The circuit operation of the adopted five-level rec-

tifier can be divided into four modes according to the states
of the power switches (S1 and S2). The equivalent circuit
and the modelling equations in each mode are shown in
Figs. 25 and expressed in the Appendix. Two power
switches (S1 and S2) can be controlled using a hysteresis or
triangular wave current controller such that the line current
is a sinusoidal wave with low current distortion. To com-
pensate the DC link voltage VDC and reduce the ripple volt-
age, a voltage regulator is used to reduce the steady state
error of the DC link voltage. The reference supply current
is obtained from the multiplication of the amplitude of the
Fig.2 Equivalent circuits of the adopted five-level rectifier for S1 = S2 = 0 command current and the sinusoidal time function. The
Top: is > 0
Bottom: is < 0 phase lock loop is adopted to produce a sinusoidal function
IEE Proc.-Electr. Power Appl., Vol. 146, No. 4, July 1999 399
(sin ) which is in phase with the AC source voltage. The
sin look-up table is stored in an EPROM. The EPROM
contents pass through a digital to analogue converter in
order to produce a sinusoidal time function output. The
PWM switching signals of two AC power switches are gen-
erated in order to obtain a sinusoidal line current with a
high power factor. In order to produce five-level PWM at
the AC side of the adopted rectifier, the DC link voltage
VDC is controlled in the range of 2s,peak > VDC > s,peak.
Four digital control signals k1 ~ k4 are defined in the pro-
posed control algorithm:

Fig.6 Implementation of a look-up table (Table 2) using NAND gates

The digital signal k1 is used to represent the positive half
cycle (k1 = 1 ) or negative half cycle (k1 = 0) of the AC
source current is. The hysteresis current controller is
adopted to force the AC mains current to be a sinusoidal
wave which has low harmonic currents and is in phase with
the mains voltage. The switching signals of the two power
switches S1 and S2 are generated according to the switching
table (Table 1). The control variables are the sign of the

Table 1: Relations between the switching signals (S1, S2) and

control signals (k1 ~ k4) for three-level PWM rectifier

k1 k2 k3 k4 (S1, S2)
0 0 0 0 (1, 1)
1 (1, 0)
1 0 (1, 1)
1 (0, 1)
1 0 0 (1, 0)
1 (0, 0)
1 0 (0, 1)
1 (0, 0)

1 0 0 0 (0, 1)
1 (0, 0)
1 0 (1, 0)
1 (0, 0) Fig.7 Control blocks of the single-phase five-level PWM rectifier
1 0 0 (1, 1)
1 (0, 1) mains current (k1), the output of the hysteresis current
1 0 (1, 1) comparator (k2), the output of the voltage comparator of
two split capacitors (k3), and the comparison of source
1 (1, 0)
voltage and minimum voltage of 1 and 2 (k4). For exam-
ple, if the source current is positive (k1 = 1), the capacitor
Table 2: Truth table of three-level PWM rectifier
voltage 1 is larger than 2 (k3 = 1), the instantaneous sup-
(k3, k4) ply voltage is less than the minimum voltage of 1 and 2
(k4 = 0), and the output of the hysteresis current compara-
00 01 11 10 tor is low (k2 = 0), then one should decrease the line cur-
(k1, k2) 00 11 10 01 11 rent since is* is < h. One way to decrease the line current
01 10 00 00 01 and charge the capacitor C2 is to set the two AC power
switches (S1, S2) = (1, 0) and ab = 2. For the case of sim-
11 11 01 10 11
ilar digital control signals (k1 = 1, k2 = 0, k3 = 0, and k4 =
10 01 00 00 10 0), two AC power switches (S1, S2) can be assigned to be
Table entries are values for (S1, S2) (0, 1) to force ab = 1. For this case, the supply current is
400 IEE Proc.-Electr. Power Appl., Vol. 146, No. 4, July 1999
decreasing and the capacitor C1 is charging. The switching
table (Table 1) can be further rewritten as a truth table
(Table 2). The relations between the states of the two AC
power switches S1 ~ S2 and four digital signals k1 ~ k4 can
be expressed by the sum of products as follows.

where ki is the complement of a logic signal ki, and i = 1,

2, 3, 4. Eqns. 5 and 6 can be implemented by logic NAND
gates, shown in Fig. 6, or programmable array logic (PAL)
to simplify the control circuit. If the two capacitor voltages,
1 and 2, are equal, then there is a five-level PWM pattern
(VDC, VDC/2, 0, VDC/2 and VDC) on the waveform of ab.
The complete control block of the adopted rectifier is
shown in Fig. 7.

Fig.9 Switching patterns of the three-level inverter using the sine-triangular

PWM scheme

ing patterns of the three-level inverter are given in Fig. 9

and expressed as

Fig.8 Switching states
a Three-phase two-level inverter
b Three-phase three-level inverter
4 Control algorithm of the three-level inverter
A three-level diode clamped inverter for an AC motor drive
is shown in the right half of Fig. 1. There are two fast
recovery diodes, four power switch devices and four free-
wheeling diodes in each leg of the three-phase voltage
source inverter. In the conventional three-phase two-level
voltage source inverter, there are 8 switching states, as
shown in Fig. 8a. However, there are 27 switching states,
shown in Fig. 8b, in the three-level inverter. Several PWM
methods such as the sine-carrier PWM method [11], hyster-
esis comparator [12], sigma-delta scheme [13], or space vec-
tor PWM scheme [14] are proposed to generate the three-
level PWM patterns. The sine-carrier PWM patterns are
usually generated by comparing the three reference modu-
lating waves with two triangular carrier waves. The switch-
IEE Proc.-Electr. Power Appl., Vol. 146, No. 4, July 1999
where x = a, b, c. The three reference modulating waves are
related by a phase shift of 120 with the same amplitude.
Two carrier waves are in phase each other with a DC volt-
age offset. There are three equivalent circuits, according to
the states of the power switches Ta1 ~ Ta4, of the diode
clamped inverter in one leg shown in Fig. 10. Two impor-
tant parameters of the design process are the amplitude
modulation index ma = Ar/Ac, where Ar is the amplitude of
the reference modulating signal and Ac is the amplitude of
the carrier wave, and the frequency modulation index mf =
fc/fr, where fc is the frequency of the carrier wave and fr is
the frequency of the reference modulating signal. A voltage
space vector V can be used to represent the output voltages
of the three-phase inverter in vector form:
401

Fig.10 Operation modes of the three-level inverter in one leg
a Ta1 = Ta2 on, Ta3 = Ta4 off
b Ta2 = Ta3 on, Ta1 = Ta4 off
c Ta1 = Ta2 off, Ta3 = Ta4 on
Fig.11 Reference voltage vector V* in the first sector (0 < < /3)
The space vector representation of output voltages of the
three-phase three-level inverter in the two-axis coordinate
system is shown in Fig. 8b. According to the angle and
magnitude of the reference voltage space vectors V*, the
possible switching states, shown in Fig. 11, in the first sec-
tor 0 < < /3 can be classified into four groups: large
voltage vectors such as V2 and V5, middle voltage vectors
such as V4, small voltage vectors such as V1 and V3, and
zero voltage vectors such as V0. For the space vector PWM
402
method, the voltage space vector is obtained by transform-
ing the output voltages of the three-phase inverter accord-
ing to eqn. 11. If the reference voltage space vector V* falls
in a small triangular region, shown in Fig. 11, where is
between 0 and /3, three adjacent voltage vectors VT1, VT2
and VT3 are selected for the space vector PWM control
scheme. These selected voltage vectors are dependent on
the angle and the amplitude of the reference voltage vector
V*. The time interval of each voltage vector can be
obtained by the time-averaging principle:
where T is the sampling time of the reference voltage vec-
tor, and V* is the reference voltage vector of the three-
phase inverter. The relations between the three adjacent
voltage vectors (VT1, VT2 and VT3) and the actual switching
Table 3: Relations between the voltage vectorsVT1 ~ VT3 and
the selected voltage vectorsV0 ~ V5 in the first sector (0 < <
/3)
Triangle VT1 VT2 VT3
1 V0 V1 V3
2 V1 V2 V4
3 V1 V3 V4
4 V3 V4 V5
states (V0 ~ V5) are shown in Table 3. By using the time-
averaging scheme, the reference voltage in the frame
can be expressed as
where * and * are the reference voltage components
along with the axes (stationary reference frame). If the
reference voltage vector V* is given, the time intervals T1 ~
T3 of the voltage vectors VT1 ~ VT3 can be obtained from
eqns. 1315:
If the reference voltage vector V* is located in the other sec-
tors, it can be transformed into the first sector using the fol-
lowing equation
where i = 1, 2, ..., 6. The vector control scheme is the most
common way to control the magnitude and frequency of
the stator voltage for an induction motor drive. The system
inputs are flux and torque references which are used to
determine the corresponding current values of ids and iqs. A
mathematical description of the induction motor can be
more comprehensive when expressed by vectors in the syn-
chronous reference frame. The dynamic properties of an
induction motor can be described by a set of nonlinear dif-
ferential equations. The vector equations based on the syn-
chronous reference flame can be written in matrix form as
IEE Proc.-Electr. Power Appl., Vol. 146, No. 4, July 1999

The electromagnetic torque, which is developed by the
interaction of the air gap flux and rotor MMF, and the
motor angular speed variation are expressed as
In the rotor flux field-oriented control scheme, the d-axis
can be exactly fixed to the rotor flux vector |r|, such that
From eqn. 23, the electromagnetic torque Te can be con-
trolled by a torque producing current iqs if the rotor flux is
kept constant. In this condition, the stator currents of the
induction machine can be separated into two orthogonal
currents: the torque producing current iqs and the flux pro-
ducing current ids. Fig. 12 shows the proposed three-level
Fig.12 Proposed block of three-level induction motor drives based on vector control approach
IEE Proc.-Electr. Power Appl., Vol. 146, No. 4, July 1999
induction motor drives based on the rotor flux oriented
control approach. The instantaneous value of the angular
rotor speed r is measured and compared with the com-
mand value of the rotor speed r*. The resulting error is
supplied to the input of the speed controller. The output of
the speed controller is the reference value of the torque pro-
ducing current iqs*. The flux producing current ids* is
obtained from the output of the flux controller. The stator
voltages in the synchronous dq frame are converted into
the stator oriented frame by application of the trans-
formation eje, where e is the synchronous angle of the
rotor magnetising current based on the rotor flux model.
The reference stator voltages * and * in the stator refer-
ence frame are used to obtain the time intervals, T1 ~ T3,
of the output voltage vectors, VT1 ~ VT3, according to
eqn. 16.
5 Experimental verification
To investigate the proposed control method, a digital signal
processor (TMS320C50) is adopted as the kernel in the
realisation of the multilevel AC/DC/AC converter. The
tasks of the digital controller include multilevel pulse width
modulation of the adopted rectifier, control of an induction
motor drive, monitoring current, voltage, speed and data
acquisition. The modulation technique of the adopted five-
level rectifier is based on a look-up table with hysteresis
current control to improve the dynamic response due to the
load variation. The DC link voltage was obtained by recti-
fication of the supply voltage with a single-phase five-level
PWM rectifier. The DC voltage, line current, supply volt-
age, and inverter output currents are measured with the
optocoupler, current transducer, and potential transformer.
The relations between the four control signals and two
PWM patterns are implemented by a programmable array
logic (18CV8). The circuit parameters of the adopted recti-
fier are s = 110Vrms, L = 1.5mH, S1 and S2 = IRFP450,
C = 2200F. The output rated power of the five-level
rectifier is 1.2kW in the laboratory tests. The average
switching frequency of the adopted rectifier is about 10kHz
and the range of variation is about 2kHz. The DC bus
403
voltage is about 200V. A constructed 2 HP three-phase
inverter drive was carried out to drive a 1kW induction
motor from Nikki Denso Inc. The vector control based on
a rotor flux oriented induction drive is adopted to produce
a three-phase controlled voltage for variable speed applica-
tions. The space vector PWM scheme is adopted to obtain
a three-level PWM pattern. Fig. 13 gives the measured
waveforms of the supply voltage, line current and AC side
voltage of the adopted single-phase five-level PWM recti-
fier. The power factor and total harmonic distortion of the
single-phase five-level rectifier are 0.99 and 6%, respectively,
at the rated power based on the proposed switching
scheme. To verify the dynamic response of the five-level
rectifier, the measured waveforms of the load variation
Fig.16 Experimental line voltage waveforms of the three-level inverter for
induction motor drives
200V/div; 10ms/div

Fig.13 Experimental waveforms of the supply voltage, supply current and

AC side voltage of the proposed rectifier
Upper traces: 100V/div, 10A/div; lower trace: 200V/div; time: 5ms/div

Fig.17 Experimental line current waveforms of the three-level inverter for

induction motor drives
5A/div; 10ms/div

Fig.14 Dynamic response of the five-level rectifier due to load variation from
400W to 800W
10A/div; 100V/div; 0.2s/div

Fig.18 Measured waveforms of reference rotor speed and actual rotor speed
due to speed change (0 rpm 1200 rpm 1200 rpm)
100rpm/div; 0.5s/div

from 400W to 800W are shown in Fig. 14. The voltage

drop at the load change instantly is about 20V and the
recovery time of the DC bus is about 0.2s. Figs. 1517
show the experimental results of the phase voltages, line
voltages and load currents of the three-level pulse width
modulation for an induction motor drive. There is a three-
level PWM in each leg and five-level PWM in the line volt-
age. The load currents have low harmonic distortion from
the measured results. To prevent overvoltage in the DC bus
when the motor operates in the regeneration mode, the
braking circuit is used to control the regenerated energy.
Fig.15 Experimental phase voltage waveforms of the three-level inverter for
induction motor drives The reference rotor speed and actual rotor speed due to
100V/div; 10ms/div speed change based on rotor flux-oriented control are
404 IEE Proc.-Electr. Power Appl., Vol. 146, No. 4, July 1999
shown in Fig. 18. The transient time of the rotor speed due
to speed change is about 0.1s. The vector trajectory of the
stator current is shown in Fig. 19 under the 2Nt m
torque command.
12 SILVA, J.F.: Sliding mode controllers for multilevel inverters. Pro-
ceedings of EPE97, 1997, pp. 3.3313.336
13 MANJREKAR, M., and VENKATARAMANAN, G.: Advanced
topologies and modulation strategies for multilevel inverters. Proceed-
ings of IEEE power electronics specialists conference, PESC-96, 1996,
pp. 10131018
14 SUH, B.S., and HYUN, D.S.: A new n-level high voltage inversion
system, IEEE Trans. Ind. Electron., 1997, 44, (1), pp. 107115

8 Appendix

The equivalent circuit, as shown in Fig. 25, and the mod-

elling equations in each mode are expressed as
Mode 1: (S1 = S2 = 0):

or

Fig.19 Stator current of the motor drive

6 Conclusions
Mode 2: (S1 = 1, S2 = 0):
A new control scheme of the AC/DC/AC converter with
multilevel PWM technique has been proposed in this
paper. A look-up table with hysteresis current control strat-
egy is used to draw a nearly sinusoidal wave with unity
power factor from the supply line. The power factor, cur-
rent harmonics, and inverter output voltage waveforms or
have been improved from the experimental results. The DC
link voltage balance problem which is inherent in the multi-
level system can be improved by using the adopted control
algorithm of the five-level PWM rectifier. The vector con-
trol of the induction motor with a three-level inverter drive
is implemented in this paper to reduce the stress of the Mode 3: (S1 = 0, S2 = 1):
power device and improve the stator current harmonics.
The experimental results show a good supply current wave-
form with nearly unity power factor and good output line
voltages with less harmonic content.

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power applications. Proceedings of IEEE power electronics specialists the states of power switches and the sign of the supply cur-
conference, PESC-95, 1995, pp. 347352 rent:
IEE Proc.-Electr. Power Appl., Vol. 146, No. 4, July 1999 405
 where sgn(is) = 1 if is > 0 or sgn(is) = 1 if is < 0.

Table 4: Relation between the AC side voltage of the rectifier

and the switching signals S1 and S2

is (S1, S2) ab
+ (0, 0) 1 + 2
(0, 1) 1
(1, 0) 2
(1, 1) 0
(0, 0) (1 + 2)
(0, 1) 2
(1, 0) 1
(1, 1) 0

406 IEE Proc.-Electr. Power Appl., Vol. 146, No. 4, July 1999