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Am29F002/Am29F002N
2 Megabit (256 K x 8-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation Top or bottom boot block configurations
5.0 Volt-only operation for read, erase, and available
program operations Embedded Algorithms
Minimizes system level requirements Embedded Erase algorithm automatically
High performance preprograms and erases the entire chip or any
combination of designated sectors
Access times as fast as 55 ns
Embedded Program algorithm automatically
Low power consumption (typical values at 5
writes and verifies data at specified addresses
MHz)
1 A standby mode current Minimum 100,000 write cycle guarantee per
sector
20 mA read current
Package option
30 mA program/erase current
32-pin PDIP
Flexible sector architecture
32-pin TSOP
One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
32-pin PLCC
three 64 Kbyte sectors
Supports full chip erase Compatibility with JEDEC standards
Sector Protection features: Pinout and software compatible with single-
power supply Flash
A hardware method of locking a sector to
prevent any program or erase operations within Superior inadvertent write protection
that sector Data# Polling and toggle bits
Sectors can be locked via programming Provides a software method of detecting
equipment program or erase operation completion
Temporary Sector Unprotect feature allows code
Erase Suspend/Erase Resume
changes in previously locked sectors
Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
Hardware reset pin (RESET#)
Hardware method to reset the device to reading
array data (not available on Am29F002N)
GENERAL DESCRIPTION
The Am29F002 Family consists of 2 Mbit, 5.0 volt-only device automatically times the erase pulse widths and
Flash memory devices organized as 262,144 bytes. verifies proper cell margin.
The Am29F002 offers the RESET# function, the
The host system can detect whether a program or
Am29F002N does not. The data appears on DQ7
erase operation is complete by reading the DQ7 (Data#
DQ0. The device is offered in 32-pin PLCC, 32-pin
Polling) and DQ6 (toggle) status bits. After a program
TSOP, and 32-pin PDIP packages. This device is
or erase cycle has been completed, the device is ready
designed to be programmed in-system with the
to read array data or accept another command.
standard system 5.0 volt V CC supply. No V PP is
required for write or erase operations. The device can The sector erase architecture allows memory sectors
also be programmed in standard EPROM program- to be erased and reprogrammed without affecting the
mers. data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 55, 70, 90,
and 120 ns, allowing high speed microprocessors to Hardware data protection measures include a low
operate without wait states. To eliminate bus contention VCC detector that automatically inhibits write opera-
the device has separate chip enable (CE#), write tions during power transitions. The hardware sector
enable (WE#) and output enable (OE#) controls. protection feature disables both program and erase
operations in any combination of the sectors of mem-
The device requires only a single 5.0 volt power sup-
ory. This can be achieved via programming equipment.
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the The Erase Suspend feature enables the user to put
program and erase operations. erase on hold for any period of time to read data from,
The device is entirely command set compatible with the or program data to, any sector that is not selected for
JEDEC single-power-supply Flash standard. Com- erasure. True background erase can thus be achieved.
mands are written to the command register using The hardware RESET# pin terminates any operation
standard microprocessor write timings. Register con- in progress and resets the internal state machine to
tents serve as input to an internal state-machine that reading array data. The RESET# pin may be tied to the
controls the erase and programming circuitry. Write system reset circuitry. A system reset would thus also
cycles also internally latch addresses and data needed reset the device, enabling the system microprocessor
for the programming and erase operations. Reading to read the boot-up firmware from the Flash memory.
data out of the device is similar to reading from other (This feature is not available on the Am29F002N.)
Flash or EPROM devices.
The system can place the device into the standby
Device programming occurs by executing the program mode. Power consumption is greatly reduced in this
command sequence. This initiates the Embedded mode.
Program algorithman internal algorithm that auto-
matically times the program pulse widths and verifies AMDs Flash technology combines years of Flash
proper cell margin. memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
Device erasure occurs by executing the erase com- ness. The device electrically erases all bits within
mand sequence. This initiates the Embedded Erase a sector simultaneously via Fowler-Nordheim tun-
algorithman internal algorithm that automatically neling. The data is programmed using hot electron
preprograms the array (if it is not already programmed) injection.
before executing the erase operation. During erase, the
2 Am29F002/Am29F002N
PRELIMINARY
BLOCK DIAGRAM
DQ0DQ7
VCC
Sector Switches
VSS
Erase Voltage Input/Output
RESET# Generator Buffers
n/a Am29F00N
WE# State
Control
Command
Register PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
OE# Logic
Y-Decoder Y-Gating
STB
Address Latch
A0A17
20818C-1
Am29F002/Am29F002N 3
PRELIMINARY
CONNECTION DIAGRAMS
NC on Am29F00N NC on Am29F00N
RESET#
RESET#
NC 1 32 VCC
WE#
A16 2 31 WE#
A16
A17
VCC
A12
A15
A15 3 30 A17
A12 4 29 4 3 2 1 32 31 30
A14
A7 5 29 A14
A7 5 28 A13
A6 6 28 A13
A6 6 27 A8
A5 7 27 A8
A5 7 26 A9
A4 8 26 A9
A4 8 PDIP 25 A11 PLCC
A3 9 25 A11
A3 9 24 OE# A2 10 24 OE#
A2 10 23 A10 A1 11 A10
23
A1 11 22 CE# A0 12 22 CE#
A0 12 21 DQ7 DQ0 13 21 DQ7
DQ0 13 20 DQ6 14 15 16 17 18 19 20
DQ1 14 19 DQ5
VSS
DQ3
DQ6
DQ1
DQ2
DQ4
DQ5
DQ2 15 18 DQ4
VSS 16 17 DQ3
A11 1 32 OE#
A9 2 31 A10
A8 3 30 CE#
A13 4 29 DQ7
A14 5 28 DQ6
A17 6 27 DQ5
WE# 7 26 DQ4
VCC 8 25 DQ3
Standard TSOP
NC on Am29F00N RESET# 9 24 VSS
A16 10 23 DQ2
A15 11 22 DQ1
A12 12 21 DQ0
A7 13 20 A0
A6 14 19 A1
A5 15 18 A2
A4 16 17 A3
20818C-2
4 Am29F002/Am29F002N
PRELIMINARY
supply tolerances)
VSS = Device ground
NC = Pin not connected internally
20818C-3
Am29F002/Am29F002N 5
PRELIMINARY
ORDERING INFORMATION
Standard Product
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29F002 T -70 P C B
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0C to +70C)
I = Industrial (-40C to +85C)
E = Extended (55C to +125C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F002/Am29F002N
2 Megabit (256 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Am29F002T-70
Am29F002B-70
PC, PI, JC, JI, EC, EI
Am29F002NT-70
Am29F002NB-70
Am29F002T-90
Am29F002B-90
Am29F002NT-90
Am29F002NB-90 PC, PI, PE,
JC, JI, JE,
Am29F002T-120 EC, EI, EE
Am29F002B-120
Am29F002NT-120
Am29F002NB-120
6 Am29F002/Am29F002N
PRELIMINARY
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Dont Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information. This function requires the
RESET# pin and is therefore not available on the Am29F002N device.
Requirements for Reading Array Data sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power An erase operation can erase one sector, multiple sec-
control and selects the device. OE# is the output control tors, or the entire device. The Sector Address Tables in-
and gates array data to the output pins. WE# should re- dicate the address space that each sector occupies. A
main at VIH. sector address consists of the address bits required
to uniquely select a sector. See the Command Defini-
The internal state machine is set for reading array
tions section for details on erasing a sector or the entire
data upon device power-up, or after a hardware reset.
chip, or suspending/resuming the erase operation.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No After the system writes the autoselect command se-
command is necessary in this mode to obtain array quence, the device enters the autoselect mode. The
data. Standard microprocessor read cycles that as- system can then read autoselect codes from the inter-
sert valid addresses on the device address inputs nal register (which is separate from the memory array)
produce valid data on the device data outputs. The on DQ7DQ0. Standard read cycle timings apply in this
device remains enabled for read access until the mode. Refer to the Autoselect Mode and Autoselect
command register contents are altered. Command Sequence sections for more information.
See Reading Array Data for more information. Refer ICC2 in the DC Characteristics table represents the ac-
to the AC Read Operations table for timing specifica- tive current specification for the write mode. The AC
tions and to the Read Operations Timings diagram for Characteristics section contains timing specification
the timing waveforms. ICC1 in the DC Characteristics tables and timing diagrams for write operations.
table represents the active current specification for
reading array data. Program and Erase Operation Status
During an erase or program operation, the system may
Writing Commands/Command Sequences check the status of the operation by reading the status
To write a command or command sequence (which in- bits on DQ7DQ0. Standard read cycle timings and ICC
cludes programming data to the device and erasing read specifications apply. Refer to Write Operation
Am29F002/Am29F002N 7
PRELIMINARY
Status for more information, and to each AC Charac- RESET#: Hardware Reset Pin
teristics section for timing diagrams.
Note: The RESET# pin is not available on the
Am29F002N.
Standby Mode
When the system is not reading or writing to the device, The RESET# pin provides a hardware method of reset-
it can place the device in the standby mode. In this ting the device to reading array data. When the system
mode, current consumption is greatly reduced, and the drives the RESET# pin low for at least a period of tRP,
outputs are placed in the high impedance state, inde- the device immediately terminates any operation in
pendent of the OE# input. progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
The device enters the CMOS standby mode when CE# pulse. The device also resets the internal state ma-
and RESET# pins (CE# only on the Am29F002N) are chine to reading array data. The operation that was in-
both held at VCC 0.5 V. (Note that this is a more re- terrupted should be reinitiated once the device is ready
stricted voltage range than VIH.) The device enters the to accept another command sequence, to ensure data
TTL standby mode when CE# and RESET# pins (CE# integrity.
only on the Am29F002N) are both held at VIH. The de-
vice requires standard access time (tCE) for read ac- Current is reduced for the duration of the RESET#
cess when the device is in either of these standby pulse. When RESET# is held at VIL, the device enters
modes, before it is ready to read data. the TTL standby mode; if RESET# is held at VSS
0.5 V, the device enters the CMOS standby mode.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, RE- The RESET# pin may be tied to the system reset cir-
SET#: Hardware Reset Pin. cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
If the device is deselected during erasure or program- ware from the Flash memory.
ming, the device draws active current until the
operation is completed. Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
In the DC Characteristics tables, ICC3 represents the
standby current specification. Output Disable Mode
If the device is deselected during erasure or program- When the OE# input is at VIH, output from the device is
ming, the device draws active current until the disabled. The output pins are placed in the high imped-
operation is completed. ance state.
ICC3 in the DC Characteristics tables represents the
standby current specification.
8 Am29F002/Am29F002N
PRELIMINARY
Autoselect Mode
The autoselect mode provides manufacturer and de- dress must appear on the appropriate highest order
vice identification, and sector protection verification, address bits. Refer to the corresponding Sector Ad-
through identifier codes output on DQ7DQ0. This dress Tables. The Command Definitions table shows
mode is primarily intended for programming equipment the remaining address bits that are dont care. When all
to automatically match a device to be programmed with necessary bits have been set as required, the program-
its corresponding programming algorithm. However, ming equipment may then read the corresponding
the autoselect codes can also be accessed in-system identifier code on DQ7DQ0.
through the command register.
To access the autoselect codes in-system, the host
When using programming equipment, the autoselect system can issue the autoselect command via the
mode requires VID (11.5 V to 12.5 V) on address pin command register, as shown in the Command Defini-
A9. Address pins A6, A1, and A0 must be as shown in tions table. This method does not require VID. See
Autoselect Codes (High Voltage Method) table. In addi- Command Definitions for details on using the autose-
tion, when verifying sector protection, the sector ad- lect mode.
Device ID: L L H
Am29F002/Am29F002N X X VID X L X L H B0h
(Top Boot Block) L L H
Device ID: L L H
Am29F002/Am29F002N X X VID X L X L H 34h
(Bottom Boot Block) L L H
01h
(protected)
Sector Protection Verification L L H SA X VID X L X H L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Dont care.
Sector Protection/Unprotection
The hardware sector protection feature disables both Sector protection/unprotection must be implemented
program and erase operations in any sector. The using programming equipment. The procedure re-
hardware sector unprotection feature re-enables both quires a high voltage (VID) on address pin A9 and the
program and erase operations in previously pro- control pins. Details on this method are provided in the
tected sectors. supplements, publication numbers 20819 and 21183.
Am29F002/Am29F002N 9
PRELIMINARY
RESET# = VIH
Temporary Sector
Unprotect
Completed (Note 2)
20818C-4
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
10 Am29F002/Am29F002N
PRELIMINARY
COMMAND DEFINITIONS
Writing specific address and data commands or se- however, the device ignores reset commands until the
quences into the command register initiates device op- operation is complete.
erations. The Command Definitions table defines the
The reset command may be written between the se-
valid register command sequences. Writing incorrect
quence cycles in an autoselect command sequence.
address and data values or writing them in the im-
Once in the autoselect mode, the reset command must
proper sequence resets the device to reading array
be written to return to reading array data (also applies
data.
to autoselect during Erase Suspend).
All addresses are latched on the falling edge of WE# or
If DQ5 goes high during a program or erase operation,
CE#, whichever happens later. All data is latched on
writing the reset command returns the device to read-
the rising edge of WE# or CE#, whichever happens
ing array data (also applies during Erase Suspend).
first. Refer to the appropriate timing diagrams in the
AC Characteristics section.
Autoselect Command Sequence
Reading Array Data The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
The device is automatically set to reading array data
and determine whether or not a sector is protected.
after device power-up. No commands are required to
The Command Definitions table shows the address
retrieve data. The device is also ready to read array
and data requirements. This method is an alternative to
data after completing an Embedded Program or Em-
that shown in the Autoselect Codes (High Voltage
bedded Erase algorithm.
Method) table, which is intended for PROM program-
After the device accepts an Erase Suspend command, mers and requires VID on address bit A9.
the device enters the Erase Suspend mode. The sys-
The autoselect command sequence is initiated by
tem can read array data using the standard read tim-
writing two unlock cycles, followed by the autoselect
ings, except that if it reads at an address within erase-
command. The device then enters the autoselect
suspended sectors, the device outputs status data.
mode, and the system may read at any address any
After completing a programming operation in the Erase
number of times, without initiating another command
Suspend mode, the system may once again read array
sequence.
data with the same exception. See Erase Sus-
pend/Erase Resume Commands for more information A read cycle at address XX00h or retrieves the manu-
on this mode. facturer code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector ad-
The system must issue the reset command to re-en-
dress (SA) and the address 02h in returns 01h if that
able the device for reading array data if DQ5 goes high,
sector is protected, or 00h if it is unprotected. Refer to
or while in the autoselect mode. See the Reset Com-
the Sector Address tables for valid sector addresses.
mand section, next.
The system must write the reset command to exit the
See also Requirements for Reading Array Data in the
autoselect mode and return to reading array data.
Device Bus Operations section for more information.
The Read Operations table provides the read parame-
Byte Program Command Sequence
ters, and Read Operation Timings diagram shows the
timing diagram. Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two un-
Reset Command lock write cycles, followed by the program set-up
command. The program address and data are written
Writing the reset command to the device resets the de-
next, which in turn initiate the Embedded Program al-
vice to reading array data. Address bits are dont care
gorithm. The system is not required to provide further
for this command.
controls or timings. The device automatically provides
The reset command may be written between the se- internally generated program pulses and verify the pro-
quence cycles in an erase command sequence before grammed cell margin. The Command Definitions take
erasing begins. This resets the device to reading array shows the address and data requirements for the byte
data. Once erasure begins, however, the device ig- program command sequence.
nores reset commands until the operation is complete.
When the Embedded Program algorithm is complete,
The reset command may be written between the se- the device then returns to reading array data and ad-
quence cycles in a program command sequence be- dresses are no longer latched. The system can deter-
fore programming begins. This resets the device to mine the status of the program operation by using DQ7
reading array data (also applies to programming in or DQ6. See Write Operation Status for information
Erase Suspend mode). Once programming begins, on these status bits.
Am29F002/Am29F002N 11
PRELIMINARY
Any commands written to the device during the Em- command, which in turn invokes the Embedded Erase
bedded Program Algorithm are ignored. On the algorithm. The device does not require the system to
Am29F002 only, note that a hardware reset during the preprogram prior to erase. The Embedded Erase algo-
sector erase operation immediately terminates the op- rithm automatically preprograms and verifies the entire
eration. The Sector Erase command sequence should memory for an all zero data pattern prior to electrical
be reinitiated once the device has returned to reading erase. The system is not required to provide any con-
array data, to ensure data integrity. trols or timings during these operations. The Command
Definitions table shows the address and data require-
Programming is allowed in any sequence and across
ments for the chip erase command sequence.
sector boundaries. A bit cannot be programmed
from a 0 back to a 1. Attempting to do so may halt Any commands written to the chip during the Embed-
the operation and set DQ5 to 1, or cause the Data# ded Erase algorithm are ignored. On the Am29F002
Polling algorithm to indicate the operation was suc- only, note that a hardware reset during the sector
cessful. However, a succeeding read will show that the erase operation immediately terminates the operation.
data is still 0. Only erase operations can convert a 0 The Sector Erase command sequence should be rein-
to a 1. itiated once the device has returned to reading array
data, to ensure data integrity.
The system can determine the status of the erase
START
operation by using DQ7, DQ6, or DQ2. See Write
Operation Status for information on these status
bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
Write Program addresses are no longer latched.
Command Sequence
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in AC
Characteristics for parameters, and to the Chip/Sector
Data Poll Erase Operation Timings for timing waveforms.
from System
Embedded
Program Sector Erase Command Sequence
algorithm Sector erase is a six bus cycle operation. The sector
in progress erase command sequence is initiated by writing two un-
Verify Data? lock cycles, followed by a set-up command. Two addi-
No
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
Yes erase command. The Command Definitions table
shows the address and data requirements for the sec-
No tor erase command sequence.
Increment Address Last Address?
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
Yes rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
Programming system is not required to provide any controls or tim-
Completed ings during these operations.
20818C-5 After the command sequence is written, a sector erase
Note: See the appropriate Command Definitions table for
time-out of 50 s begins. During the time-out period,
program command sequence. additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
Figure 2. Program Operation may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 s,
otherwise the last address and command might not be
Chip Erase Command Sequence accepted, and erasure may begin. It is recommended
Chip erase is a six-bus-cycle operation. The chip erase that processor interrupts be disabled during this time to
command sequence is initiated by writing two unlock ensure all commands are accepted. The interrupts can
cycles, followed by a set-up command. Two additional be re-enabled after the last Sector Erase command is
unlock write cycles are then followed by the chip erase written. If the time between additional sector erase
12 Am29F002/Am29F002N
PRELIMINARY
Am29F002/Am29F002N 13
PRELIMINARY
Erase Suspend/Erase Resume Commands tors produces status data on DQ7DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
The Erase Suspend command allows the system to in-
if a sector is actively erasing or is erase-suspended.
terrupt a sector erase operation and then read data
See Write Operation Status for information on these
from, or program data to, any sector not selected for
status bits.
erasure. This command is valid only during the sector
erase operation, including the 50 s time-out period After an erase-suspended program operation is com-
during the sector erase command sequence. The plete, the system can once again read array data within
Erase Suspend command is ignored if written during non-suspended sectors. The system can determine
the chip erase operation or Embedded Program algo- the status of the program operation using the DQ7 or
rithm. Writing the Erase Suspend command during the DQ6 status bits, just as in the standard program oper-
Sector Erase time-out immediately terminates the ation. See Write Operation Status for more informa-
time-out period and suspends the erase operation. Ad- tion.
dresses are dont-cares when writing the Erase Sus-
The system may also write the autoselect command
pend command.
sequence when the device is in the Erase Suspend
When the Erase Suspend command is written during a mode. The device allows reading autoselect codes
sector erase operation, the device requires a maximum even at addresses within erasing sectors, since the
of 20 s to suspend the erase operation. However, codes are not stored in the memory array. When the
when the Erase Suspend command is written during device exits the autoselect mode, the device reverts to
the sector erase time-out, the device immediately ter- the Erase Suspend mode, and is ready for another
minates the time-out period and suspends the erase valid operation. See Autoselect Command Sequence
operation. for more information.
After the erase operation has been suspended, the The system must write the Erase Resume command
system can read array data from or program data to (address bits are dont care) to exit the erase suspend
any sector not selected for erasure. (The device erase mode and continue the sector erase operation. Further
suspends all sectors selected for erasure.) Normal writes of the Resume command are ignored. Another
read and write timings and command definitions apply. Erase Suspend command can be written after the de-
Reading at any address within erase-suspended sec- vice has resumed erasing.
14 Am29F002/Am29F002N
PRELIMINARY
Cycles
Command
Sequence First Second Third Fourth Fifth Sixth
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID,
4 555 AA 2AA 55 555 90 X01 B0
Auto- Top Boot Block
select Device ID,
4 555 AA 2AA 55 555 90 X01 34
(Note 7) Bottom Boot Block
Sector Protect Verify (SA) 00
4 555 AA 2AA 55 555 90
(Note 8) X02 01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30
Legend:
X = Dont care PD = Data to be programmed at location PA. Data latches on the
RA = Address of the memory location to be read. rising edge of WE# or CE# pulse, whichever happens first.
RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17A13 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations. 7. The fourth cycle of the autoselect command sequence is a
2. All values are in hexadecimal. read cycle.
3. Except when reading array or autoselect data, all bus cycles 8. The data is 00h for an unprotected sector and 01h for a
are write operations. protected sector. See Autoselect Command Sequence for
more information.
4. Address bits A17A12 are dont cares for unlock and
command cycles, except when PA or SA is required. 9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
5. No unlock or command cycles required when reading array mode. The Erase Suspend command is valid only during a
data. sector erase operation.
6. The Reset command is required to return to reading array 10. The Erase Resume command is valid only during the Erase
data when device is in the autoselect mode, or if DQ5 goes Suspend mode.
high (while the device is providing status data).
Am29F002/Am29F002N 15
PRELIMINARY
16 Am29F002/Am29F002N
PRELIMINARY
DQ6: Toggle Bit I trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
Toggle Bit I on DQ6 indicates whether an Embedded
pended. DQ6, by comparison, indicates whether the
Program or Erase algorithm is in progress or complete,
device is actively erasing, or is in Erase Suspend, but
or whether the device has entered the Erase Suspend
cannot distinguish which sectors are selected for era-
mode. Toggle Bit I may be read at any address, and is
sure. Thus, both status bits are required for sector and
valid after the rising edge of the final WE# pulse in the
mode information. Refer to Table 6 to compare outputs
command sequence (prior to the program or erase op-
for DQ2 and DQ6.
eration), and during the sector erase time-out.
Figure 5 shows the toggle bit algorithm in flowchart
During an Embedded Program or Erase algorithm op-
form, and the section DQ2: Toggle Bit II explains the
eration, successive read cycles to any address cause
algorithm. See also the DQ6: Toggle Bit I subsection.
DQ6 to toggle. (The system may use either OE# or
Refer to the Toggle Bit Timings figure for the toggle bit
CE# to control the read cycles.) When the operation is
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
complete, DQ6 stops toggling.
ferences between DQ2 and DQ6 in graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog- Reading Toggle Bits DQ6/DQ2
gles for approximately 100 s, then returns to reading Refer to Figure 5 for the following discussion. When-
array data. If not all selected sectors are protected, ever the system initially begins reading toggle bit sta-
the Embedded Erase algorithm erases the unpro- tus, it must read DQ7DQ0 at least twice in a row to
tected sectors, and ignores the selected sectors that determine whether a toggle bit is toggling. Typically, a
are protected. system would note and store the value of the toggle bit
The system can use DQ6 and DQ2 together to deter- after the first read. After the second read, the system
mine whether a sector is actively erasing or is erase- would compare the new value of the toggle bit with the
suspended. When the device is actively erasing (that is, first. If the toggle bit is not toggling, the device has
the Embedded Erase algorithm is in progress), DQ6 completed the program or erase operation. The sys-
toggles. When the device enters the Erase Suspend tem can read array data on DQ7DQ0 on the following
mode, DQ6 stops toggling. However, the system must read cycle.
also use DQ2 to determine which sectors are erasing However, if after the initial two read cycles, the system
or erase-suspended. Alternatively, the system can use determines that the toggle bit is still toggling, the
DQ7 (see the subsection on DQ7: Data# Polling). system also should note whether the value of DQ5 is
If a program address falls within a protected sector, high (see the section on DQ5). If it is, the system
DQ6 toggles for approximately 2 s after the program should then determine again whether the toggle bit is
command sequence is written, then returns to reading toggling, since the toggle bit may have stopped tog-
array data. gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
DQ6 also toggles during the erase-suspend-program program or erase operation. If it is still toggling, the
mode, and stops toggling once the Embedded Pro- device did not complete the operation successfully, and
gram algorithm is complete. the system must write the reset command to return to
The Write Operation Status table shows the outputs for reading array data.
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit The remaining scenario is that the system initially de-
algorithm, and to the Toggle Bit Timings figure in the termines that the toggle bit is toggling and DQ5 has not
AC Characteristics section for the timing diagram. gone high. The system may continue to monitor the
The DQ2 vs. DQ6 figure shows the differences be- toggle bit and DQ5 through successive read cycles, de-
tween DQ2 and DQ6 in graphical form. See also the termining the status as described in the previous para-
subsection on DQ2: Toggle Bit II. graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
DQ2: Toggle Bit II beginning of the algorithm when it returns to determine
The Toggle Bit II on DQ2, when used with DQ6, indi- the status of the operation (top of Figure 5).
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress), DQ5: Exceeded Timing Limits
or whether that sector is erase-suspended. Toggle Bit DQ5 indicates whether the program or erase time has
II is valid after the rising edge of the final WE# pulse in exceeded a specified internal pulse count limit. Under
the command sequence. these conditions DQ5 produces a 1. This is a failure
DQ2 toggles when the system reads at addresses condition that indicates the program or erase cycle was
within those sectors that have been selected for era- not successfully completed.
sure. (The system may use either OE# or CE# to con-
Am29F002/Am29F002N 17
PRELIMINARY
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to 1. See text.
20818C-8
18 Am29F002/Am29F002N
PRELIMINARY
Am29F002/Am29F002N 19
PRELIMINARY
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0C to +70C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . 40C to +85C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . 55C to +125C
VCC Supply Voltages
VCC for 5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
20 Am29F002/Am29F002N
PRELIMINARY
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC max 1.0 A
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max 1.0 A
ICC1 VCC Active Read Current (Note 2) CE# = VIL, OE# = VIH 20 30 mA
ICC2 VCC Active Write Current (Notes 3, 4) CE# = VIL, OE# = VIH 30 40 mA
ICC3 VCC Standby Current VCC = VCC max, CE#, OE# = VIH 0.4 1 mA
ICC4 VCC Reset Current (Note 1) VCC = VCC max; RESET# = VIL 0.4 1 mA
VCC
VIH Input High Voltage 2.0 V
+ 0.5
VOL Output Low Voltage IOL = 12 mA, VCC = VCC min 0.45 V
VOH Output High Voltage IOH = 2.5 mA, VCC = VCC min 2.4 V
Notes:
1. RESET# is not available on Am29F002N.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
Am29F002/Am29F002N 21
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
ICC3 VCC Standby Current (Note 5) VCC = VCC max; CE# = VCC0.5 V 1 5 A
ICC4 VCC Reset Current (Notes 1, 5) VCC = VCC max; RESET# = VIL 1 5 A
VOL Output Low Voltage IOL = 12 mA, VCC = VCC min 0.45 V
Notes:
1. RESET# is not available on Am29F002N.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
5. ICC3 and ICC4 = 20 A max at extended temperature (>+85 C).
22 Am29F002/Am29F002N
PRELIMINARY
TEST CONDITIONS
Table 7. Test Specifications
5.0 V
All
Test Condition -55 others Unit
2.7 k
Device Output Load 1 TTL gate
Under
Test Output Load Capacitance, CL
30 100 pF
(including jig capacitance)
CL 6.2 k
Input Rise and Fall Times 5 20 ns
Steady
Changing from H to L
Changing from L to H
KS000010-PAL
Am29F002/Am29F002N 23
PRELIMINARY
AC CHARACTERISTICS
Read Operations
Parameter Speed Option
JEDEC Std Description Test Setup -55 -70 -90 -120 Unit
CE# = VIL
tAVQV tACC Address to Output Delay Max 55 70 90 120 ns
OE# = VIL
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 ns
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.
tRC
tDF
tOE
OE#
tOEH
WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid
RESET#
n/a Am29F002N
20818C-12
Figure 9. Read Operations Timings
24 Am29F002/Am29F002N
PRELIMINARY
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
CE#, OE#
tRH
RESET#
n/a Am29F002N
tRP
tReady
RESET#
n/a Am29F002N
tRP
20818C-13
Figure 10. RESET# Timings
25 Am29F002/Am29F002N
PRELIMINARY
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performance section for more information.
Am29F002/Am29F002N 26
PRELIMINARY
AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS
Addresses 555h PA PA PA
tAH
CE#
tCH
tGHWL
OE#
tWP tWHWH1
WE#
tWPH
tCS
tDS
tDH
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
20818C-14
Figure 11. Program Operation Timings
27 Am29F002/Am29F002N
PRELIMINARY
AC CHARACTERISTICS
tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#
tGHWL
OE# tCH
tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status).
20818C-15
Figure 12. Chip/Sector Erase Operation Timings
Am29F002/Am29F002N 28
PRELIMINARY
AC CHARACTERISTICS
tRC
Addresses VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data
High Z
DQ0DQ6 Status Data Status Data True Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
20818C-16
Figure 13. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses VA VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
20818C-17
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
29 Am29F002/Am29F002N
PRELIMINARY
AC CHARACTERISTICS
Enter
Embedded Erase Enter Erase Erase
Erasing Suspend Suspend Program Resume
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
20818C-18
Figure 15. DQ2 vs. DQ6
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
12 V
RESET#
0 or 5 V 0 or 5 V
tVIDR tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
20818C-19
Figure 16. Temporary Sector Unprotect Timing Diagram (Am29F002 only)
Am29F002/Am29F002N 30
PRELIMINARY
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
31 Am29F002/Am29F002N
PRELIMINARY
AC CHARACTERISTICS
555 for program PA for program
2AA for erase SA for sector erase
555 for chip erase
Data# Polling
Addresses PA
tWC tAS
tAH
tWH
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CE#
tWS tCPH
tDS
tDH
DQ7# DOUT
Data
tRH A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase
RESET#
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of data written to device, DOUT = data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
20818C-20
Figure 17. Alternate CE# Controlled Write Operation Timings
Am29F002/Am29F002N 32
PRELIMINARY
Notes:
1. Typical program and erase times assume the following conditions: 25C, 5.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90C, VCC = 4.5 V (4.75 V for -55), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
1.0 V 12.5 V
(including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pins 1.0 V VCC + 1.0 V
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. RESET# not available on Am29F002N.
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25C, f = 1.0 MHz.
33 Am29F002/Am29F002N
PRELIMINARY
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Test Conditions Min Unit
150C 10 Years
Minimum Pattern Data Retention Time
125C 20 Years
Am29F002/Am29F002N 34
PRELIMINARY
PHYSICAL DIMENSIONS
PD 032
32-Pin Plastic DIP (measured in inches)
1.640
1.670 .600
.625
32 17
.530 .009
.580 .015
Pin 1 I.D.
.630
16 .700
.045 0
.065 .005 MIN 10
.140
.225
PL 032
32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.447 .495
.453
.009
.015
.042
.125 .056
.585 Pin 1 I.D. .140
.595
.080
.547 .095
.553
SEATING
PLANE .400
REF.
.490
.530
.013
.021
.050 REF. 16-038FPO-5
.026
.032 PL 032
DA79
TOP VIEW SIDE VIEW 6-28-94 ae
35 Am29F002/Am29F002N
PRELIMINARY
Pin 1 I.D.
1
7.90
8.10
0.50 BSC
0.05
18.30 0.15
18.50
19.80
20.20
0.08 16-038-TSOP-2
1.20 0.20 TS 032
MAX 0.10 DA95
0.21 3-25-97 lv
0
5
0.50
0.70
Am29F002/Am29F002N 36
PRELIMINARY
Trademarks
Copyright 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
37 Am29F002/Am29F002N