Hybrid Functional Verification Methodology for Video/Audio SoC
Sandeep Gupta
Mentor Emulation Division
Mentor Graphics (India) Pvt. Ltd.
Sandeep_g@mentor.com
Abstract
Functional verification (namely early verification of
multimedia processing capabilities) is one of the main
challenges in developing SoC-based products, such as
consumer electronic devices and portables that incorporate
complex audio and video interfaces. Due to rising design
complexity, increasingly intricate hardware/software
interactions and rising demand for lower power operation are
putting pressure on SoC functional verification strategies.
These trends are the threats to SoC predictability and product
development schedules. In this paper I am discussing hybrid
functional verification methodology well suited for
Video/Audio SoC.
Keywords
Hybrid Verification, Emulation, Audio-Video SoC, Cage
Architecture, Capture-Analyzer-Generator-Exerciser.
I. Introduction
It is now more critical than ever that verification solution
not only be fast, but also comprehensive especially for
Multimedia SoC.
The hybrid function verification methodology discussed
here delivers real-world test data and analysis tools to ensure
that the verification of the SoC has been checked thoroughly
for compliance and conformance to standards, along with
verifying complex interoperability issues in both software and
hardware. It reduces the problems faced by many designers
who require the accurate generation and analysis of long data
streams for multiple protocols and standards, such as
video/audio data for multimedia applications, and remove the
need for complicated test benches.
II. Traditional functional verification methodologies
The traditional functional verification methodologies are
"black-box." That is, they apply stimulus to the inputs of an
RTL design and compare the outputs to expected values. Such
an end-to-end approach ignores the details of the internal
implementation. Black-box methods include directed, pseudo-
random, and system-level simulation. These methods are
inadequate for thorough functional verification of large SOC
designs for two reasons:
Poor observability: The effects of a bug often take so
many cycles and require such special sensitization of the
circuit to reach the design's outputs that the bug goes
undetected by the end-to-end test.
Poor controllability: The stimulus sequence required to
trigger a bug is often so complex that test writers can't
deliberately generate it. Also, this sequence is often so
978-1-4244-4952-1/09/$25.00 2009 IEEE 264
unlikely that pseudo-random and system-level environments
have essentially no chance of producing it.
Both observability and controllability become worse as
the design size grows, which is why functional verification of
monster SOC designs is such a big problem. Verification of
multi-million-gates design with traditional black-box methods
is very much error prone.
III. Hybrid functional verification methodology
The hybrid functional verification uses both hardware-
software capabilities thus this new interactive methodology
offers an answer to the escalating challenges. The hardware
accelerator could be used for emulating the SoC prototype.
And the software model generates, exercises, captures &
analyzes the video and audio streams to/from design RTL
running in verification accelerators (Emulator).
Customer Analyzer
Designs
(RTL) Translator
HW Host
Accelerators machine
Video & Audio Out Data Out over USB
Fig. 1: Hardware-Software verification Model (Analyzer)
Exerciser Customer
Designs
Translator (RTL)
Host HW
machine Accelerator
Data Out over USB Video & Audio
Fig. 2: Hardware-Software verification Model (Exerciser)
This system is designed to handle data streams at full
emulation speeds for maximum performance. The new
approach promises to simplify the adoption and proliferation
of new verification technologies and improves interfacing and
reuse across functional groups. It easy to deploy,
incorporating stimuli generation and results analysis features,
ensuring that SoC designs are right the first time while saving
the time and expertise otherwise spent on creating complex
test-benches.
1st Int'l Symposium on Quality Electronic Design-Asia
 Functional verification using the software based Analyzer
solution, together with hardware emulators, delivers nearly
1,000 to 10000X speed improvement over software
simulation, saving weeks or even months of regression testing.
Hence this methodology helps the design teams to run billions
of real-world cycles on their SoC before tape-out, meeting
customer delivery schedules and rigorous project goals.
It has capability to validate both contents and protocol for
Audio out and Video out. The design engineer could test and
analyze the functionality of their designs by; real time
visualization, content capture and compare, and real time
content generation. Thus it allows identifying and fixing the
system bugs in both hardware and software. Design teams can
also perform true system-level verification and address
important interoperability and performance issues.
IV. Software Model & Cage Architecture
The software model proposed here utilized cage
architecture. It has capability of supporting all the existing
video/audio formats/protocols and can extend easily for newer
formats/protocols. This CAGE architecture comprises four
different software applications namely Capture, Analyzer,
Generator and exerciser.
Capture (C): It captures multimedia signals from a
design under test (DUT) by reading IOs data coming out from
the Hardware accelerator through an IO Translator and stores
it into database and/or sends data to the Analyzer application
via USB bus.
Emulation Domain
Hardware
Accelerator
DB DB
Software
Domain
AVI WAV AVI WAV
Analyzer Exerciser
Fig. 3: Cage Architecture
Analyzer (A): It parses/renders the data send by the
Capture (C). And uses advanced analysis to determine the
accuracy of the multimedia data by examining pixel-level
video and utilizing audio spectrum analysis tools. By the
visualization of the multimedia data, early design flaws can be
detected, thus reducing risk of design re-spins and
significantly increasing productivity. The output can be saved
as the AVI & WAV files directly.
Generator (G): allows design engineer to generate
various Audio/Video Formats data files (DB).
The various video/audio formats/protocols covered are
described as below.
Video/Graphics: RGB, YUV, 4:2:2, 4:4:4. (All formats
can be any frame size, up to 5600 x 4300, interlaced or
progressive)
Mobile Applications: Raw Bayer video (8/10-bit)
[SMIA 1.0]
Audio: I2S, S/PDIF, and 32-bit linear PCM
High-Definition: HDMI 1.2
Exerciser (E): The Exerciser stream-in the data as
generated by Generator on the DUT.
V. Conclusion
1. Fast, easy set-up A simple connection to any
verification accelerator.
2. Supports major industry standards Improves potential
for design reuse and helps ensure product interoperability
for audio & video.
3. Investigate SoC video output Visualization of design
output to analyze video artifacts.
4. Investigate SoC audio output Listen to audio output
from the design
5. Regression testing Recorded video and audio data can
be compared to reference data.
6. User-friendly GUI Provides access to Multimedia-
Analyzer Software via the host PC.
7. Reduces overall verification time Design verification at
MHz speeds using the capabilities of hardware-assisted
verification.
VI.References
1. Digital Video Standards - ITU601-656.
2. High- definition Multimedia Interface Specification 1.3.
3. A DTV Profile for uncompressed high speed digital
interface DEA-861-C.
4. SMIA CCP2 Specification.