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INTRODUCTION time since they are limited by the requirement to refresh the
charge in the bootstrap capacitor.
The purpose of this paper is to highlight the most common Proper capacitor choice can reduce drastically these limi-
subjects driving a half bridge power stage in motor drive ap- tations.
plications (with monolithic IC gate driver) and to suggest ap-
propriate solutions to solve the issues. Bootstrap capacitor sizing
In the following sections different topics are discussed: the
sizing of some fundamental components, as bootstrap circuit To size the bootstrap capacitor, the first step is to establish
and on/off gate resistors; the half bridge parasitic elements the minimum voltage drop (VBS) that we have to guarantee
are presented with their effects and some possible solutions when the high side IGBT is on. If VGEmin is the minimum gate
are proposed. In the end section some layout tips are pre- emitter voltage to maintain, the voltage drop must be:
sented.
All the situations and the solutions proposed are, unless VBS VCC VF VGEmin VCEon
otherwise specified, for a typical IR monolithic gate driver
with floating bootstrap supply. under the condition:
This method has the advantage of being simple and low cost but may force some limitations on
Foron-time
duty-cycle and since they
more information are limited
in North Americabycall
the+1 requirement toEurope
310 252 7105, in refreshcall
the+49charge theor visit us at www.irf.com
6102 884in311, DT04-04
bootstrap capacitor.
Proper capacitor choice can reduce drastically these limitations.
capacitor (paralleling
ILK_CAP is only electrolytic
relevant when using anand low ESR
electrolytic ceramic
capacitor and may the above
can be ignored if otherformulas.
types of
capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor
result in an efficient solution).
(paralleling electrolytic and low ESR ceramic may result in an efficient solution).
2. This kind of bootstrap sizing approach does not take into
Then
Thenwe wehave:
have: account neither the duty cycle of the PWM, nor the funda
QTOT = QG + QLS + (ILK _ GE + IQBS + ILK + ILK _ DIODE + ILK _ CAP + IDS ) THON mental frequency
DT04-4 revA of the current. It considers only the
QTOT = QG +QLS + (ILK _GE + IQBS + ILK + ILK _DIODE + ILK _CAP + IDS ) THON amount of charge that is needed when the high voltage side
The
Theminimum
minimum size of bootstrap
size of bootstrap capacitor is: Using
capacitor is: monolithic high voltage gatedriver
of the drivers
is floating and IGBT gate is driven once.
Bootstrap QTOT
diode leakage current (ILK_DIODE); Considerations on PWM duty cycle, kind of modulation (six-
CBOOT min =diode bias when on (IDS- )
Desat VBS step, 12-step, sine-wave) must be considered with their own
Charge required by the internal level shifters (QLS);
Bootstrap capacitor leakage current (ILK_CAP); peculiarity to achieve best bootstrap circuit sizing.
Anexample
High sidefollows:
on time (T ).
An example follows: HON
ILK_CAP is only
a) using a 25Arelevant
@ 125C when
IGBTusing an electrolytic capacitor
(IRGP30B120KD) and a high and ignoredConsiderations
can behalf-bridge
voltage if gate types of about bootstrap circuit
otherdriver
capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor
(IR2214):
a) using aelectrolytic
(paralleling 25A @ 125C IGBT
and low ESR (IRGP30B120KD)
ceramic may resultand in anaefficient
high volt- solution).
age
Then half-bridge
Iwe = 800 A
QBShave:
gate driver (IR2214):
(Datasheet IR2214); a. Voltage ripple
ILK = 50 A (Datasheet IR2214);
QTOT = QG + QLS + (I LK _ GE + IQBS + ILK + ILK _ DIODE + I LK _ CAP + IDS ) THON
Q = 20 nC;
IQBS = 800 A (Datasheet IR2214);
LS Three different situations can occur in the bootstrap capac-
QG = 160 nC (Datasheet IRGP30B120KD);
The minimum size of bootstrap capacitor is:
ILK = 50= A
ILK_GE 100(Datasheet
nA IR2214);
(Datasheet IRGP30B120KD); itor charging (see figure 1):
QILK_DIODE
= 20 =nC;
QTOT 100QA = 160 nC (Datasheet
(with reverseIRGP30B120KD);
recovery time <100 ns);
CBOOT LS min =
G
ILK_CAP =V0BS (neglected for ceramic capacitor);
ILK_GE = 100 nA (Datasheet IRGP30B120KD); - ILOAD < 0; the load current flows in the low side IGBT dis-
IDS- = 150 A (Datasheet IR2214);
An example
ILK_DIODE = 100
THON = follows:
100 s.A (with reverse recovery time <100 ns); playing relevant VCEon
I
a) using
= 0 (neglected for ceramic capacitor);
And: a 25A @ 125C IGBT (IRGP30B120KD) and a high voltage half-bridge gate driver
LK_CAP
I - = 150 A (Datasheet IR2214);
(IR2214):
DS
V =V V BS CC F
VCEon
IT HON
QBS =V=
800
CC 10015s.
= A V (Datasheet IR2214);
ILK = V F=
50 A1V (Datasheet IR2214); In this case we have the lowest value for VBS. This repre-
QLS =V20 nC;
CEonmax = 3.1 V
And:
QG =V160 nC
GEmin = 10.5 V
(Datasheet IRGP30B120KD); sents the worst case for the bootstrap capacitor sizing.
ILK_GE = 100 nA (Datasheet IRGP30B120KD);
ILK_DIODE = 100 A (with reverse recovery time <100 ns);
When the IGBT is turned off the Vs node is pushed up by
the
IV
maximum voltage drop V BS becomes
LK_CAP
CC
= =150 V (neglected for ceramic capacitor); the load current until the high side freewheeling diode gets
IDS- = 150 A (Datasheet IR2214);
VTBS
VHON==1CC100
F V
VVFs.VGEmin VCEon = 15V 1V 10.5 V 3.1V = 0.4 V forwarded biased
V = 3.1 V
And: CEonmax
And
Vthe bootstrap
= 10.5 Vcapacitor is: - ILOAD = 0; the IGBT is not loaded while being on and VCE can
GEmin
VCC = 15 V
V = 1290
V nC be neglected
C VF = 3.1 V= 725 nF
the maximum
BOOT voltage drop
CEonmax0.4 V VBS becomes
VGEmin = 10.5 V
VBS =VCC VF
NOTES:
VBS VCC VF VGEmin VCEon=15V 1V 10.5V 3.1V = 0.4V
the maximum voltage drop VBS becomes
VBS VCC VF VGEmin VCEon = 15V 1V 10.5 V 3.1V = 0.4 V - ILOAD > 0; the load current flows through the freewheeling
And the bootstrap capacitor is:
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And the bootstrap capacitor is:
diode 3
290 nC
CBOOT
0. 4 V
= 725 nF VBS =VCC VF +VFP
NOTES:
In this case we have the highest value for VBS. Turning on the
Notes: high side IGBT, ILOAD flows into it and VS is pulled up.
www.irf.com 3
1. Here above VCC has been chosen to be 15V. Some IGBTs To minimize the risk of undervoltage, bootstrap capacitor
may require higher supply to properly work with the boot- should be sized according to the ILOAD<0 case.
strap technique. Also Vcc variations must be accounted in
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d. off
capacitor sizing. When the IGBT is turned Bootstrap
the Vs Diode
node is pushed up by the load current until
The diode must have a BV > DC+ and a fast recovery time (trr < 100 ns) to minimize the amou
the high side freewheeling diode get forwarded biased
of charge fed back from the bootstrap capacitor to VCC supply.
ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected
Using Monolithic High Voltage Gate Drivers GATE RESISTANCES
VBS = VCC VF
The switching speed of the output transistor can be controlled by properly size the resisto
controlling the turn-on and turn-off gate current. The following section provides some basic rule
b. ILOAD >Resistor
Bootstrap 0; the load current flows through the freewheeling
Qgc and diode
for sizing the resistors Qtoge obtain
indicatethethedesired
gate toswitching
collector time
and gate to emitter
and speed by introducing th
equivalent outputcharge
resistance of the gate driver (RDRp and RDRn respectively of p and n channel).
respectively.
VBS = VCC VF + VFP The examples always use IGBT power transistor. Figure 2 shows the nomenclature used in th
A resistor (Rboot) is placed in series with bootstrap diode (see
following Sizing
paragraphs. the turn-on
In addition, Vge* gate resistor
indicates the plateau voltage, Qgc and Qge indicate the ga
figure 1) so to limit the current when the bootstrap capacitor
to collector and gate to emitter charge respectively.
In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it
is initially
and V charged. The choice of bootstrap resistor is strictly
S is pulled up. I C
related to VBS time-constant. The minimum on time for charg- C RES
b. Bootstrap Resistor
t ,Q t ,Q
c.
A Bootstrap
resistor (R Capacitor
boot) is placed in series with bootstrap diode (see figure 1) so to limit the current when
1 GE 2 GC
V
the bootstrap capacitor is initially charged. The choice of bootstrap resistor isdV/dt strictly related to
CE
forms
c. aBootstrap
voltage divider with Rboot generating a voltage step on
Capacitor V * ge
V GE
at the
VBSFor firstTcharge
high of bootstrap
HON designs wherecapacitor.
is used an Theelectrolytic
voltage steptank capacitor, its ESR must be considered. CRESoff
10%
andThis parasitic
the related resistance
speed (dVBS/dt)forms
shouldabevoltage
limited.divider with Rboot generating a voltage
As a general 10% step on VBS at the
first charge of bootstrap capacitor.
rule, ESR should meet the following constraint: The voltage step and the related speed (dV BS/dt) should be t,Q
d. Bootstrap Diode
For the matters of the calculation included hereafter, the
The diode must have a BV > DC+ and a fast recovery time switching time tsw is defined as the time spent to reach the
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(trr < 100 ns) to minimize the amount of charge fed back from end of the plateau voltage (a total Qgc + Qge has been pro- Using mono
the bootstrap capacitor to VCC supply. vided to the IGBT gate). To obtain the desired switching time
the gate resistance
gate). can the
To obtain be sized starting
desired from Qge
switching andthe
time Qgc,
gate resistanc
GATE RESISTANCES Vcc, Vge*
Qgc, (see
Vcc,figure*
Vge 3):
(see figure 3):
The switching speed of the output transistor can be con- Qgc + Qge
I avg =
trolled by properly size the resistors controlling the turn-on t sw
and turn-off gate current. The following section provides and
some basic rules for sizing the resistors to obtain the desired
*
switching time and speed by introducing the equivalent output Vcc Vge
RTOT =
resistance of the gate driver (RDRp and RDRn respectively of Iavg
p and n channel). The examples always use IGBT power tran-
where RTOT = R DRp + RGon , RGon = gate on-resistor and RD
sistor. Figure 2 shows the nomenclature used in the following
paragraphs. In addition, Vge* indicates the plateau voltage, (from the gate driver datasheet)
Vcc/Vb Iavg
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CRES
RDRp
Using monolithic high voltage gate drivers
c + Qge
Using monolithic high voltage gate drivers
t sw gate). To obtain the desired switching time the gate resistance can be sized starting from Qge and DT04-4
Qgc, Vcc, Vge* (see figure 3):
Using Monolithic
gate). To obtain High
the Voltage Gate Drivers
desired switching time the gate resistance can be sized starting from Qge and
* Qgc, Vcc, V *
ge (see figure 3):
Using monolithic high voltage gate
Vcc Vge Qgc + Qge
I avg =
Iavg t swQ
where Q gc +
TOT DRpgeGon R = R + R , RGon = gatethe
Sizing on-resistor and gate
turn-off external events.
resistor
avg =
Iand
TOT = R DRp + RGon= ,driver
RDRp RGon = gate on-resistor
t swequivalent and (from
on-resistance = driver
RDRp the equivalent
gate driver In on-resistance
this case, dV/dt of the output node induces a parasitic
and
datasheet)
gate driver datasheet) * The worst case in sizing current the turn-off
throughresistor Goff is in
CRESoffRflowing whenRGoffthe
andcollector
RDRn (seeof the IGBT in off
figure
Vcc Vge forced to commutate by external events.
RTOT = 4)1.
* Using
Using monolith
monolith
RTOT =
VccIavg Vge
Vcc/Vb IavgIn this case, dV/dt of the 1
output nodedrop
If the voltage induces a parasitic
at the gate exceedscurrent through
the threshold voltageCRESoff flowing
and R (see figure 4) .
where RTOT Iavg= R
DRp + RGon ,C
DRn
RGon = gate on-resistor and of the IGBT,= the
RDRp device
driver may self turn
equivalent on causing large oscilla-
on-resistance
IfRES
the voltage drop at the gate Sizing exceeds
Sizing the
the the threshold
turn-off
turn-off gate
gate voltage of the IGBT, the device may
resistor
resistor
where
(from the RTOTgate R DRp +datasheet)
= driver RGon , Ron = gate on-resistor
Goncausing andtion
large oscillation and relevant
DRp =relevant
Rand cross
crossconduction.
driver equivalent on-resistance
conduction.
RDRp
(from the gate driver datasheet) Theworst
The worstcase
caseininsizing
sizingthe theturn-off
turn-off resistor
resistor RRGoff is when
Goff is when the
the co
co
Vcc/Vb I forced to commutate by external
avg forced to commutate by external events. events.
RGon Vcc/Vb I InInthis
thiscase,
case,dV/dt
dV/dt ofof the
the output
output node
node induces
induces
dV/dt aa parasitic
parasitic curren
curren
avg
CRES and R (see
HS Turning
figure 4)
ON
11.
and RDRn (see figure 4) .
DRn
CRES IfIfthe thevoltage
voltagedrop
dropat atthe
theCgate
gateexceeds
exceedsthethethreshold
thresholdvoltage
voltage of
of th
th
RDRp RESoff
COM/Vs ononcausing
causinglarge
largeoscillation
oscillationand andrelevant
relevantcross
crossconduction.
conduction.
RDRp RGoff
OFF
Figure 3: RGon sizing RGon ON
RDRn CIES
RGon HSTurning
HS TurningON
ON
eports the gate resistance size for two commonly used IGBTs (calculation made using
atasheet values and assuming Vcc=15V). COM/Vs CCRESoff
RESoff
COM/Vs Figure 4: RGoff sizing: current path when Low Side is off and
Table 1 reports the gate resistance size for two commonly RRGoff
oltage slopeused IGBTs (calculation made using typical datasheet High Side turns on Goff
Figure3:
Figure 4:RRGon
values sizing:
Goffsizing current path when Low Side is off and High Side turns OFF on
OFF
and assuming Vcc=15V). Figure 3: R Gon sizing ON
ON CCIES
RRDRn
DRn IES
gate resistor RGon can1be
Table sized to
reports thecontrol Hereafter
output
gate resistance slopesize(dVisfor
described
OUT /dt).
two commonlyhowHereafter
toused
sizeisIGBTs
the turn-off
described
resistor
(calculation
how tomade made
size the
when the
using output
turn-off resistor when
dV/dt is caused
Table
e output voltage 1
has reports
a the
non-linear gate resistance
behaviour,
companion
typical datasheet values and assuming Vcc=15V). size
the for two
maximum
IGBT commonly
output
turning-on used
slope
(as IGBTs
showncan (calculation
be
in figure 4). using
ated by: Output voltage
typical datasheet slope values and assuming Vcc=15V). the output dV/dt is caused by the companion IGBT turning-on
Other dV/dt cases may be present and must be taken into account. As an example, th
Output voltage slope generated by long motor (as
cableshown in figure(high
coupling 4). frequency spikes).
Figure
Figure 4: RRGoff sizing:current
current path wheninto LowSide Side isis off
off
Iavg Output
Turn-on voltage
gate resistorslope RGon can be Forsized
this to controlthe
reason output Other dV/dt
off-resistance must be 4:
cases may
properly Goffsizing:
be present and must
sized according path betowhen
taken Low
the application wors
CRESoff slope (dVOUTgate
Turn-on /dt). resistor RGon can be sized to control output account.
slope
Hereafter As OUT
(dV an example,
/dt).
is described
described thehowdV/dttogenerated
size the by long motor
the turn-off
turn-off resistor when when theth
Turn-on gate resistor RGon can The
be sized to control Hereafter
outputrelates
slope (dV is
/dt). how to size resistor
While the
While the output
output voltage has ahas
voltage afollowing
non-linearnon-linear equation
behaviour, the cable
behaviour, thethe
companion IGBT
OUT
couplingmaximum (high
IGBT gate threshold
frequency
output
turning-on voltage
spikes).
slope
(as can
shown to
beinthe collector
figure 4). dV/dt:
While the output voltage has a non-linear behaviour, the maximum output slope can be companion IGBT turning-on (as shown in figure 4).
the expression approximated
yielding
maximum Iavg and
output
approximated by:rearranging:
slope
by: can be approximated by: Other dV/dt
For thisdV/dt
Other reasoncasescases may be
the off-resistance
may be present
present
must beand and
properlymust
must beac-
sized
be taken into
taken into acc
acc
dV
Vth (RGoff + RDRn ) I = (RGoff + RDRn ) CRESoff
generated
generated
cording to the byby long
long
application motor
motor cable
outcable
worst case. coupling
coupling (high
(high frequency
frequency spikes).
spikes).
Vcc Vge
*
dVout
dV IIavg
avg Forthis
For thisreason
reasonthe theoff-resistance
off-resistance
dt mustbe
must beproperly
properlysized sized accordin
accordin
out =
dt = CRESoff
dV The following
CRESoff out dt C RESoff
Rearranging the equation The The
yields: followingequation
following equation
equation
relates
relates
the IGBT
relates theIGBT
the
gate threshold
IGBT gatethreshold
gate
volt- voltage to
threshold voltage to
dt age to the collector dV/dt:
inserting
inserting theexpression
the
inserting the expression
expression yielding
yielding
yielding IavgIavg
and andrearranging:
Iavgand rearranging:
rearranging: dVout
dV
ample, table 2 shows the sizing of gate resistance RGoff to get Vthout/dt=5V/nsVwhen
dV RDRnVthth(R (using
Goff ++
RGoff two
RRDRnDRn)) I I ==(R(RGoff
Goff ++R DRn)) C
RDRn CRESoff
RESoff
out
www.irf.com 11
This
Thisisistrue
trueunder
under the
theassumption
assumptionthat
thatgate
gatevoltage
voltageremains
remains fixe
fixe
DT04-4 revA
Using Monolithic High Voltage Gate Drivers Using monolithic high voltage gate drivers
at least two order of magnitude greater than CRES). board. This solution reduces the noise coupled to the local
ble 3: RGoff sizing V high sideCC L
ground of the driver. Moreover it is suggested to make star
H
driver
low C VCC
GBT Vth(min) ELEMENT
PARASITIC CRESoff RGoff EFFECTSvoltage V
connections between ground pins and board ground for all
LOAD OUT
supply
GP30B120K(D) 4 85pF RGoff 4 V SS gate drivers
L (see layout tips).
G4PH30K(D) 3 14pF RGoff 35
L
low side
In figure 5 a single-phase motor drive power stage and its
driver
DT04-4 revA
ARASITIC ELEMENT EFFECTS
driver is shown. Some of the characteristics of the driver and
GATE DRIVER COM below Ground (Vss-COM)
Q
the power stage will drive
be analyzed.
D V
Using monolithic high voltage gate drivers
power To properly
and drive the pow-
L L FDL
figure 5 a single-phase motor stage its driver is shown. Some of the
COM
aracteristics of the driver and the power stage will be analyzed. Low side IGBT is considered to explain COM below Vss
COM
L R event.
below
DC- GroundFigure 6 shows one of the possible configurations of
(Vss-COM)
DC-
DC+ (high voltage supply) DC+
L R
DC+
To properly drive the power stage it is Vvery important to know the effects of inductive parasitic
S
VOUT
elements. In normal operation V mode
high side the fast Lvoltage variations, induced by a fast current change,
CC
FDL
SS
GATE DRIVER
COM
RSENSE
LDC- RDC-
GND
LDC- RDC-
GND
Figure 5: Parasitic elements in the power stage Figure 6: Parasitic elements during low-side turn-off
Consider to turn off (dotted arrow) the low side IGBT when load current is flowing through it (bold
properly drivewww.irf.com
the power stage it is very important to know the arrow). effectsAsoftheinductive turns off the current flowing 8
parasitic
power device in the parasitic inductance (LDC-)
ments. In normal operation mode the fast voltage variations, induced by a fast current
and the change,
For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us voltage
changes rapidly induced pushes COM below ground. The amount
at www.irf.com DT04-04of voltage
flyback is governed by the well known law:
y influence the gate driver performances.
dI L
presence of high and low power signals both referenced to the same VL ground,
= LDC it is important
. to DC
oid ground loops on board or ground planes close to the switching portions of the dt board. This dc
This equation relates COM undershoot (strictly dependent on inductance voltage) to the slope of
ution reduces the noise coupled to the local ground of the driver.load Moreover
current. it is suggested to
RGOFF VG
CVCC QL DL VFDL
ON
VE
VSS COM
Using Monolithic High Voltage Gate Drivers
GATE DRIVER
RSENSE
emitter sense shunt is included for completeness). NOTES: IGBT short circuit desaturation easily generate high
Consider to turn offGND
(dotted arrow) the low side IGBT when collector dV/dt. IGBT gate is pulled above the local supply by
LDC-
load current is flowing through it (bold arrow). As the power the R DC-gate-collector stray capacitance.
device turns off the current flowing in the parasitic inductance In some cases (usually when turn-on resistor is low) a fast
Figure 6: Parasitic elements during low-side turn-off
(LDC-) changes rapidly and the induced voltage pushes COM diode is needed between IGBT gate and local supply to DT04-4 pro- revA
below ground. tect the driver output (figure 8).
Consider to turn off (dotted arrow) the low side IGBT when load current is flowing through it (bold
Thearrow).
amountAsof the
voltage flyback
power is governed
device turns offby the
the current
well As an alternative
flowing Using
solution a zener
in the parasitic monolithic
clamp
inductance (Lhigh
can be ) voltage
DC-placed
gate drivers
be-
known changes
law: rapidly and the induced voltage pushes COM below ground. The amount of voltage
flyback is governed by the well known law: DC+
dI LDC
VLdc = LDC .
dt DG DH
RT
This equation relates COM undershoot (strictly dependent on inductance voltage) to the slope of
O
SH
load
This current.
equation relates COM undershoot (strictly dependent DT04-4 revA
on inductancereason,
For this voltage) the first
to the solution
slope of loadiscurrent.
to turn off more softly the IGBT, by increasing the low side turn
VOUT
off resistor (respecting the superior limit, see sizing the turn-off gate resistor section), Using monolithicto limit high
thevoltage gate drivers
For this reason, the first solution is to turn off more softly the
dIL/dt.
IGBT, by increasing the low side turn off resistor (respecting VCC
R D ONp Pn
RGATE
CGC DC+
T
H
R
detection may react when current has
This solution may be not sufficient when in presence of a exceeded several times the rated current for normal
O
V
SH
Vcc E
operation
phase-DC+ shortinducing
circuit. faster current change at turn-off. VG
In that case the solution shown in figure 7 prevents COM pin to follow IGBT emitter filtering V the OUT
These kind of short circuits are usually broken turning off
under-Vss spike.
the low side IGBT. Short circuit detection may react when cur- V
R D
CC
ONp
R
Pn C
GATE
GC
rent has exceeded several times the rated current for normal Figure 8: Driver output protection V
in caseQof IGBT(ON) desaturation
G
L
operation inducing faster current change at turn-off. As an alternative solution a zener clamp can be placed between IGBT gate and emitter. It should
Vcc V E
NOTES: IGBT short circuit desaturation easily generate high collector dV/dt. IGBT gate is pulledFigure 9: zener protection for IGBT gate-emitter LDC- flyback
above the local supplyNOTES: IGBT short circuit desaturation easily generate high collector dV/dt. IGBT gate is pulled
by the gate-collector stray capacitance. Figure 9: zener protection for IGBT gate-emitter
above the local supply by the gate-collector stray capacitance.
In some cases (usually when turn-on resistor is low) a fast diode is needed between IGBT gate
In some cases (usually when turn-on resistor is low) a fast diode is needed between IGBT gate
and local supply to protect the driver
and local supplyoutput (figure
to protect the8).
driver output (figure 8).
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cal l +49 6102 884 311, or visit us at www.irf.com DN04-04
www.irf.com 11
11
DT04-4 revA
Using Monolithic High Voltage Gate Drivers
Using monolithic high voltage gate drivers
DT04-4
DT04-4 revA
revA Using monolithic
Using monolithic hig
DC- stray inductance (LDC-, see figure 9). Using monolithic
monolithic high
high voltage
voltage gate
gate drivers
drivers
DC+
Using DC+
DC+
V highhigh side LH
freewheeling diode. This usually happens when current V V LOAD side
driver
driver
OUT
CC
CC
LH IH
IH
A well
well known
known event that triggers Vs to go below Vss or COM is the forward biasing of the low side
flows out of theUsing monolithic high voltage gate drivers V DT04-4 revA
A event that
half-bridge triggers
towards the Vs to go below Vss or COM is the forward biasing of the low side I
VOUTVOUT LOA
freewheeling diode.
diode. This
This usually
usually happens
happens when
when current
current flows
flows outout of
of the
the half-bridge
half-bridge towards the
L
L SS LOAD
freewheeling VSS low side towards the L
load.
load. driver
load. IL IL
In
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In order to reduce the slope of current flowing in the parasiticcharge inductances may be sosuch to minimize
that a the
relevant voltage is developed be
In order to reduce the slope of current flowing in the para- 2. It is also important to notice that the current developed acro
derivative terms, RGOFF can be increased, respecting previously emitter discussed
and the VS constraints
pin. This (R voltage
GOFF may be brought to the hig
siticsizing
inductances so. to minimize the derivative terms, RGOFFwww.irf.com can 1. RVS works charge may be
in series to the such that aresistor
bootstrap relevant andvoltage
must is developed
section) through the HO-VS ESD protection diode. 13
be increased, respecting previously discussed constraints be considered in sizing the bootstrap resistance (RBOOTbe
emitter and the VS pin. This voltage may *= brought to the
through the HO-VS ESD protection diode.
(R sizing section). RBOOT+RVS).
GOFF
Resistor between Vs and Vout
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12
Using Monolithic High Voltage Gate Drivers
Rboot Dboot
DC+
VCC VB
Cboot
ON RGON
QH DH
OFF RGOFF
VSS VS RVS
QH DH
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DT04-4 revA
Using Monolithic High Voltage Gate Drivers DT04-4
Using monolithic high voltage revA
gate drivers
DT04-4 revA
DT04-4 revA
Using monolithic high voltage gate drivers
Dboot
DC+
Using monolithic high
D voltage gate drivers
DC+
DC+ DC+
RBOOT Dboot RBOOT Dboot
DC+ DC+
Dboot VCC VB Dboot VCC VB
RBOOT Cboot DC+ RBOOT Cboot DC+
ON
RBOOT Dboot RBOOT Dboot
RGOFF
CVCC CVCC
VCC VB QH DH VCC VB
Cboot Cboot QH DH
ON
VB
OFF
VB RGON
VCC VCC
VSS VS Cboot RGOFF VSS VSCboot
CVCC VB CVCC ON VB
VCC QH DH VCC
Cboot RGOFF Cboot QH DH
CVCC GATEOFF
DRIVER CVCC ON GATE DRIVER
QH DH RGON
VSS RGOFF VSS VS
CVCC VS RVS VOUT CVCC RVSQH DH VOUT
OFF QH DH RGON
VSS VSS VS DRIVER QH DH
VS
GATE DRIVER GATE
OFF
RGON
VSS VS VSS VS
GATE DRIVER RVS VOUT GATE DRIVER RVS VOUT
GATE DRIVER RVS GATE DRIVER RVS
VOUT VOUT
RVS Figure
V
12: Gate turn-on and turn-off with RVS
OUT
RVS VOUT
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DT04-4 revA
Using Monolithic High Voltage Gate Drivers
Using monolithic high voltage gate drivers DT04-
DC+ a voltage across the gate-emitterUsing monolithic
increasing high voltage
the possibility of gate
RBOOT Dboot
self turn-on effect. For this reason is strongly recommended to
place the gate resistances close together and to minimize the
IGC
loop area (see figure 14).
VB VB/ VCC
VCC gate
Cboot
ON resistance CGC
Routing and placement example
CVCC HOP/LOP
QH DH HON/LON
VSS or COM
RGON We consider, as example, the IR2214 a high voltage and high
VS
(see comments) output current gate driver, seeGate the lead
Drive assignments in figure
GATE DRIVER 15. Loop VGE
RVS VOUT Figure 16 shows one of the possible layout solutions using a
VS/COM
3 layer PCB. This example takes into account all the previous
considerations. Placement and routing for supply capacitors
Figure
and gate resistances in the14: gate
high anddrive loop side minimize
low voltage
Figure 13: Clamping structure with zener diode respectively supply path and gate drive loop. The bootstrap
Routing and placement diode is placed under the device to have the cathode as close
example
B LAYOUT TIPS
Supply capacitors as possible to bootstrap capacitor and the anode far from high
ance from high to low voltage We consider, as example, voltagethe
andIR2214
close to aVCChigh
. voltage and high output current gate driver
lead assignments
If the output stages are able to quickly turn on IGBT with in figure 15.
minimize the noise coupled between the signals referred to ground and those floating its
high
gly recommended to value of current,
place the supply
components tied to capacitors must in
floating voltage bethe
placed
high as
voltage side of HIN 1 24 DSH
ce (VB, VS side)close
while as
thepossible
other components in the opposite side.
to the device pins (VCC and VSS for the ground LIN VB
tied supply, VB and VS for the floating supply) in order to mini- FLT_CLR N.C.
und plane
mize parasitic inductance/resistance. SY_FLT HOP
FAULT/SD HON
nd plane must not be placed under or nearby the high voltage floating side to minimize noise
SSOP24
VSS VS
ling.
Gate drive loops SSDL SSDH
LON N.C.
Current loops behave like an antenna able to receive and
e output stages are able to quickly turn on IGBT with high value of current, the supply LOP N.C.
Gate Drive
Loop VGE
VS/COM
R2 D2
VGH DC+
R3
C1
R4 VEH
IR2214
D1
R5
D3 Phase VCC R1
VGL
R6 C2
R7 VEL
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