Newspaper Vending Machine

Controller Design Specification

Consider a newspaper vending machine like those found at many street corners.
Newspapers cost 35 cents, and the machine accepts nickels, dimes and quarters. When
enough money has been deposited, the machine unlocks a door which allows the buyer to
retrieve a newspaper, and returns change if necessary. You will design the control logic
for this vending machine as a finite-state machine using D flip-flops.

The coin slot mechanism detects which coin has been deposited, and produces two
signals A and B that represent the value of the coin as shown in the table below. Invalid
coins are pennies, foreign currency, etc., and are immediately returned to the buyer.

Coin A B
No coin deposited, or invalid coin 0 0
Nickel 0 1
Dime 1 0
Quarter 1 1

When a valid coin is inserted, the values of A and B are asserted as shown above, and are
reset to zero after the next rising edge of the clock. This prevents the signals A and B
from being asserted for more than one clock cycle when a single coin is inserted.

Your FSM will take A and B as inputs, and produce outputs V and C. A rising edge on V
(vend) will cause the door lock to open, and the lock will remain open until the buyer
closes the door. It is not necessary to assert V for more than one clock cycle in order to
do this.

The output C is normally 1. If C is 0 on the rising edge of the clock, then a nickel will be
returned as change. If the buyer deposits more than 35 cents, then your FSM must return
the difference in nickels. You may assume that there is an inexhaustible supply of
nickels available for change.

1. Draw a state transition diagram for your design.

2. Choose a suitable state assignment.
3. Determine the state transition table. Include the excitations for JK flip-flops.
4. Determine the state and output logic.
5. Draw the circuit schematic.
 State Transition Diagram
1. Nickel Deposits.
Note that states are labeled with the output values VC, and transitions are labeled with the input values AB.
Also note that for states Reset, 5c, , 30c, FSM remains in that state when AB=00, but this is not shown in the diagram.

Reset
01 01

5c
01 01

10c
01 01
XX
15c
01

20c 01
01

Open 25c 01
11 01

01 30c 01
01
2. Making Change.
The buyer may deposit as much as 55 cents total, so the FSM must be able to return up to 20 cents change.
Once the total deposited exceeds 35 cents, change is returned no matter what the inputs are.

Reset
01 01

55c 5c
XX 00 01 01

50c 10c
XX 00 01 01
XX
45c 15c
00 01

XX 40c 20c 01
00 01

XX Open 25c 01
11 01

01 30c 01
01
3. Dime Deposits.

Reset
10
01 01

55c 5c
10
XX 00 01 01

50c 10c
XX 00 01 01
XX
45c 15c
10
00 01

XX 40c 20c 01
00 01

XX Open 25c 01
10 10
11 01

01 30c 01
10 10
01
4. Quarter Deposits

Reset
10
01 01

55c 5c
10
XX 00 01 01

50c 10c
XX 00 01 01
XX 11
45c 15c
10
00 01

XX 40c 11 11 20c 01
00 11 11 01

XX Open 25c 01
10 10
11 01

01 30c 01
10 10
01
11

11
 State Transition Table
Present Next State Outputs
State AB=00 AB=01 AB=10 AB=11 VC
Reset Reset 5c 10c 25c 01
5c 5c 10c 15c 30c 01
10c 10c 15c 20c Open 01
15c 15c 20c 25c 40c 01
20c 20c 25c 30c 45c 01
25c 25c 30c Open 50c 01
30c 30c Open 40c 55c 01
Open Reset Reset Reset Reset 11
40c Open Open Open Open 00
45c 40c 40c 40c 40c 00
50c 45c 45c 45c 45c 00
55c 50c 50c 50c 50c 00

State Assignment
State Q3 Q2 Q1 Q0
Reset 0 0 0 0
5c 0 0 0 1
10c 0 0 1 1
15c 0 1 0 1
20c 0 1 0 0
25c 1 0 1 0
30c 1 1 1 1
Open 1 1 1 0
40c 1 0 1 1
45c 1 1 0 1
50c 1 1 0 0
55c 1 0 0 0
 State Assigned Table
Present Next State Outputs
State AB=00 AB=01 AB=10 AB=11 VC
0000 0000 0001 0011 1010 01
0001 0001 0011 0101 1111 01
0010 XXXX XXXX XXXX XXXX XX
0011 0011 0101 0100 1110 01
0100 0100 1010 1111 1101 01
0101 0101 0100 1010 1011 01
0110 XXXX XXXX XXXX XXXX XX
0111 XXXX XXXX XXXX XXXX XX
1000 1100 1100 1100 1100 00
1001 XXXX XXXX XXXX XXXX XX
1010 1010 1111 1110 1100 01
1011 1110 1110 1110 1110 00
1100 1101 1101 1101 1101 00
1101 1011 1011 1011 1011 00
1110 0000 0000 0000 0000 11
1111 1111 1110 1011 1000 01
 State logic for D3

Q1Q0 Q1Q0
Q3Q2 00 01 11 10 Q3Q2 00 01 11 10

00 0 0 0 X 00 0 0 0 X
01 0 0 X X 01 1 0 X X
11 1 1 1 0 11 1 1 1 0
10 1 X 1 1 10 1 X 1 1

AB=00 AB=01
Q1Q0 Q1Q0
Q3Q2 00 01 11 10 Q3Q2 00 01 11 10

00 0 0 0 X 00 1 1 1 X
01 1 1 X X 01 1 1 X X
11 1 1 1 0 11 1 1 1 0
10 1 X 1 1 10 1 X 1 1

AB=10 AB=11

D = Q Q + Q Q + Q Q + A Q Q + AB Q + B Q Q Q
3 3 2 3 1 3 0 3 2 3 3 2 0
= Q Q + Q + Q + Q A Q + B + BQ Q
3 2 1 0 3 2 2 0
 State Logic for D2

Q1Q0 Q1Q0
00 01 11 10 00 01 11 10
Q3Q2 Q3Q2
00 0 0 0 X 00 0 0 1 X
01 1 1 X X 01 0 1 X X
11 1 0 1 0 11 1 0 1 0
10 1 X 1 0 10 1 X 1 1

AB=00 AB=01
Q1Q0 Q1Q0
00 01 11 10 00 01 11 10
Q3Q2 Q3Q2
00 0 1 1 X 00 0 1 1 X
01 1 0 X X 01 1 0 X X
11 1 0 0 0 11 1 0 0 0
10 1 X 1 1 10 1 X 1 1

AB=10 AB=11

D = Q Q Q + A Q Q Q + A Q Q Q + B Q Q Q + AQ Q
2 3 1 0 3 2 0 3 1 0 3 2 0 2 0
+ A Q Q + B Q Q + AQ Q Q
2 1 2 1 2 1 0
= Q A Q + Q + BQ + Q Q B Q + A Q + Q A Q
2 0 1 1 2 0 3 1 0 3
+ Q Q Q + Q A Q
3 1 0 1 0
 State Logic for D1
Q1Q0 Q1Q0
00 01 11 10 00 01 11 10
Q3Q2 Q3Q2
00 0 0 1 X 00 0 1 0 X
01 0 0 X X 01 1 0 X X
11 0 1 1 0 11 0 1 1 0
10 0 X 1 1 10 0 X 1 1

AB=00 AB=01
Q1Q0 Q1Q0
00 01 11 10 00 01 11 10
Q3Q2 Q3Q2
00 1 0 0 X 00 1 1 1 X
01 1 1 X X 01 0 1 X X
11 0 1 1 0 11 0 1 0 0
10 0 X 1 1 10 0 X 1 0

AB=10 AB=11
D = A B Q Q + AQ Q + Q Q Q + AQ Q Q + B Q Q + B Q Q Q
1 1 0 3 0 3 2 0 3 2 1 3 0 3 2 1
+ AB Q Q Q + B Q Q Q + A B Q Q + AQ Q Q + AB Q Q
3 2 0 2 1 0 3 0 2 1 0 3 2
= Q Q Q (A ) + Q Q Q B AQ + Q Q Q (A B)
3 2 0 3 2 0 1 3 2 0
+ Q Q Q A B Q + A Q + Q Q Q ABQ + Q Q Q (1)
3 2 0 1 1 3 2 0 1 3 2 0
+ Q Q Q (0) + Q Q Q AB + Q
3 2 0 3 2 0 1
 State Logic for D0

Q 1Q 0 Q1 Q0
00 01 11 10 00 01 11 10
Q3Q2 Q3 Q2
00 0 1 1 X 00 1 1 1 X
01 0 1 X X 01 0 0 X X
11 1 1 1 0 11 1 1 0 0
10 0 X 0 0 10 0 X 0 1

AB=00 AB=01
Q 1Q 0 Q1 Q0
00 01 11 10 00 01 11 10
Q3Q2 Q3 Q2
00 1 1 0 X 00 0 1 0 X
01 1 0 X X 01 1 1 X X
11 1 1 1 0 11 1 1 0 0
10 0 X 0 0 10 0 X 0 0

AB=10 AB=11

D = Q + Q + Q Q + Q + Q A + B + Q + Q A + B + Q + Q
0 3 2 1 3 2 0 3 0 3 2
B + Q + Q B + Q + Q A + Q + Q A + B + Q + Q + Q
1 0 2 1 2 1 3 2 0
A + B + Q + Q
2 0
= Q + Q + Q Q B + Q + Q A + Q Q + Q + A + B A + B + Q
3 2 1 0 0 1 3 3 2 0
B + Q + Q A + Q + Q B + Q
2 1 2 1 0
 Output Logic for V

Q1 Q0
00 01 11 10
Q3Q2
00 0 0 0 X
01 0 0 X X
11 0 0 0 1
10 0 X 0 0

AB=11

V =Q Q Q
2 1 0

Output Logic for C

Q1 Q0
00 01 11 10
Q3Q2
00 1 1 1 X
01 1 1 X X
11 0 0 1 1
10 0 X 0 1

AB=11

C = Q +Q Q +Q Q
3 2 1 1 0
 Final Design
Q2
Q1
Q0 Q3
B D3 SET
Q3
D Q
Q2 Q3
A
CLR Q
B
Q2
Q0

A
Q0
Q1 Q2
B
Q1 0
Q0
B 1
Q3
0
A 1
D2 SET
Q2
D Q
Q1
A
Q3 Q3
CLR Q

A Q0 0
1
Q0
Q2
A Q3
Q1 Q2
Q0 C
B
A
B Q1 A 0
1
A 2
1 D1 Q1
B A 0
3
D
SET
Q V
4
Q1 1 5

A 0 6
CLR Q
7
B
Q1

Q3
Q1
Q0
Q2
B
Q1
A
Q3 Q0 B D0 SET
Q0
A Q2 D Q
Q3 Q1
B Q2 CLR Q
Q0
A A
B Q1
B CLK
Q0 Q2
 State Transition Table
Present Next State Outputs
State AB=00 AB=01 AB=10 AB=11 VC
Reset Reset 5c 10c 25c 01
5c 5c 10c 15c 30c 01
10c 10c 15c 20c Open 01
15c 15c 20c 25c 40c 01
20c 20c 25c 30c 45c 01
25c 25c 30c Open 50c 01
30c 30c Open 40c 55c 01
Open Reset Reset Reset Reset 11
40c Open Open Open Open 00
45c 40c 40c 40c 40c 00
50c 45c 45c 45c 45c 00
55c 50c 50c 50c 50c 00

One-Hot State Assignment

State Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Reset 0 0 0 0 0 0 0 0 0 0 0 1
5c 0 0 0 0 0 0 0 0 0 0 1 0
10c 0 0 0 0 0 0 0 0 0 1 0 0
15c 0 0 0 0 0 0 0 0 1 0 0 0
20c 0 0 0 0 0 0 0 1 0 0 0 0
25c 0 0 0 0 0 0 1 0 0 0 0 0
30c 0 0 0 0 0 1 0 0 0 0 0 0
Open 0 0 0 0 1 0 0 0 0 0 0 0
40c 0 0 0 1 0 0 0 0 0 0 0 0
45c 0 0 1 0 0 0 0 0 0 0 0 0
50c 0 1 0 0 0 0 0 0 0 0 0 0
55c 1 0 0 0 0 0 0 0 0 0 0 0
 State Assigned Table
Hot Present Next State Outputs
Bit State AB=00 AB=01 AB=10 AB=11 VC
Q0 000000000001 000000000001 000000000010 000000000100 000000100000 01
Q1 000000000010 000000000010 000000000100 000000001000 000001000000 01
Q2 000000000100 000000000100 000000001000 000000010000 000010000000 01
Q3 000000001000 000000001000 000000010000 000000100000 000100000000 01
Q4 000000010000 000000010000 000000100000 000001000000 001000000000 01
Q5 000000100000 000000100000 000001000000 000010000000 010000000000 01
Q6 000001000000 000001000000 000010000000 000100000000 100000000000 01
Q7 000010000000 000000000001 000000000001 000000000001 000000000001 11
Q8 000100000000 000010000000 000010000000 000010000000 000010000000 00
Q9 001000000000 000100000000 000100000000 000100000000 000100000000 00
Q10 010000000000 001000000000 001000000000 001000000000 001000000000 00
Q11 100000000000 010000000000 010000000000 010000000000 010000000000 00
 State and Output Logic for the One-Hot State Assignment
The state logic expressions can be found without K-maps. For example, note that from
state 000010000000 (Open) the next state is always 000000000001 (Reset), for any input
values. The only other way to reach state 000000000001 is from the same state when the
inputs are AB = 00.
D = Q + Q AB
0 7 0

The state logic for the other flip-flops expressions can be found in similar fashion.
D = Q AB + Q AB
1 1 0
D = Q AB + Q AB + Q AB
2 2 1 0
D = Q AB + Q AB + Q AB
3 3 2 1
D = Q AB + Q AB + Q AB
4 4 3 2
D = Q AB + Q AB + Q AB +Q AB
5 5 4 3 0
D = Q AB + Q AB + Q AB +Q AB
6 6 5 4 1
Note the pattern in the expressions for D1 through D6. Each could be implemented by a
4:1 MUX with A and B as the select inputs.

The state logic for D7 is more complicated because there are seven different present state
and input combinations that lead to state 000010000000 as the next state.
D = Q + Q AB + Q AB + Q AB
7 8 6 5 2

Similarly,
D = Q + Q AB + Q AB
8 9 6 3
D = Q + Q AB
9 10 4
D = Q AB
10 6
The output logic can also be determined by inspection. The output V = 1 if and only if
the FSM is in state 000010000000 (Open). The output C = 1 if the FSM is in any of the
states 000000000001 (Reset) through 000010000000 (Open). Therefore,
V =Q
7
C = Q +Q +Q +Q +Q +Q +Q +Q
0 1 2 3 4 5 6 7

The added cost of the extra flip-flops for this one-hot state assignment is clearly worth it,
given the reduction in complexity of the state logic.