Sumanth.

Mobile: +917204093366 Email: prattipatisumanth555@gmail.com

OBJECTIVE: Well versed in physical design implementation of chips and digital signal processors. Looking for an
opportunity to work as a physical design engineer in a dynamic work environment .

Self-DESCRIPTION: Self-starter, driven by passion for physical design, inclined to finding innovative solutions,
enjoying teamwork and effective in taking feedback from co-workers.

Executive Summary

A result focused professional with 1 year 10 months of industrial experience in physical design with including
Internship.
Currently associated with Chaologix Technologies India pvt. Ltd. As a physical design engineer.
I have worked with multiple technology nodes ranging from 65nm and 180nm.
Worked on P&R of complex block
Worked on Flat full chip implementation and Block level implementation.
Good Knowledge on physical layout development and Verification (DRC, LVS).
Expertise on reliability verification flows which include IR drop analysis and EM fixes.
Proficiency in PVS for physical verification and gained experience on cadence tool flow.

Core Competencies:

Physical design.
Physical Verification.

Technical skills:

Place and Routing : Cadence Encounter 13.1v.

Signal Integrity : Primetime- SI.
RC Extraction : Star RC-XT, Quantus(QRC).
Static Timing Analysis : Encounter Timing System, Prime Time.
Physical Verification : Assura, PVS (DRC, LVS).
Languages : Verilog, System Verilog, C.

EDA Proficiency:

Layout tools : Cadence Virtuoso.

Verification tools : Assura and PVS.

Place and Route : Cadence Encounter 13.1v.

Operating Systems : Solaris, Linux & Windows.

Career Profile:

Organization Duration Responsibilities

ChaoLogix Technologies India pvt. Ltd.

July 2015 to December2015 5months of experience in STA AND physical
Hyderabad design Domains.

ChaoLogix Technologies India pvt. Ltd.

January 2016 - Present 1 Year 4 months of experience in Physical
Hyderabad Design Domain
-From Netlist to GDSII.
-Physical Verification and Timing

Academic Credentials:

Year of
Class/Course Name of Institute Board/University Marks%
Passing

MSc School of Manipal Academy of Higher CGPA

2015
(VLSI Design) Information Science Education (MAHE), Manipal 7.6

B-Tech VRS & YRN College of

Jawaharlal Nehru Technological
(Electronics & Engineering and 2013 67.4
University, Kakinada.
Communication) Technology, Chirala

Vignana Bharathi
Board of Intermediate Education,
Intermediate Junior College, Chirala. 2009 72.4
AP.

Sarada Public School, Board of Secondary Education,

SSC 2007 80
Parchoor. AP.
Extra Curricular Activities:

Seminar on Universal Verification Methodology.

Seminar on A1CSA: Energy Efficient Fast Adder Architecture for Cell Based VLSI Design.
Paper presentation on MOTES.
Participated in PYTHON WORK SHOP.

Key Performance Areas/Professional Projects:

1)Project Name: AES CORE Light Weight (Feb 2016 to August 2016)

Client: ChaoLogix Technologies India PVT.LTD.

Technology node: 65nm

Environment: Cadence Encounter 13.1v, Encounter Timing System, PVS, Conformal, Quantus(QRC).

Responsibilities: Complete Place and Route and ECO flows (RTL GDSII) including Block Level STA and physical

Verification and Logical Equivalence check.

2)Project Name: AES CORE High Speed (Oct 2016 to Feb 2017)

Client: ChaoLogix Technologies India PVT.LTD.

Technology node: 65nm

Environment: Cadence Encounter 13.1v, Encounter Timing System, PVS, Conformal, Quantus(QRC).

Responsibilities: Complete Place and Route and ECO flows (RTL GDSII) including Block Level STA and physical

Verification and Logical Equivalence check.

Academic Projects:

1)Project Name: 32 Bit Full Adder Place& Route using Cadence Encounter 13.1v

Client: School of information science Manipal.

Technology Node: 180nm

Environment: Cadence Encounter 13.1v

Responsibilities: Developed RTL code for 32-bit Full adder. By Logic Synthesis generated net list and imported design

libraries. IO placement and block placement has been done Power planning and Routing. Cell placement, Pre CTS.CTS

(Clock Tree Synthesis) and post CTS. Performed Pre-Routing and post routing. STA (Static Timing Analysis)
2)Project Name: Redefining CMOS Logic Style for Sub Threshold Operation.

Client: School of information science Manipal.

Technology Node: 180nm

Environment: Cadence Virtuoso, Assura, QRC.

Project Description: In this work, a new CMOS logic style, that results in reduced leakage Currents both in active and

idle modes of operation leading to a better Static and dynamic performance, is proposed. Logic styles, such as

Transmission gates, NAND, 1-bit Full adder digital circuits. It is implemented on 180nm and 90nm by using cadence.

Responsibilities: Developed the Circuit for NAND gates and 1bit Full adder digital circuits did simulation and verify voltage,

leakage currents and calculate the rise & fall time and power dissipation.

Personal Particulars:

Date of birth : 11-05-1992

Language proficiency : English, Telugu.

Permanent address : D.no 1-98\2, Devarapalli, Parchoor (mandal), Prakasham district, A.P. India.

Reference : Available on request