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R2
transferred into a bit pattern in a single clock domain
Fig. 1. FPGA-based ADC immediately and only one set of edge detect, pulse filter and
count latch circuit is used. The meta-stability is limited at the
The analog inputs are directly connected to the FPGA input
sampling stage only and in fact, the meta-stability in sampling
stage does no harm but carrying the input signal arrival time
Manuscript received October 30, 2007. This work was supported in part information. The decoding becomes very simple in our
by Universities Research Association Inc. under Contract No. DE-AC02- design. The detail is described in Section II.
76CH03000 with the United States Department of Energy. The TDC in FPGA alone is already very useful. The TDC
The authors are with Fermi National Accelerator Laboratory, Batavia, IL
60510 USA (phone: 630-840-8911; fax: 630-840-2950; e-mail: jywu168@ card designed for Fermilab MIPP upgrade project is
fnal.gov).
documented in this paper. transfer registers in the FPGA as shown in Fig. 3. This
The multi-sampling structure can have other applications. A symmetric placement assures equal propagation delays from
deserializer circuit known as Digital Phase Follower (DPF) input buffer to the sampling registers, resulting in uniform bin
is also documented. Using DPF, any FPGA input can be used widths and thus minimizes differential non-linearity.
to receive serial data without needing dedicated deserializer
that is only available in high-end FPGA families. The DPF
can compensate input data phase drift not only due to cable
4Ch
temperature variation, but also due to crystal oscillator
frequency difference between transmitter and receiver.
64
56
48
40
32
24
16
0
0 32 64 96 128 160 192 224 256 (a)
(a) Leading Ramp Trailing Ramp
2.5
2
V
2
1.5
V
1.5
1
0 32 64 96 128 160 192 224 256
1
(b)
2500 3000 3500 4000 4500 5000 5500 Fig. 7. (a) Input waveform (b) Digitized waveform
t(ns) Passive components are chosen for the ramping reference
(b) voltage generation network primarily for simplicity. The
Fig. 5. (a) Raw data from TDC (b) Digitized waveform
ramping voltage from passive RC network is intrinsically non-
It should be pointed out that the TDC values represent not
linear which sometimes is viewed as a disadvantage. In
only the voltage levels at the sampling points, but also the
FPGA, however, correcting nonlinearity is merely a transform
sampling times. In high precision applications, the differences
via a look-up table. In our example here, the exponential
of the sampling times should be taken into account but it is not
voltage ramp can be further used to increase measurement
too difficult to do so.
dynamic range, which becomes an advantage.
B. Exponential Reference Voltage In many applications, only relative precision in a
The exponential discharge property of the RC networks can measurement is needed, i.e., finer measurements are only
be used to increase the dynamic range of the ADC. In the needed for small signals while for larger signals, coarser
second configuration, the values of R1 = 50 , R2 = 100 and measurements are sufficient.
C = 150pF. The reference voltage shown in Fig. 6 has a short
time constant. IV. THE ENCLOSED LOOP MICRO-SEQUENCER
A 96-channel TDC card is designed for the Fermilab MIPP
experiment electronics upgrade project as shown in Fig. 8.
Q0 Selected
Sample Newer Samples SEL was 3 SEL is 0
QF SEL Fig. 11. The Digital Phase Following Processes
VI. CONCLUSION
Multi-sampling based TDC has been studied, implemented
in low cost FPGA and bench tested.
Three applications: multi-channel FPGA-only TDC, FPGA-
only ADC and a deserializer Digital Phase Follower are
discussed. Interfacing FPGA directly with the continuous
variables (arrival time and input voltage) eliminates external
devices and simplifies system design. The measurement made
can be processed immediately in the FPGA without having to
pass data via on board busses.
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